56 typedef enum endpoint_parameter{ep_num, ep_type, ep_direction, ep_size, ep_bank, nyet_status} t_endpoint_parameter;
72 #define PIPE_CONTROL 0
83 #define MSK_EP_DIR 0x7F
85 #define MSK_EPTYPE 0xC0
86 #define MSK_EPSIZE 0x70
88 #define MSK_DTSEQ 0x0C
89 #define MSK_NBUSYBK 0x03
90 #define MSK_CURRBK 0x03
91 #define MSK_DAT 0xFF // UEDATX
92 #define MSK_BYCTH 0x07 // UEBCHX
93 #define MSK_BYCTL 0xFF // UEBCLX
94 #define MSK_EPINT 0x7F // UEINT
95 #define MSK_HADDR 0xFF // UHADDR
98 #define MSK_PNUM 0x07 // UPNUM
99 #define MSK_PRST 0x7F // UPRST
100 #define MSK_PTYPE 0xC0 // UPCFG0X
101 #define MSK_PTOKEN 0x30
102 #define MSK_PEPNUM 0x0F
103 #define MSK_PSIZE 0x70 // UPCFG1X
106 #define MSK_NBUSYBK 0x03
108 #define MSK_ERROR 0x1F
110 #define MSK_PTYPE 0xC0 // UPCFG0X
111 #define MSK_PTOKEN 0x30
112 #define MSK_TOKEN_SETUP 0x30
113 #define MSK_TOKEN_IN 0x10
114 #define MSK_TOKEN_OUT 0x20
115 #define MSK_PEPNUM 0x0F
117 #define MSK_PSIZE 0x70 // UPCFG1X
123 #define TYPE_CONTROL 0
124 #define TYPE_ISOCHRONOUS 1
126 #define TYPE_INTERRUPT 3
129 #define DIRECTION_OUT 0
130 #define DIRECTION_IN 1
148 #define NYET_ENABLED 0
149 #define NYET_DISABLED 1
152 #define TOKEN_SETUP 0
156 #define Is_ep_addr_in(x) ( (x&0x80)? TRUE : FALSE)
163 #define Usb_build_ep_config0(type, dir, nyet) ((type<<6) | (dir))
164 #define Usb_build_ep_config1(size, bank ) ((size<<4) | (bank<<2) )
165 #define usb_configure_endpoint(num, type, dir, size, bank, nyet) \
166 ( Usb_select_endpoint(num), \
167 usb_config_ep(Usb_build_ep_config0(type, dir, nyet),\
168 Usb_build_ep_config1(size, bank) ))
170 #define Host_build_pipe_config0(type, token, ep_num) ((type<<6) | (token<<4) | (ep_num))
171 #define Host_build_pipe_config1(size, bank ) ((size<<4) | (bank<<2) )
172 #define host_configure_pipe(num, type, token,ep_num, size, bank, freq) \
173 ( Host_select_pipe(num), \
174 Host_set_interrupt_frequency(freq), \
175 host_config_pipe(Host_build_pipe_config0(type, token, ep_num),\
176 Host_build_pipe_config1(size, bank) ))
184 #define Usb_enable_regulator() (UHWCON |= (1<<UVREGE))
186 #define Usb_disable_regulator() (UHWCON &= ~(1<<UVREGE))
188 #define Is_usb_regulator_enabled() ((UHWCON & (1<<UVREGE)) ? TRUE : FALSE)
196 #define Usb_enable_uid_pin() (UHWCON |= (1<<UIDE))
198 #define Usb_disable_uid_pin() (UHWCON &= ~(1<<UIDE))
200 #define Usb_force_device_mode() (Usb_disable_uid_pin(), UHWCON |= (1<<UIMOD))
202 #define Usb_force_host_mode() (Usb_disable_uid_pin(), UHWCON &= ~(1<<UIMOD))
204 #define Usb_enable_uvcon_pin() (UHWCON |= (1<<UVCONE))
206 #define Usb_disable_uvcon_pin() (UHWCON &= ~(1<<UVCONE))
208 #define Usb_full_speed_mode() (UDCON &= ~(1<<LSM))
210 #define Usb_low_speed_mode() (UDCON |= (1<<LSM))
213 #define Usb_enable() (USBCON |= ((1<<USBE) | (1<<OTGPADE)))
215 #define Usb_disable() (USBCON &= ~((1<<USBE) | (1<<OTGPADE)))
216 #define Is_usb_enabled() ((USBCON & (1<<USBE)) ? TRUE : FALSE)
219 #define Usb_enable_vbus_pad() (USBCON |= (1<<OTGPADE))
221 #define Usb_disable_vbus_pad() (USBCON &= ~(1<<OTGPADE))
223 #define Usb_select_device() (USBCON &= ~(1<<HOST))
224 #define Usb_select_host() (USBCON |= (1<<HOST))
225 #define Is_usb_host_enabled() ((USBCON & (1<<HOST)) ? TRUE : FALSE)
228 #define Usb_freeze_clock() (USBCON |= (1<<FRZCLK))
229 #define Usb_unfreeze_clock() (USBCON &= ~(1<<FRZCLK))
230 #define Is_usb_clock_freezed() ((USBCON & (1<<FRZCLK)) ? TRUE : FALSE)
232 #define Usb_enable_id_interrupt() (USBCON |= (1<<IDTE))
233 #define Usb_disable_id_interrupt() (USBCON &= ~(1<<IDTE))
234 #define Is_usb_id_interrupt_enabled() ((USBCON & (1<<IDTE)) ? TRUE : FALSE)
235 #define Is_usb_id_device() ((USBSTA & (1<<ID)) ? TRUE : FALSE)
236 #define Usb_ack_id_transition() (USBINT = ~(1<<IDTI))
237 #define Is_usb_id_transition() ((USBINT & (1<<IDTI)) ? TRUE : FALSE)
239 #define Usb_enable_vbus_interrupt() (USBCON |= (1<<VBUSTE))
240 #define Usb_disable_vbus_interrupt() (USBCON &= ~(1<<VBUSTE))
241 #define Is_usb_vbus_interrupt_enabled() ((USBCON & (1<<VBUSTE)) ? TRUE : FALSE)
242 #define Is_usb_vbus_high() ((USBSTA & (1<<VBUS)) ? TRUE : FALSE)
243 #define Is_usb_vbus_low() ((USBSTA & (1<<VBUS)) ? FALSE : TRUE)
244 #define Usb_ack_vbus_transition() (USBINT = ~(1<<VBUSTI))
245 #define Is_usb_vbus_transition() ((USBINT & (1<<VBUSTI)) ? TRUE : FALSE)
248 #define Usb_get_general_interrupt() (USBINT & (USBCON & MSK_IDTE_VBUSTE))
250 #define Usb_ack_all_general_interrupt() (USBINT = ~(USBCON & MSK_IDTE_VBUSTE))
251 #define Usb_ack_cache_id_transition(x) ((x) &= ~(1<<IDTI))
252 #define Usb_ack_cache_vbus_transition(x) ((x) &= ~(1<<VBUSTI))
253 #define Is_usb_cache_id_transition(x) (((x) & (1<<IDTI)) )
254 #define Is_usb_cache_vbus_transition(x) (((x) & (1<<VBUSTI)))
257 #define Usb_get_otg_interrupt() (OTGINT & OTGIEN)
259 #define Usb_ack_all_otg_interrupt() (OTGINT = ~OTGIEN)
260 #define Is_otg_cache_bconnection_error(x) (((x) & MSK_BCERRI))
261 #define Usb_ack_cache_bconnection_error(x) ((x) &= ~MSK_BCERRI)
263 #define Usb_enter_dpram_mode() (UDPADDH = (1<<DPACC))
264 #define Usb_exit_dpram_mode() (UDPADDH = (U8)~(1<<DPACC))
265 #define Usb_set_dpram_address(addr) (UDPADDH = (1<<DPACC) + ((Uint16)addr >> 8), UDPADDL = (Uchar)addr)
266 #define Usb_write_dpram_byte(val) (UEDATX=val)
267 #define Usb_read_dpram_byte() (UEDATX)
270 #define Usb_enable_vbus() (OTGCON |= (1<<VBUSREQ))
272 #define Usb_disable_vbus() (OTGCON |= (1<<VBUSRQC))
274 #define Usb_enable_manual_vbus() (PORTE|=0x80,DDRE|=0x80,Usb_disable_uvcon_pin())
277 #define Usb_device_initiate_hnp() (OTGCON |= (1<<HNPREQ))
279 #define Usb_host_accept_hnp() (OTGCON |= (1<<HNPREQ))
281 #define Usb_host_reject_hnp() (OTGCON &= ~(1<<HNPREQ))
283 #define Usb_device_initiate_srp() (OTGCON |= (1<<SRPREQ))
285 #define Usb_select_vbus_srp_method() (OTGCON |= (1<<SRPSEL))
287 #define Usb_select_data_srp_method() (OTGCON &= ~(1<<SRPSEL))
289 #define Usb_enable_vbus_hw_control() (OTGCON &= ~(1<<VBUSHWC))
291 #define Usb_disable_vbus_hw_control() (OTGCON |= (1<<VBUSHWC))
293 #define Is_usb_vbus_enabled() ((OTGCON & (1<<VBUSREQ)) ? TRUE : FALSE)
295 #define Is_usb_hnp() ((OTGCON & (1<<HNPREQ)) ? TRUE : FALSE)
297 #define Is_usb_device_srp() ((OTGCON & (1<<SRPREQ)) ? TRUE : FALSE)
300 #define Usb_enable_suspend_time_out_interrupt() (OTGIEN |= (1<<STOE))
302 #define Usb_disable_suspend_time_out_interrupt() (OTGIEN &= ~(1<<STOE))
303 #define Is_suspend_time_out_interrupt_enabled() ((OTGIEN & (1<<STOE)) ? TRUE : FALSE)
305 #define Usb_ack_suspend_time_out_interrupt() (OTGINT &= ~(1<<STOI))
307 #define Is_usb_suspend_time_out_interrupt() ((OTGINT & (1<<STOI)) ? TRUE : FALSE)
310 #define Usb_enable_hnp_error_interrupt() (OTGIEN |= (1<<HNPERRE))
312 #define Usb_disable_hnp_error_interrupt() (OTGIEN &= ~(1<<HNPERRE))
313 #define Is_hnp_error_interrupt_enabled() ((OTGIEN & (1<<HNPERRE)) ? TRUE : FALSE)
315 #define Usb_ack_hnp_error_interrupt() (OTGINT &= ~(1<<HNPERRI))
317 #define Is_usb_hnp_error_interrupt() ((OTGINT & (1<<HNPERRI)) ? TRUE : FALSE)
320 #define Usb_enable_role_exchange_interrupt() (OTGIEN |= (1<<ROLEEXE))
322 #define Usb_disable_role_exchange_interrupt() (OTGIEN &= ~(1<<ROLEEXE))
323 #define Is_role_exchange_interrupt_enabled() ((OTGIEN & (1<<ROLEEXE)) ? TRUE : FALSE)
325 #define Usb_ack_role_exchange_interrupt() (OTGINT &= ~(1<<ROLEEXI))
327 #define Is_usb_role_exchange_interrupt() ((OTGINT & (1<<ROLEEXI)) ? TRUE : FALSE)
330 #define Usb_enable_bconnection_error_interrupt() (OTGIEN |= (1<<BCERRE))
332 #define Usb_disable_bconnection_error_interrupt() (OTGIEN &= ~(1<<BCERRE))
333 #define Is_bconnection_error_interrupt_enabled() ((OTGIEN & (1<<BCERRE)) ? TRUE : FALSE)
335 #define Usb_ack_bconnection_error_interrupt() (OTGINT &= ~(1<<BCERRI))
337 #define Is_usb_bconnection_error_interrupt() ((OTGINT & (1<<BCERRI)) ? TRUE : FALSE)
340 #define Usb_enable_vbus_error_interrupt() (OTGIEN |= (1<<VBERRE))
342 #define Usb_disable_vbus_error_interrupt() (OTGIEN &= ~(1<<VBERRE))
343 #define Is_vbus_error_interrupt_enabled() ((OTGIEN & (1<<VBERRE)) ? TRUE : FALSE)
345 #define Usb_ack_vbus_error_interrupt() (OTGINT &= ~(1<<VBERRI))
347 #define Is_usb_vbus_error_interrupt() ((OTGINT & (1<<VBERRI)) ? TRUE : FALSE)
350 #define Usb_enable_srp_interrupt() (OTGIEN |= (1<<SRPE))
352 #define Usb_disable_srp_interrupt() (OTGIEN &= ~(1<<SRPE))
353 #define Is_srp_interrupt_enabled() ((OTGIEN & (1<<SRPE)) ? TRUE : FALSE)
355 #define Usb_ack_srp_interrupt() (OTGINT &= ~(1<<SRPI))
357 #define Is_usb_srp_interrupt() ((OTGINT & (1<<SRPI)) ? TRUE : FALSE)
365 #define Usb_initiate_remote_wake_up() (UDCON |= (1<<RMWKUP))
367 #define Usb_detach() (UDCON |= (1<<DETACH))
369 #define Usb_attach() (UDCON &= ~(1<<DETACH))
371 #define Is_usb_pending_remote_wake_up() ((UDCON & (1<<RMWKUP)) ? TRUE : FALSE)
373 #define Is_usb_detached() ((UDCON & (1<<DETACH)) ? TRUE : FALSE)
376 #define Usb_get_device_interrupt() (UDINT & (1<<UDIEN))
378 #define Usb_ack_all_device_interrupt() (UDINT = ~(1<<UDIEN))
381 #define Usb_enable_remote_wake_up_interrupt() (UDIEN |= (1<<UPRSME))
383 #define Usb_disable_remote_wake_up_interrupt() (UDIEN &= ~(1<<UPRSME))
384 #define Is_remote_wake_up_interrupt_enabled() ((UDIEN & (1<<UPRSME)) ? TRUE : FALSE)
386 #define Usb_ack_remote_wake_up_start() (UDINT = ~(1<<UPRSMI))
388 #define Is_usb_remote_wake_up_start() ((UDINT & (1<<UPRSMI)) ? TRUE : FALSE)
391 #define Usb_enable_resume_interrupt() (UDIEN |= (1<<EORSME))
393 #define Usb_disable_resume_interrupt() (UDIEN &= ~(1<<EORSME))
394 #define Is_resume_interrupt_enabled() ((UDIEN & (1<<EORSME)) ? TRUE : FALSE)
396 #define Usb_ack_resume() (UDINT = ~(1<<EORSMI))
398 #define Is_usb_resume() ((UDINT & (1<<EORSMI)) ? TRUE : FALSE)
401 #define Usb_enable_wake_up_interrupt() (UDIEN |= (1<<WAKEUPE))
403 #define Usb_disable_wake_up_interrupt() (UDIEN &= ~(1<<WAKEUPE))
404 #define Is_swake_up_interrupt_enabled() ((UDIEN & (1<<WAKEUPE)) ? TRUE : FALSE)
406 #define Usb_ack_wake_up() (UDINT = ~(1<<WAKEUPI))
408 #define Is_usb_wake_up() ((UDINT & (1<<WAKEUPI)) ? TRUE : FALSE)
411 #define Usb_enable_reset_interrupt() (UDIEN |= (1<<EORSTE))
413 #define Usb_disable_reset_interrupt() (UDIEN &= ~(1<<EORSTE))
414 #define Is_reset_interrupt_enabled() ((UDIEN & (1<<EORSTE)) ? TRUE : FALSE)
416 #define Usb_ack_reset() (UDINT = ~(1<<EORSTI))
418 #define Is_usb_reset() ((UDINT & (1<<EORSTI)) ? TRUE : FALSE)
421 #define Usb_enable_sof_interrupt() (UDIEN |= (1<<SOFE))
423 #define Usb_disable_sof_interrupt() (UDIEN &= ~(1<<SOFE))
424 #define Is_sof_interrupt_enabled() ((UDIEN & (1<<SOFE)) ? TRUE : FALSE)
426 #define Usb_ack_sof() (UDINT = ~(1<<SOFI))
428 #define Is_usb_sof() ((UDINT & (1<<SOFI)) ? TRUE : FALSE)
431 #define Usb_enable_suspend_interrupt() (UDIEN |= (1<<SUSPE))
433 #define Usb_disable_suspend_interrupt() (UDIEN &= ~(1<<SUSPE))
434 #define Is_suspend_interrupt_enabled() ((UDIEN & (1<<SUSPE)) ? TRUE : FALSE)
436 #define Usb_ack_suspend() (UDINT = ~(1<<SUSPI))
438 #define Is_usb_suspend() ((UDINT & (1<<SUSPI)) ? TRUE : FALSE)
441 #define Usb_enable_address() (UDADDR |= (1<<ADDEN))
443 #define Usb_disable_address() (UDADDR &= ~(1<<ADDEN))
445 #define Usb_configure_address(addr) (UDADDR = (UDADDR & (1<<ADDEN)) | ((U8)addr & MSK_UADD))
448 #define Usb_frame_number() ((U16)((((U16)UDFNUMH) << 8) | ((U16)UDFNUML)))
450 #define Is_usb_frame_number_crc_error() ((UDMFN & (1<<FNCERR)) ? TRUE : FALSE)
460 #define Usb_select_endpoint(ep) (UENUM = (U8)ep )
463 #define Usb_get_selected_endpoint() (UENUM )
466 #define Usb_reset_endpoint(ep) (UERST = 1 << (U8)ep, UERST = 0)
469 #define Usb_enable_endpoint() (UECONX |= (1<<EPEN))
471 #define Usb_enable_stall_handshake() (UECONX |= (1<<STALLRQ))
473 #define Usb_reset_data_toggle() (UECONX |= (1<<RSTDT))
475 #define Usb_disable_endpoint() (UECONX &= ~(1<<EPEN))
477 #define Usb_disable_stall_handshake() (UECONX |= (1<<STALLRQC))
479 #define Usb_select_epnum_for_cpu() (UECONX &= ~(1<<EPNUMS))
481 #define Is_usb_endpoint_enabled() ((UECONX & (1<<EPEN)) ? TRUE : FALSE)
483 #define Is_usb_endpoint_stall_requested() ((UECONX & (1<<STALLRQ)) ? TRUE : FALSE)
486 #define Usb_configure_endpoint_type(type) (UECFG0X = (UECFG0X & ~(MSK_EPTYPE)) | ((U8)type << 6))
488 #define Usb_configure_endpoint_direction(dir) (UECFG0X = (UECFG0X & ~(1<<EPDIR)) | ((U8)dir))
491 #define Usb_configure_endpoint_size(size) (UECFG1X = (UECFG1X & ~MSK_EPSIZE) | ((U8)size << 4))
493 #define Usb_configure_endpoint_bank(bank) (UECFG1X = (UECFG1X & ~MSK_EPBK) | ((U8)bank << 2))
495 #define Usb_allocate_memory() (UECFG1X |= (1<<ALLOC))
497 #define Usb_unallocate_memory() (UECFG1X &= ~(1<<ALLOC))
500 #define Usb_ack_overflow_interrupt() (UESTA0X &= ~(1<<OVERFI))
502 #define Usb_ack_underflow_interrupt() (UESTA0X &= ~(1<<UNDERFI))
504 #define Usb_ack_zlp() (UESTA0X &= ~(1<<ZLPSEEN))
506 #define Usb_data_toggle() ((UESTA0X&MSK_DTSEQ) >> 2)
508 #define Usb_nb_busy_bank() (UESTA0X & MSK_NBUSYBK)
510 #define Is_usb_one_bank_busy() ((UESTA0X & MSK_NBUSYBK) == 0 ? FALSE : TRUE)
512 #define Is_endpoint_configured() ((UESTA0X & (1<<CFGOK)) ? TRUE : FALSE)
514 #define Is_usb_overflow() ((UESTA0X & (1<<OVERFI)) ? TRUE : FALSE)
516 #define Is_usb_underflow() ((UESTA0X & (1<<UNDERFI)) ? TRUE : FALSE)
518 #define Is_usb_zlp() ((UESTA0X & (1<<ZLPSEEN)) ? TRUE : FALSE)
521 #define Usb_control_direction() ((UESTA1X & (1<<CTRLDIR)) >> 2)
523 #define Usb_current_bank() ( UESTA1X & MSK_CURRBK)
526 #define Usb_ack_fifocon() (UEINTX &= ~(1<<FIFOCON))
528 #define Usb_ack_nak_in() (UEINTX &= ~(1<<NAKINI))
530 #define Usb_ack_nak_out() (UEINTX &= ~(1<<NAKOUTI))
532 #define Usb_ack_receive_setup() (UEINTX &= ~(1<<RXSTPI))
534 #define Is_usb_receive_nak_in() (UEINTX &(1<<NAKINI))
536 #define Is_usb_receive_nak_out() (UEINTX &(1<<NAKOUTI))
538 #define Usb_ack_receive_out() (UEINTX &= ~(1<<RXOUTI), Usb_ack_fifocon())
540 #define Usb_ack_stalled() (MSK_STALLEDI= 0)
542 #define Usb_ack_in_ready() (UEINTX &= ~(1<<TXINI), Usb_ack_fifocon())
544 #define Usb_kill_last_in_bank() (UENTTX |= (1<<RXOUTI))
546 #define Is_usb_read_enabled() (UEINTX&(1<<RWAL))
548 #define Is_usb_write_enabled() (UEINTX&(1<<RWAL))
550 #define Is_usb_read_control_enabled() (UEINTX&(1<<TXINI))
552 #define Is_usb_receive_setup() (UEINTX&(1<<RXSTPI))
554 #define Is_usb_receive_out() (UEINTX&(1<<RXOUTI))
556 #define Is_usb_in_ready() (UEINTX&(1<<TXINI))
558 #define Usb_send_in() (UEINTX &= ~(1<<FIFOCON))
560 #define Usb_send_control_in() (UEINTX &= ~(1<<TXINI))
562 #define Usb_free_out_bank() (UEINTX &= ~(1<<FIFOCON))
564 #define Usb_ack_control_out() (UEINTX &= ~(1<<RXOUTI))
567 #define Usb_enable_flow_error_interrupt() (UEIENX |= (1<<FLERRE))
569 #define Usb_enable_nak_in_interrupt() (UEIENX |= (1<<NAKINE))
571 #define Usb_enable_nak_out_interrupt() (UEIENX |= (1<<NAKOUTE))
573 #define Usb_enable_receive_setup_interrupt() (UEIENX |= (1<<RXSTPE))
575 #define Usb_enable_receive_out_interrupt() (UEIENX |= (1<<RXOUTE))
577 #define Usb_enable_stalled_interrupt() (UEIENX |= (1<<STALLEDE))
579 #define Usb_enable_in_ready_interrupt() (UEIENX |= (1<<TXINE))
581 #define Usb_disable_flow_error_interrupt() (UEIENX &= ~(1<<FLERRE))
583 #define Usb_disable_nak_in_interrupt() (UEIENX &= ~(1<<NAKINE))
585 #define Usb_disable_nak_out_interrupt() (UEIENX &= ~(1<<NAKOUTE))
587 #define Usb_disable_receive_setup_interrupt() (UEIENX &= ~(1<<RXSTPE))
589 #define Usb_disable_receive_out_interrupt() (UEIENX &= ~(1<<RXOUTE))
591 #define Usb_disable_stalled_interrupt() (UEIENX &= ~(1<<STALLEDE))
593 #define Usb_disable_in_ready_interrupt() (UEIENX &= ~(1<<TXIN))
596 #define Usb_read_byte() (UEDATX)
598 #define Usb_write_byte(byte) (UEDATX = (U8)byte)
601 #define Usb_byte_counter() ((((U16)UEBCHX) << 8) | (UEBCLX))
603 #define Usb_byte_counter_8() ((U8)UEBCLX)
606 #define Usb_interrupt_flags() (UEINT)
608 #define Is_usb_endpoint_event() (Usb_interrupt_flags() != 0x00)
617 #define Host_allocate_memory() (UPCFG1X |= (1<<ALLOC))
619 #define Host_unallocate_memory() (UPCFG1X &= ~(1<<ALLOC))
622 #define Host_enable() (USBCON |= (1<<HOST))
625 #define SOFEN 0 //For AVRGCC, SOFEN bit missing in default sfr file
628 #define Host_enable_sof() (UHCON |= (1<<SOFEN))
630 #define Host_disable_sof() (UHCON &= ~(1<<SOFEN))
632 #define Host_send_reset() (UHCON |= (1<<RESET))
634 #define Host_is_reset() ((UHCON & (1<<RESET)) ? TRUE : FALSE)
636 #define Host_send_resume() (UHCON |= (1<<RESUME))
638 #define Host_is_resume() ((UHCON & (1<<RESUME)) ? TRUE : FALSE)
641 #define Host_enable_sof_interrupt() (UHIEN |= (1<<HSOFE))
643 #define Host_disable_sof_interrupt() (UHIEN &= ~(1<<HSOFE))
644 #define Is_host_sof_interrupt_enabled() ((UHIEN & (1<<HSOFE)) ? TRUE : FALSE)
646 #define Host_is_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
647 #define Is_host_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
648 #define Host_ack_sof() (UHINT &= ~(1<<HSOFI))
651 #define Host_enable_hwup_interrupt() (UHIEN |= (1<<HWUPE))
653 #define Host_disable_hwup_interrupt() (UHIEN &= ~(1<<HWUPE))
654 #define Is_host_hwup_interrupt_enabled() ((UHIEN & (1<<HWUPE)) ? TRUE : FALSE)
656 #define Host_is_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
658 #define Is_host_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
659 #define Host_ack_hwup() (UHINT &= ~(1<<HWUPI))
662 #define Host_enable_down_stream_resume_interrupt() (UHIEN |= (1<<RSMEDE))
664 #define Host_disable_down_stream_resume_interrupt() (UHIEN &= ~(1<<RSMEDE))
665 #define Is_host_down_stream_resume_interrupt_enabled() ((UHIEN & (1<<RSMEDE)) ? TRUE : FALSE)
667 #define Is_host_down_stream_resume() ((UHINT & (1<<RSMEDI)) ? TRUE : FALSE)
668 #define Host_ack_down_stream_resume() (UHINT &= ~(1<<RSMEDI))
671 #define Host_enable_remote_wakeup_interrupt() (UHIEN |= (1<<RXRSME))
673 #define Host_disable_remote_wakeup_interrupt() (UHIEN &= ~(1<<RXRSME))
674 #define Is_host_remote_wakeup_interrupt_enabled() ((UHIEN & (1<<RXRSME)) ? TRUE : FALSE)
676 #define Host_is_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
678 #define Is_host_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
679 #define Host_ack_remote_wakeup() (UHINT &= ~(1<<RXRSMI))
682 #define Host_enable_device_connection_interrupt() (UHIEN |= (1<<DCONNE))
684 #define Host_disable_device_connection_interrupt() (UHIEN &= ~(1<<DCONNE))
685 #define Is_host_device_connection_interrupt_enabled() ((UHIEN & (1<<DCONNE)) ? TRUE : FALSE)
687 #define Is_device_connection() (UHINT & (1<<DCONNI))
689 #define Host_ack_device_connection() (UHINT = ~(1<<DCONNI))
692 #define Host_enable_device_disconnection_interrupt() (UHIEN |= (1<<DDISCE))
694 #define Host_disable_device_disconnection_interrupt() (UHIEN &= ~(1<<DDISCE))
695 #define Is_host_device_disconnection_interrupt_enabled() ((UHIEN & (1<<DDISCE)) ? TRUE : FALSE)
697 #define Is_device_disconnection() (UHINT & (1<<DDISCI) ? TRUE : FALSE)
699 #define Host_ack_device_disconnection() (UHINT = ~(1<<DDISCI))
702 #define Host_enable_reset_interrupt() (UHIEN |= (1<<RSTE))
704 #define Host_disable_reset_interrupt() (UHIEN &= ~(1<<RSTE))
705 #define Is_host_reset_interrupt_enabled() ((UHIEN & (1<<RSTE)) ? TRUE : FALSE)
707 #define Host_ack_reset() (UHINT = ~(1<<RSTI))
709 #define Is_host_reset() Host_is_reset()
713 #define Host_vbus_request() (OTGCON |= (1<<VBUSREQ))
715 #define Host_clear_vbus_request() (OTGCON |= (1<<VBUSRQC))
717 #define Host_configure_address(addr) (UHADDR = addr & MSK_HADDR)
720 #define Is_host_full_speed() ((USBSTA & (1<<SPEED)) ? TRUE : FALSE)
729 #define Host_select_pipe(p) (UPNUM = (U8)p)
732 #define Host_get_selected_pipe() (UPNUM )
735 #define Host_enable_pipe() (UPCONX |= (1<<PEN))
737 #define Host_disable_pipe() (UPCONX &= ~(1<<PEN))
740 #define Host_set_token_setup() (UPCFG0X = UPCFG0X & ~MSK_TOKEN_SETUP)
742 #define Host_set_token_in() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_IN)
744 #define Host_set_token_out() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_OUT)
747 #define Host_get_endpoint_number() (UPCFG0X & (MSK_PEPNUM))
750 #define Host_get_pipe_interrupt() (UPINT)
753 #define Host_set_interrupt_frequency(frq) (UPCFG2X = (U8)frq)
756 #define Is_pipe_configured() (UPSTAX & (1<<CFGOK))
758 #define Is_host_one_bank_busy() ((UPSTAX & (1<<MSK_NBUSYBK)) != 0)
760 #define Host_number_of_busy_bank() (UPSTAX & (1<<MSK_NBUSYBK))
763 #define Host_reset_pipe(p) (UPRST = 1<<p , UPRST = 0)
766 #define Host_write_byte(dat) (UPDATX = dat)
768 #define Host_read_byte() (UPDATX)
771 #define Host_freeze_pipe() (UPCONX |= (1<<PFREEZE))
773 #define Host_unfreeze_pipe() (UPCONX &= ~(1<<PFREEZE))
775 #define Is_host_pipe_freeze() (UPCONX & (1<<PFREEZE))
778 #define Host_reset_pipe_data_toggle() (UPCONX |= (1<<RSTDT) )
781 #define Is_host_setup_sent() ((UPINTX & (1<<TXSTPI)) ? TRUE : FALSE)
783 #define Is_host_control_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
785 #define Is_host_control_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
787 #define Is_host_stall() ((UPINTX & (1<<RXSTALLI)) ? TRUE : FALSE)
789 #define Is_host_pipe_error() ((UPINTX & (1<<PERRI)) ? TRUE : FALSE)
791 #define Host_send_setup() (UPINTX &= ~(1<<FIFOCON))
793 #define Host_send_control_in() (UPINTX &= ~(1<<FIFOCON))
795 #define Host_send_control_out() (UPINTX &= ~(1<<FIFOCON))
797 #define Host_ack_control_out() (UPINTX &= ~(1<<TXOUTI))
799 #define Host_ack_control_in() (UPINTX &= ~(1<<RXINI))
801 #define Host_ack_setup() (UPINTX &= ~(1<<TXSTPI))
803 #define Host_ack_stall() (UPINTX &= ~(1<<RXSTALLI))
806 #define Host_send_out() (UPINTX &= ~(1<<FIFOCON))
808 #define Is_host_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
810 #define Host_ack_out_sent() (UPINTX &= ~(1<<TXOUTI))
812 #define Is_host_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
814 #define Host_ack_in_received() (UPINTX &= ~(1<<RXINI))
816 #define Host_send_in() (UPINTX &= ~(1<<FIFOCON))
818 #define Is_host_nak_received() ((UPINTX & (1<<NAKEDI)) ? TRUE : FALSE)
820 #define Host_ack_nak_received() (UPINTX &= ~(1<<NAKEDI))
825 #define Is_host_read_enabled() (UPINTX&(1<<RWAL))
827 #define Is_host_write_enabled() (UPINTX&(1<<RWAL))
830 #define Host_standard_in_mode() (UPCONX &= ~(1<<INMODE))
832 #define Host_continuous_in_mode() (UPCONX |= (1<<INMODE))
835 #define Host_in_request_number(in_num) (UPINRQX = (U8)in_num)
837 #define Host_get_in_request_number() (UPINRQX)
840 #define Host_data_length_U8() (UPBCLX)
842 #define Host_data_length_U16() ((((U16)UPBCHX)<<8) | UPBCLX)
844 #define Host_byte_counter() Host_data_length_U16()
846 #define Host_byte_counter_8() Host_data_length_U8()
849 #define Host_get_pipe_length() ((U16)0x08 << ((UPCFG1X & MSK_PSIZE)>>4))
852 #define Host_get_pipe_type() (UPCFG0X>>6)
855 #define Host_error_status() (UPERRX & MSK_ERROR)
857 #define Host_ack_all_errors() (UPERRX = 0x00)
860 #define Host_enable_transmit_interrupt() (UPIENX |= (1<<TXOUTE))
862 #define Host_disable_transmit_interrupt() (UPIENX &= ~(1<<TXOUTE))
865 #define Host_enable_receive_interrupt() (UPIENX |= (1<<RXINE))
867 #define Host_disable_receive_interrupt() (UPIENX &= ~(1<<RXINE))
870 #define Host_enable_stall_interrupt() (UPIENX |= (1<<RXSTALLE))
872 #define Host_disable_stall_interrupt() (UPIENX &= ~(1<<RXSTALLE))
875 #define Host_enable_error_interrupt() (UPIENX |= (1<<PERRE))
877 #define Host_disable_error_interrupt() (UPIENX &= ~(1<<PERRE))
880 #define Host_enable_nak_interrupt() (UPIENX |= (1<<NAKEDE))
882 #define Host_disable_nak_interrupt() (UPIENX &= ~(1<<NAKEDE))
884 #define Get_pipe_token(x) ((x & (0x80)) ? TOKEN_IN : TOKEN_OUT)
896 ( (((x)>>8)&0x00FF) \
897 | (((x)<<8)&0xFF00) \
908 #if !defined(BIG_ENDIAN) && !defined(LITTLE_ENDIAN)
909 #error YOU MUST Define the Endian Type of target: LITTLE_ENDIAN or BIG_ENDIAN
912 #define Usb_write_word_enum_struc(x) (x)
914 #define Usb_write_word_enum_struc(x) (wSWAP(x))
927 U8 host_config_pipe (U8, U8);
928 U8 host_determine_pipe_size (U16);
929 void host_disable_all_pipe (
void);
930 U8 usb_get_nb_pipe_interrupt (
void);
932 U8 usb_endpoint_wait_for_read_control_enabled();
933 U8 usb_endpoint_wait_for_write_enabled();
934 U8 usb_endpoint_wait_for_receive_out();
935 U8 usb_endpoint_wait_for_IN_ready();
937 #define usb_endpoint_wait_for_read_enabled usb_endpoint_wait_for_write_enabled
U8 usb_config_ep(U8 config0, U8 config1)
usb_configure_endpoint.
U8 usb_read_packet(U8 ep_num, U8 *rbuf, U8 data_length)
usb_read_packet.
U8 usb_init_device(void)
usb_init_device.
void usb_halt_endpoint(U8 ep_num)
usb_halt_endpoint.
U8 usb_send_packet(U8 ep_num, U8 *tbuf, U8 data_length)
usb_send_packet.
U8 usb_select_enpoint_interrupt(void)
usb_select_endpoint_interrupt.
This file includes the correct compiler definitions for the different architectures.