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gptimer.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538
33  * @{
34  *
35  * \defgroup cc2538-gptimer cc2538 General-Purpose Timers
36  *
37  * Driver for the cc2538 General Purpose Timers
38  * @{
39  *
40  * \file
41  * Header file for the cc2538 General Purpose Timers
42  */
43 #ifndef GPTIMER_H_
44 #define GPTIMER_H_
45 /*---------------------------------------------------------------------------*/
46 /** \name Base addresses for the GPT register instances
47  * @{
48  */
49 #define GPT_0_BASE 0x40030000 /**< GPTIMER0 */
50 #define GPT_1_BASE 0x40031000 /**< GPTIMER1 */
51 #define GPT_2_BASE 0x40032000 /**< GPTIMER2 */
52 #define GPT_3_BASE 0x40033000 /**< GPTIMER3 */
53 /** @} */
54 /*---------------------------------------------------------------------------*/
55 /** \name GPTIMER Register offset declarations
56  * @{
57  */
58 #define GPTIMER_CFG 0x00000000 /**< GPTM configuration */
59 #define GPTIMER_TAMR 0x00000004 /**< GPTM Timer A mode */
60 #define GPTIMER_TBMR 0x00000008 /**< GPTM Timer B mode */
61 #define GPTIMER_CTL 0x0000000C /**< GPTM control */
62 #define GPTIMER_SYNC 0x00000010 /**< GPTM synchronize (0 only) */
63 #define GPTIMER_IMR 0x00000018 /**< GPTM interrupt mask */
64 #define GPTIMER_RIS 0x0000001C /**< GPTM raw interrupt status */
65 #define GPTIMER_MIS 0x00000020 /**< GPTM masked interrupt status */
66 #define GPTIMER_ICR 0x00000024 /**< GPTM interrupt clear */
67 #define GPTIMER_TAILR 0x00000028 /**< GPTM Timer A interval load */
68 #define GPTIMER_TBILR 0x0000002C /**< GPTM Timer B interval load */
69 #define GPTIMER_TAMATCHR 0x00000030 /**< GPTM Timer A match */
70 #define GPTIMER_TBMATCHR 0x00000034 /**< GPTM Timer B match */
71 #define GPTIMER_TAPR 0x00000038 /**< GPTM Timer A prescale */
72 #define GPTIMER_TBPR 0x0000003C /**< GPTM Timer B prescale */
73 #define GPTIMER_TAPMR 0x00000040 /**< GPTM Timer A prescale match */
74 #define GPTIMER_TBPMR 0x00000044 /**< GPTM Timer B prescale match */
75 #define GPTIMER_TAR 0x00000048 /**< GPTM Timer A */
76 #define GPTIMER_TBR 0x0000004C /**< GPTM Timer B */
77 #define GPTIMER_TAV 0x00000050 /**< GPTM Timer A value */
78 #define GPTIMER_TBV 0x00000054 /**< GPTM Timer B value */
79 #define GPTIMER_RTCPD 0x00000058 /**< GPTM RTC predivide */
80 #define GPTIMER_TAPS 0x0000005C /**< GPTM Timer A prescale snapshot */
81 #define GPTIMER_TBPS 0x00000060 /**< GPTM Timer B prescale snapshot */
82 #define GPTIMER_TAPV 0x00000064 /**< GPTM Timer A prescale value */
83 #define GPTIMER_TBPV 0x00000068 /**< GPTM Timer B prescale value */
84 #define GPTIMER_PP 0x00000FC0 /**< GPTM peripheral properties */
85 /** @} */
86 /*---------------------------------------------------------------------------*/
87 /** \name GPTIMER_CFG register bit masks
88  * @{
89  */
90 #define GPTIMER_CFG_GPTMCFG 0x00000007 /**< configuration */
91 /** @} */
92 /*---------------------------------------------------------------------------*/
93 /** \name GPTIMER_TnMR bit values
94  * @{
95  */
96 #define GPTIMER_TAMR_TAMR_ONE_SHOT 0x00000001
97 #define GPTIMER_TAMR_TAMR_PERIODIC 0x00000002
98 #define GPTIMER_TAMR_TAMR_CAPTURE 0x00000003
99 #define GPTIMER_TBMR_TBMR_ONE_SHOT 0x00000001
100 #define GPTIMER_TBMR_TBMR_PERIODIC 0x00000002
101 #define GPTIMER_TBMR_TBMR_CAPTURE 0x00000003
102 /** @} */
103 /*---------------------------------------------------------------------------*/
104 /** \name GPTIMER_TAMR register bit masks
105  * @{
106  */
107 #define GPTIMER_TAMR_TAPLO 0x00000800 /**< Legacy PWM operation */
108 #define GPTIMER_TAMR_TAMRSU 0x00000400 /**< Timer A match register update mode */
109 #define GPTIMER_TAMR_TAPWMIE 0x00000200 /**< Timer A PWM interrupt enable */
110 #define GPTIMER_TAMR_TAILD 0x00000100 /**< Timer A PWM interval load write */
111 #define GPTIMER_TAMR_TASNAPS 0x00000080 /**< Timer A snap-shot mode */
112 #define GPTIMER_TAMR_TAWOT 0x00000040 /**< Timer A wait-on-trigger */
113 #define GPTIMER_TAMR_TAMIE 0x00000020 /**< Timer A match interrupt enable */
114 #define GPTIMER_TAMR_TACDIR 0x00000010 /**< Timer A count direction */
115 #define GPTIMER_TAMR_TAAMS 0x00000008 /**< Timer A alternate mode */
116 #define GPTIMER_TAMR_TACMR 0x00000004 /**< Timer A capture mode */
117 #define GPTIMER_TAMR_TAMR 0x00000003 /**< Timer A mode */
118 /** @} */
119 /*---------------------------------------------------------------------------*/
120 /** \name GPTIMER_TBMR register bit masks
121  * @{
122  */
123 #define GPTIMER_TBMR_TBPLO 0x00000800 /**< Legacy PWM operation */
124 #define GPTIMER_TBMR_TBMRSU 0x00000400 /**< Timer B match register update mode */
125 #define GPTIMER_TBMR_TBPWMIE 0x00000200 /**< Timer B PWM interrupt enable */
126 #define GPTIMER_TBMR_TBILD 0x00000100 /**< Timer B PWM interval load write */
127 #define GPTIMER_TBMR_TBSNAPS 0x00000080 /**< Timer B snap-shot mode */
128 #define GPTIMER_TBMR_TBWOT 0x00000040 /**< Timer B wait-on-trigger */
129 #define GPTIMER_TBMR_TBMIE 0x00000020 /**< Timer B match interrupt enable */
130 #define GPTIMER_TBMR_TBCDIR 0x00000010 /**< Timer B count direction */
131 #define GPTIMER_TBMR_TBAMS 0x00000008 /**< Timer B alternate mode */
132 #define GPTIMER_TBMR_TBCMR 0x00000004 /**< Timer B capture mode */
133 #define GPTIMER_TBMR_TBMR 0x00000003 /**< Timer B mode */
134 /** @} */
135 /*---------------------------------------------------------------------------*/
136 /** \name GPTIMER_CTL register bit masks
137  * @{
138  */
139 #define GPTIMER_CTL_TBPWML 0x00004000 /**< Timer B PWM output level */
140 #define GPTIMER_CTL_TBOTE 0x00002000 /**< Timer B output trigger enable */
141 #define GPTIMER_CTL_TBEVENT 0x00000C00 /**< Timer B event mode */
142 #define GPTIMER_CTL_TBSTALL 0x00000200 /**< Timer B stall enable */
143 #define GPTIMER_CTL_TBEN 0x00000100 /**< Timer B enable */
144 #define GPTIMER_CTL_TAPWML 0x00000040 /**< Timer A PWM output level */
145 #define GPTIMER_CTL_TAOTE 0x00000020 /**< Timer A output trigger enable */
146 #define GPTIMER_CTL_RTCEN 0x00000010 /**< RTC enable */
147 #define GPTIMER_CTL_TAEVENT 0x0000000C /**< Timer A event mode */
148 #define GPTIMER_CTL_TASTALL 0x00000002 /**< Timer A stall enable */
149 #define GPTIMER_CTL_TAEN 0x00000001 /**< Timer A enable */
150 /** @} */
151 /*---------------------------------------------------------------------------*/
152 /** \name GPTIMER_SYNC register bit masks
153  * @{
154  */
155 #define GPTIMER_SYNC_SYNC3 0x000000C0 /**< Synchronize GPTM3 */
156 #define GPTIMER_SYNC_SYNC2 0x00000030 /**< Synchronize GPTM2 */
157 #define GPTIMER_SYNC_SYNC1 0x0000000C /**< Synchronize GPTM1 */
158 #define GPTIMER_SYNC_SYNC0 0x00000003 /**< Synchronize GPTM0 */
159 /** @} */
160 /*---------------------------------------------------------------------------*/
161 /** \name GPTIMER_IMR register bit masks
162  * @{
163  */
164 #define GPTIMER_IMR_TBMIM 0x00000800 /**< Timer B match int mask */
165 #define GPTIMER_IMR_CBEIM 0x00000400 /**< Timer B capture event int mask */
166 #define GPTIMER_IMR_CBMIM 0x00000200 /**< Timer B capture match int mask */
167 #define GPTIMER_IMR_TBTOIM 0x00000100 /**< Timer B time-out int mask */
168 #define GPTIMER_IMR_TAMIM 0x00000010 /**< Timer A match int mask */
169 #define GPTIMER_IMR_RTCIM 0x00000008 /**< RTC int mask */
170 #define GPTIMER_IMR_CAEIM 0x00000004 /**< Timer A capture event int mask */
171 #define GPTIMER_IMR_CAMIM 0x00000002 /**< Timer A capture match int mask */
172 #define GPTIMER_IMR_TATOIM 0x00000001 /**< Timer A time-out int mask */
173 /** @} */
174 /*---------------------------------------------------------------------------*/
175 /** \name GPTIMER_RIS register bit masks
176  * @{
177  */
178 #define GPTIMER_RIS_TBMRIS 0x00000800 /**< Timer B match raw status */
179 #define GPTIMER_RIS_CBERIS 0x00000400 /**< Timer B capture event raw status */
180 #define GPTIMER_RIS_CBMRIS 0x00000200 /**< Timer B capture match raw status */
181 #define GPTIMER_RIS_TBTORIS 0x00000100 /**< Timer B time-out raw status */
182 #define GPTIMER_RIS_TAMRIS 0x00000010 /**< Timer A match raw status */
183 #define GPTIMER_RIS_RTCRIS 0x00000008 /**< RTC raw status */
184 #define GPTIMER_RIS_CAERIS 0x00000004 /**< Timer A capture event raw status */
185 #define GPTIMER_RIS_CAMRIS 0x00000002 /**< Timer A capture match raw status */
186 #define GPTIMER_RIS_TATORIS 0x00000001 /**< Timer A time-out raw status */
187 /** @} */
188 /*---------------------------------------------------------------------------*/
189 /** \name GPTIMER_MIS register bit masks
190  * @{
191  */
192 #define GPTIMER_MIS_TBMMIS 0x00000800 /**< Timer B match masked status */
193 #define GPTIMER_MIS_CBEMIS 0x00000400 /**< Timer B capture event masked status */
194 #define GPTIMER_MIS_CBMMIS 0x00000200 /**< Timer B capture match masked status */
195 #define GPTIMER_MIS_TBTOMIS 0x00000100 /**< Timer B time-out masked status */
196 #define GPTIMER_MIS_TAMRIS 0x00000010 /**< Timer A match masked status */
197 #define GPTIMER_MIS_RTCMIS 0x00000008 /**< RTC masked status */
198 #define GPTIMER_MIS_CAEMIS 0x00000004 /**< Timer A capture event masked status */
199 #define GPTIMER_MIS_CAMMIS 0x00000002 /**< Timer A capture match masked status */
200 #define GPTIMER_MIS_TATOMIS 0x00000001 /**< Timer A time-out masked status */
201 /** @} */
202 /*---------------------------------------------------------------------------*/
203 /** \name GPTIMER_ICR register bit masks
204  * @{
205  */
206 #define GPTIMER_ICR_WUECINT 0x00010000 /**< write update error int clear */
207 #define GPTIMER_ICR_TBMCINT 0x00000800 /**< Timer B match int clear */
208 #define GPTIMER_ICR_CBECINT 0x00000400 /**< Timer B capture event int clear */
209 #define GPTIMER_ICR_CBMCINT 0x00000200 /**< Timer B capture match int clear */
210 #define GPTIMER_ICR_TBTOCINT 0x00000100 /**< Timer B time-out int clear */
211 #define GPTIMER_ICR_TAMCINT 0x00000010 /**< Timer A match int clear */
212 #define GPTIMER_ICR_RTCCINT 0x00000008 /**< RTC interrupt clear */
213 #define GPTIMER_ICR_CAECINT 0x00000004 /**< Timer A capture event int clear */
214 #define GPTIMER_ICR_CAMCINT 0x00000002 /**< Timer A capture match int clear */
215 #define GPTIMER_ICR_TATOCINT 0x00000001 /**< Timer A time-out int clear */
216 /** @} */
217 /*---------------------------------------------------------------------------*/
218 /** \name GPTIMER_TAILR register bit masks
219  * @{
220  */
221 #define GPTIMER_TAILR_TAILR 0xFFFFFFFF /**< A interval load register */
222 /** @} */
223 /*---------------------------------------------------------------------------*/
224 /** \name GPTIMER_TBILR register bit masks
225  * @{
226  */
227 #define GPTIMER_TBILR_TBILR 0x0000FFFF /**< B interval load register */
228 /** @} */
229 /*---------------------------------------------------------------------------*/
230 /** \name GPTIMER_TAMATCHR register bit masks
231  * @{
232  */
233 #define GPTIMER_TAMATCHR_TAMR 0xFFFFFFFF /**< Timer A match register */
234 /** @} */
235 /*---------------------------------------------------------------------------*/
236 /** \name GPTIMER_TBMATCHR register bit masks
237  * @{
238  */
239 #define GPTIMER_TBMATCHR_TBMR 0x0000FFFF /**< Timer B match register */
240 /** @} */
241 /*---------------------------------------------------------------------------*/
242 /** \name GPTIMER_TAPR register bit masks
243  * @{
244  */
245 #define GPTIMER_TAPR_TAPSR 0x000000FF /**< Timer A prescale */
246 /** @} */
247 /*---------------------------------------------------------------------------*/
248 /** \name GPTIMER_TBPR register bit masks
249  * @{
250  */
251 #define GPTIMER_TBPR_TBPSR 0x000000FF /**< Timer B prescale */
252 /** @} */
253 /*---------------------------------------------------------------------------*/
254 /** \name GPTIMER_TAPMR register bit masks
255  * @{
256  */
257 #define GPTIMER_TAPMR_TAPSR 0x000000FF /**< Timer A prescale match */
258 /** @} */
259 /*---------------------------------------------------------------------------*/
260 /** \name GPTIMER_TBPMR register bit masks
261  * @{
262  */
263 #define GPTIMER_TBPMR_TBPSR 0x000000FF /**< Timer B prescale match */
264 /** @} */
265 /*---------------------------------------------------------------------------*/
266 /** \name GPTIMER_TAR register bit masks
267  * @{
268  */
269 #define GPTIMER_TAR_TAR 0xFFFFFFFF /**< Timer A register */
270 /** @} */
271 /*---------------------------------------------------------------------------*/
272 /** \name GPTIMER_TBR register bit masks
273  * @{
274  */
275 #define GPTIMER_TBR_TBR 0x0000FFFF /**< Timer B register */
276 /** @} */
277 /*---------------------------------------------------------------------------*/
278 /** \name GPTIMER_TAV register bit masks
279  * @{
280  */
281 #define GPTIMER_TAV_TAV 0xFFFFFFFF /**< Timer A register */
282 /** @} */
283 /*---------------------------------------------------------------------------*/
284 /** \name GPTIMER_TBV register bit masks
285  * @{
286  */
287 #define GPTIMER_TBV_PRE 0x00FF0000 /**< Timer B prescale register */
288 #define GPTIMER_TBV_TBV 0x0000FFFF /**< Timer B register */
289 /** @} */
290 /*---------------------------------------------------------------------------*/
291 /** \name GPTIMER_RTCPD register bit masks
292  * @{
293  */
294 #define GPTIMER_RTCPD_RTCPD 0x0000FFFF /**< RTC predivider */
295 /** @} */
296 /*---------------------------------------------------------------------------*/
297 /** \name GPTIMER_TAPS register bit masks
298  * @{
299  */
300 #define GPTIMER_TAPS_PSS 0x0000FFFF /**< Timer A prescaler */
301 /** @} */
302 /*---------------------------------------------------------------------------*/
303 /** \name GPTIMER_TBPS register bit masks
304  * @{
305  */
306 #define GPTIMER_TBPS_PSS 0x0000FFFF /**< Timer B prescaler */
307 /** @} */
308 /*---------------------------------------------------------------------------*/
309 /** \name GPTIMER_TAPV register bit masks
310  * @{
311  */
312 #define GPTIMER_TAPV_PSV 0x0000FFFF /**< Timer A prescaler value */
313 /** @} */
314 /*---------------------------------------------------------------------------*/
315 /** \name GPTIMER_TBPV register bit masks
316  * @{
317  */
318 #define GPTIMER_TBPV_PSV 0x0000FFFF /**< Timer B prescaler value */
319 /** @} */
320 /*---------------------------------------------------------------------------*/
321 /** \name GPTIMER_PP register bit masks
322  * @{
323  */
324 #define GPTIMER_PP_ALTCLK 0x00000040 /**< Alternate clock source */
325 #define GPTIMER_PP_SYNCNT 0x00000020 /**< Synchronized start */
326 #define GPTIMER_PP_CHAIN 0x00000010 /**< Chain with other timers */
327 #define GPTIMER_PP_SIZE 0x0000000F /**< Timer size */
328 /** @} */
329 
330 #endif /* GPTIMER_H_ */
331 
332 /**
333  * @}
334  * @}
335  */
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