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usb-regs.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /** \addtogroup cc2538
32  * @{
33  *
34  * \defgroup cc2538-usb cc2538 USB controller
35  *
36  * Driver for the cc2538 USB controller.
37  *
38  * We use the USB core in cpu/cc253x/usb which is known to work on Linux as
39  * well as on OS X.
40  * @{
41  *
42  * \file
43  * Header file with declarations for the cc2538 USB registers
44  */
45 #ifndef USB_REGS_H_
46 #define USB_REGS_H_
47 
48 #include "contiki-conf.h"
49 /*---------------------------------------------------------------------------*/
50 /**
51  * \name USB Register Offsets
52  * @{
53  */
54 #define USB_ADDR 0x40089000 /**< Function address */
55 #define USB_POW 0x40089004 /**< Power/Control register */
56 #define USB_IIF 0x40089008 /**< IN EPs and EP0 interrupt flags */
57 #define USB_OIF 0x40089010 /**< OUT endpoint interrupt flags */
58 #define USB_CIF 0x40089018 /**< Common USB interrupt flags */
59 #define USB_IIE 0x4008901C /**< IN EPs and EP0 interrupt mask */
60 #define USB_OIE 0x40089024 /**< Out EPs interrupt-enable mask */
61 #define USB_CIE 0x4008902C /**< Common USB interrupt mask */
62 #define USB_FRML 0x40089030 /**< Current frame number (low byte) */
63 #define USB_FRMH 0x40089034 /**< Current frame number (high) */
64 #define USB_INDEX 0x40089038 /**< Current endpoint index register */
65 #define USB_CTRL 0x4008903C /**< USB control register */
66 #define USB_MAXI 0x40089040 /**< MAX packet size for IN EPs{1-5} */
67 #define USB_CS0_CSIL 0x40089044 /**< EP0 Control and Status or IN EPs
68  control and status (low) */
69 #define USB_CS0 0x40089044 /**< EP0 Control and Status
70  (Alias for USB_CS0_CSIL) */
71 #define USB_CSIL 0x40089044 /**< IN EPs control and status (low)
72  (Alias for USB_CS0_CSIL) */
73 #define USB_CSIH 0x40089048 /**< IN EPs control and status (high) */
74 #define USB_MAXO 0x4008904C /**< MAX packet size for OUT EPs */
75 #define USB_CSOL 0x40089050 /**< OUT EPs control and status (low) */
76 #define USB_CSOH 0x40089054 /**< OUT EPs control and status (high) */
77 #define USB_CNT0_CNTL 0x40089058 /**< Number of RX bytes in EP0 FIFO
78  or number of bytes in EP{1-5}
79  OUT FIFO (low) */
80 #define USB_CNT0 0x40089058 /**< Number of RX bytes in EP0 FIFO
81  (Alias for USB_CNT0_CNTL) */
82 #define USB_CNTL 0x40089058 /**< Number of bytes in EP{1-5}
83  OUT FIFO (low)
84  (Alias for USB_CNT0_CNTL) */
85 #define USB_CNTH 0x4008905C /**< Number of bytes in EP{1-5}
86  OUT FIFO (high) */
87 #define USB_F0 0x40089080 /**< Endpoint-0 FIFO */
88 #define USB_F1 0x40089088 /**< Endpoint-1 FIFO */
89 #define USB_F2 0x40089090 /**< Endpoint-2 FIFO */
90 #define USB_F3 0x40089098 /**< Endpoint-3 FIFO */
91 #define USB_F4 0x400890A0 /**< Endpoint-4 FIFO */
92 #define USB_F5 0x400890A8 /**< Endpoint-5 FIFO */
93 /** @} */
94 /*---------------------------------------------------------------------------*/
95 /**
96  * \name USB_ADDR Register Bit-Masks
97  * @{
98  */
99 #define USB_ADDR_UPDATE 0x00000080 /**< 1 while address updating */
100 #define USB_ADDR_USBADDR 0x0000007F /**< Device address */
101 /** @} */
102 /*---------------------------------------------------------------------------*/
103 /**
104  * \name USB_POW Register Bit-Masks
105  * @{
106  */
107 #define USB_POW_ISO_WAIT_SOF 0x00000080 /**< 1 until SOF received - ISO only */
108 #define USB_POW_RST 0x00000008 /**< 1 During reset signaling */
109 #define USB_POW_RESUME 0x00000004 /**< Remote wakeup resume signalling */
110 #define USB_POW_SUSPEND 0x00000002 /**< Suspend mode entered */
111 #define USB_POW_SUSPEND_EN 0x00000001 /**< Suspend enable */
112 /** @} */
113 /*---------------------------------------------------------------------------*/
114 /**
115  * \name USB_IIF Register Bit-Masks
116  * @{
117  */
118 #define USB_IIF_INEP5IF 0x00000020 /**< IN EP5 Interrupt flag */
119 #define USB_IIF_INEP4IF 0x00000010 /**< IN EP4 Interrupt flag */
120 #define USB_IIF_INEP3IF 0x00000008 /**< IN EP3 Interrupt flag */
121 #define USB_IIF_INEP2IF 0x00000004 /**< IN EP2 Interrupt flag */
122 #define USB_IIF_INEP1IF 0x00000002 /**< IN EP1 Interrupt flag */
123 #define USB_IIF_EP0IF 0x00000001 /**< EP0 Interrupt flag */
124 /** @} */
125 /*---------------------------------------------------------------------------*/
126 /**
127  * \name USB_OIF Register Bit-Masks
128  * @{
129  */
130 #define USB_OIF_OUTEP5IF 0x00000020 /**< OUT EP5 Interrupt flag */
131 #define USB_OIF_OUTEP4IF 0x00000010 /**< OUT EP4 Interrupt flag */
132 #define USB_OIF_OUTEP3IF 0x00000008 /**< OUT EP3 Interrupt flag */
133 #define USB_OIF_OUTEP2IF 0x00000004 /**< OUT EP2 Interrupt flag */
134 #define USB_OIF_OUTEP1IF 0x00000002 /**< OUT EP1 Interrupt flag */
135 /** @} */
136 /*---------------------------------------------------------------------------*/
137 /**
138  * \name USB_CIF Register Bit-Masks
139  * @{
140  */
141 #define USB_CIF_SOFIF 0x00000008 /**< Start-of-frame interrupt flag */
142 #define USB_CIF_RSTIF 0x00000004 /**< Reset interrupt flag */
143 #define USB_CIF_RESUMEIF 0x00000002 /**< Resume interrupt flag */
144 #define USB_CIF_SUSPENDIF 0x00000001 /**< Suspend interrupt flag */
145 /** @} */
146 /*---------------------------------------------------------------------------*/
147 /**
148  * \name USB_IIE Register Bit-Masks
149  * @{
150  */
151 #define USB_IIE_INEP5IE 0x00000020 /**< IN EP5 interrupt enable */
152 #define USB_IIE_INEP4IE 0x00000010 /**< IN EP4 interrupt enable */
153 #define USB_IIE_INEP3IE 0x00000008 /**< IN EP3 interrupt enable */
154 #define USB_IIE_INEP2IE 0x00000004 /**< IN EP2 interrupt enable */
155 #define USB_IIE_INEP1IE 0x00000002 /**< IN EP1 interrupt enable */
156 #define USB_IIE_EP0IE 0x00000001 /**< EP0 interrupt enable */
157 /** @} */
158 /*---------------------------------------------------------------------------*/
159 /**
160  * \name USB_OIE Register Bit-Masks
161  * @{
162  */
163 #define USB_OIE_OUTEP5IE 0x00000020 /**< OUT EP5 interrupt enable */
164 #define USB_OIE_OUTEP4IE 0x00000010 /**< OUT EP4 interrupt enable */
165 #define USB_OIE_OUTEP3IE 0x00000008 /**< OUT EP3 interrupt enable */
166 #define USB_OIE_OUTEP2IE 0x00000004 /**< OUT EP2 interrupt enable */
167 #define USB_OIE_OUTEP1IE 0x00000002 /**< OUT EP1 interrupt enable */
168 /** @} */
169 /*---------------------------------------------------------------------------*/
170 /**
171  * \name USB_CIE Register Bit-Masks
172  * @{
173  */
174 #define USB_CIE_SOFIE 0x00000008 /**< Start-of-frame interrupt enable */
175 #define USB_CIE_RSTIE 0x00000004 /**< Reset interrupt enable */
176 #define USB_CIE_RESUMEIE 0x00000002 /**< Resume interrupt enable */
177 #define USB_CIE_SUSPENDIE 0x00000001 /**< Suspend interrupt enable */
178 /** @} */
179 /*---------------------------------------------------------------------------*/
180 /**
181  * \name USB_FRML Register Bit-Masks
182  * @{
183  */
184 #define USB_FRML_FRAME 0x000000FF /**< Low byte of 11-bit frame number */
185 /** @} */
186 /*---------------------------------------------------------------------------*/
187 /**
188  * \name USB_FRMH Register Bit-Masks
189  * @{
190  */
191 #define USB_FRMH_FRAME 0x00000007 /**< 3 MSBs of 11-bit frame number */
192 /** @} */
193 /*---------------------------------------------------------------------------*/
194 /**
195  * \name USB_INDEX Register Bit-Masks
196  * @{
197  */
198 #define USB_INDEX_USBINDEX 0x0000000F /**< Endpoint selected */
199 /** @} */
200 /*---------------------------------------------------------------------------*/
201 /**
202  * \name USB_CTRL Register Bit-Masks
203  * @{
204  */
205 #define USB_CTRL_PLL_LOCKED 0x00000080 /**< PLL locked status */
206 #define USB_CTRL_PLL_EN 0x00000002 /**< 48-MHz USB PLL enable */
207 #define USB_CTRL_USB_EN 0x00000001 /**< USB enable */
208 /** @} */
209 /*---------------------------------------------------------------------------*/
210 /**
211  * \name USB_MAXI Register Bit-Masks
212  * @{
213  */
214 #define USB_MAXI_USBMAXI 0x000000FF /**< Maximum packet size */
215 /** @} */
216 /*---------------------------------------------------------------------------*/
217 /**
218  * \name USB_CS0_CSIL Register Bit-Masks
219  * @{
220  */
221 /** Listed as reserved in the UG, is this right? */
222 #define USB_CS0_CLR_SETUP_END 0x00000080
223 
224 /** Deassert OUTPKT_RDY bit of this register or reset the data toggle to 0 */
225 #define USB_CS0_CSIL_CLR_OUTPKT_RDY_or_CLR_DATA_TOG 0x00000040
226 #define USB_CS0_CLR_OUTPKT_RDY 0x00000040
227 #define USB_CSIL_CLR_DATA_TOG 0x00000040
228 
229 /**
230  * Set this bit to 1 to terminate the current transaction or
231  * is set when a STALL handshake has been sent
232  */
233 #define USB_CS0_CSIL_SEND_STALL_or_SENT_STALL 0x00000020
234 #define USB_CS0_SEND_STALL 0x00000020
235 #define USB_CSIL_SENT_STALL 0x00000020
236 
237 /**
238  * Is set if the control transfer ends due to a premature end-of-control
239  * transfer or set to 1 to make the USB controller reply with a STALL handshake
240  * when receiving IN tokens
241  */
242 #define USB_CS0_CSIL_SETUP_END_or_SEND_STALL 0x00000010
243 #define USB_CS0_SETUP_END 0x00000010
244 #define USB_CSIL_SEND_STALL 0x00000010
245 
246 /**
247  * Signal the end of a data transfer or set to 1 to flush next packet that
248  * is ready to transfer from the IN FIFO
249  */
250 #define USB_CS0_CSIL_DATA_END_or_FLUSH_PACKET 0x00000008
251 #define USB_CS0_DATA_END 0x00000008
252 #define USB_CSIL_FLUSH_PACKET 0x00000008
253 
254 /**
255  * Set when a STALL handshake is sent or set if an IN token is received when
256  * INPKT_RDY = 0, and a zero-length data packet is transmitted in response to
257  * the IN token. In bulk/interrupt mode, this bit is set when a NAK is returned
258  * in response to an IN token
259  */
260 #define USB_CS0_CSIL_SENT_STALL_or_UNDERRUN 0x00000004
261 #define USB_CS0_SENT_STALL 0x00000004
262 #define USB_CSIL_UNDERRUN 0x00000004
263 
264 /**
265  * Data packet has been loaded into the EP0 FIFO or at least one packet in the
266  * IN FIFO
267  */
268 #define USB_CS0_CSIL_INPKT_RDY_or_PKT_PRESENT 0x00000002
269 #define USB_CS0_INPKT_RDY 0x00000002
270 #define USB_CSIL_PKT_PRESENT 0x00000002
271 
272 /** Data packet received or data packet has been loaded into the IN FIFO */
273 #define USB_CS0_CSIL_OUTPKT_RDY_or_INPKT_RDY 0x00000001
274 #define USB_CS0_OUTPKT_RDY 0x00000001
275 #define USB_CSIL_INPKT_RDY 0x00000001
276 
277 /** @} */
278 /*---------------------------------------------------------------------------*/
279 /**
280  * \name USB_CSIH Register Bit-Masks
281  * @{
282  */
283 #define USB_CSIH_AUTISET 0x00000080 /**< Auto-assert INPKT_RDY */
284 #define USB_CSIH_ISO 0x00000040 /**< Selects IN endpoint type */
285 #define USB_CSIH_FORCE_DATA_TOG 0x00000008 /**< IN EP force data toggle switch */
286 #define USB_CSIH_IN_DBL_BUF 0x00000001 /**< Double buffering enable (IN FIFO) */
287 /** @} */
288 /*---------------------------------------------------------------------------*/
289 /**
290  * \name USB_MAXO Register Bit-Masks
291  * @{
292  */
293 #define USB_MAXO_USBMAXO 0x000000FF /**< Maximum packet size */
294 /** @} */
295 /*---------------------------------------------------------------------------*/
296 /**
297  * \name USB_CSOL Register Bit-Masks
298  * @{
299  */
300 #define USB_CSOL_CLR_DATA_TOG 0x00000080 /**< Setting resets data toggle to 0 */
301 #define USB_CSOL_SENT_STALL 0x00000040 /**< STALL handshake sent */
302 #define USB_CSOL_SEND_STALL 0x00000020 /**< Reply with STALL to OUT tokens */
303 #define USB_CSOL_FLUSH_PACKET 0x00000010 /**< Flush next packet read from OUT FIFO */
304 #define USB_CSOL_DATA_ERROR 0x00000008 /**< CRC or bit-stuff error in RX packet */
305 #define USB_CSOL_OVERRUN 0x00000004 /**< OUT packet can not be loaded into OUT FIFO */
306 #define USB_CSOL_FIFO_FULL 0x00000002 /**< OUT FIFO full */
307 #define USB_CSOL_OUTPKT_RDY 0x00000001 /**< OUT packet read in OUT FIFO */
308 /** @} */
309 /*---------------------------------------------------------------------------*/
310 /**
311  * \name USB_CSOH Register Bit-Masks
312  * @{
313  */
314 #define USB_CSOH_AUTOCLEAR 0x00000080 /**< Auto-clear OUTPKT_RDY */
315 #define USB_CSOH_ISO 0x00000040 /**< Selects OUT endpoint type */
316 #define USB_CSOH_OUT_DBL_BUF 0x00000001 /**< Double buffering enable (OUT FIFO) */
317 /** @} */
318 /*---------------------------------------------------------------------------*/
319 /**
320  * \name USB_CNT0_CNTL Register Bit-Masks
321  * @{
322  */
323 #define USB_CNT0_CNTL_USBCNT0 0x0000003F /**< Number of RX bytes in EP0 FIFO */
324 #define USB_CNT0_USBCNT0 0x0000003F
325 
326 #define USB_CNT0_CNTL_USBCNT_5_0 0x0000003F /**< 6 LSBs of the number of RX
327  bytes in EP1-5 OUT FIFO */
328 #define USB_CNTL_USBCNT_5_0 0x0000003F
329 /** @} */
330 /*---------------------------------------------------------------------------*/
331 /**
332  * \name USB_CNTH Register Bit-Masks
333  * @{
334  */
335 #define USB_CNTH_USBCNT 0x00000007 /**< 3 MSBs of RX byte number */
336 /** @} */
337 /*---------------------------------------------------------------------------*/
338 /**
339  * \name USB_F[0-5] Register Bit-Masks
340  * @{
341  */
342 #define USB_F0_USBF0 0x000000FF /**< Endpoint 0 FIFO mask */
343 #define USB_F1_USBF1 0x000000FF /**< Endpoint 1 FIFO mask */
344 #define USB_F2_USBF2 0x000000FF /**< Endpoint 2 FIFO mask */
345 #define USB_F3_USBF3 0x000000FF /**< Endpoint 3 FIFO mask */
346 #define USB_F4_USBF4 0x000000FF /**< Endpoint 4 FIFO mask */
347 #define USB_F5_USBF5 0x000000FF /**< Endpoint 5 FIFO mask */
348 /** @} */
349 
350 #endif /* USB_REGS_H_ */
351 
352 /**
353  * @}
354  * @}
355  */
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