Contiki 3.x
maca.h
1 /*
2  * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
3  * to the MC1322x project (http://mc1322x.devl.org)
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of the Institute nor the names of its contributors
15  * may be used to endorse or promote products derived from this software
16  * without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * This file is part of libmc1322x: see http://mc1322x.devl.org
31  * for details.
32  *
33  *
34  */
35 
36 #ifndef MACA_H_
37 #define MACA_H_
38 
39 #include <packet.h>
40 #include <stdint.h>
41 #include <utils.h>
42 
43 /* maca initialization and on off routines */
44 void maca_init(void);
45 void maca_off(void);
46 void maca_on(void);
47 
48 /* run periodically to make sure the maca is still doing right */
49 void check_maca(void);
50 
51 /* maca configuration interface */
52 void set_power(uint8_t power);
53 void set_channel(uint8_t chan);
54 
55 extern uint8_t (*get_lqi)(void);
56 
57 #define DEMOD_DCD 1 /* -96dBm, 22.2mA */
58 #define DEMOD_NCD 0 /* -100dBm, 24.2mA */
59 void set_demodulator_type(uint8_t demod);
60 
61 /* set_fcs_mode(NO_FCS) to disable checksum filtering */
62 extern volatile uint8_t fcs_mode;
63 #define set_fcs_mode(x) fcs_mode = (x)
64 
65 /* set_prm_mode(PROMISC) to disable address filtering */
66 /* set_prm_mode(AUTOACK) to enable address filtering AND autoack */
67 extern volatile uint8_t prm_mode;
68 #define set_prm_mode(x) prm_mode = (x)
69 
70 /* maca packet interface */
71 void tx_packet(volatile packet_t *p);
72 volatile packet_t* rx_packet(void);
73 volatile packet_t* get_free_packet(void);
74 void maca_free_packet(volatile packet_t *p);
75 void free_all_packets(void);
76 
77 extern volatile packet_t *rx_head, *tx_head;
78 extern volatile uint32_t maca_entry;
79 
80 extern void maca_rx_callback(volatile packet_t *p) __attribute__((weak));
81 extern void maca_tx_callback(volatile packet_t *p) __attribute__((weak));
82 
83 /* maca lowlevel routines */
84 /* most applications won't need to use them */
85 void reset_maca(void);
86 void init_phy(void);
87 void flyback_init(void);
88 void ResumeMACASync(void);
89 void radio_init(void);
90 uint32_t init_from_flash(uint32_t addr);
91 
92 /* maca_pwr indicates whether the radio is on or off */
93 /* Test it before accessing any radio function or the CPU may hang */
94 extern volatile uint8_t maca_pwr;
95 
96 #define MAX_PACKET_SIZE (MAX_PAYLOAD_SIZE + 2) /* packet includes 2 bytes of checksum */
97 
98 /* maca register and field defines */
99 
100 #define MACA_BASE (0x80004000)
101 #define MACA_RESET ((volatile uint32_t *) (MACA_BASE+0x04))
102 #define MACA_RANDOM ((volatile uint32_t *) (MACA_BASE+0x08))
103 #define MACA_CONTROL ((volatile uint32_t *) (MACA_BASE+0x0c))
104 
105 /* MACA_CONTROL bits and fields */
106 #define ISM 20
107 #define PRECOUNT 16 /* preamble reapeat counter */
108 #define PRECOUNT_MASK bit_mask(4,PRECOUNT)
109 #define RTSO 15 /* reset slot counter */
110 #define ROLE 13 /* set if PAN coordinator */
111 #define NOFC 12 /* set to disable FCS */
112 enum {
113  USE_FCS = 0,
114  NO_FCS = 1,
115 };
116 #define PRM 11 /* set for promiscuous mode */
117 enum {
118  AUTOACK = 0,
119  PROMISC = 1,
120 };
121 #define REL 10 /* 1 for relative, 0 for absolute */
122 #define ASAP 9 /* 1 start now, 0 timer start */
123 #define BCN 8 /* 1 beacon only, 0 for a */
124 #define AUTO 7 /* 1 continuous rx, rx only once */
125 #define LFSR 6 /* 1 use polynomial for Turbolink */
126 #define TM 5
127 
128 #define MACA_MODE 3
129 #define MODE_MASK bit_mask(2,MACA_MODE)
130 #define NO_CCA 0
131 #define NO_SLOT_CCA 1
132 #define SLOT_CCA 2
133 
134 #define SEQUENCE 0
135 #define SEQUENCE_MASK bit_mask(3,SEQUENCE)
136 /* end of MACA_CONTROL bits and fields */
137 
138 #define MACA_STATUS ((volatile uint32_t *) (MACA_BASE+0x10))
139 /* MACA_STATUS bits and fields */
140 #define STATUS_TIMEOUT 15
141 #define CRC 14
142 #define BUSY 13
143 #define OVR 12
144 #define CODE 0
145 #define CODE_MASK bit_mask(4,CODE)
146 /* status codes */
147 #define SUCCESS 0
148 #define CODE_TIMEOUT 1
149 #define CHANNEL_BUSY 2
150 #define CRC_FAILED 3
151 #define ABORTED 4
152 #define NO_ACK 5
153 #define NO_DATA 6
154 #define LATE_START 7
155 #define EXT_TIMEOUT 8
156 #define EXT_PND_TIMEOUT 9
157 #define PLL_UNLOCK 12
158 #define EXTERNAL_ABORT 13
159 #define NOT_COMPLETED 14
160 #define DMA_BUS_ERROR 15
161 /* end of MACA_CONTROL bits and fields */
162 
163 #define MACA_FRMPND ((volatile uint32_t *) (MACA_BASE+0x14))
164 #define MACA_TMREN ((volatile uint32_t *) (MACA_BASE+0x40))
165 #define MACA_TMRDIS ((volatile uint32_t *) (MACA_BASE+0x44))
166 #define MACA_CLK ((volatile uint32_t *) (MACA_BASE+0x48))
167 #define MACA_STARTCLK ((volatile uint32_t *) (MACA_BASE+0x4c))
168 #define MACA_CPLCLK ((volatile uint32_t *) (MACA_BASE+0x50))
169 #define MACA_SFTCLK ((volatile uint32_t *) (MACA_BASE+0x54))
170 #define MACA_CLKOFFSET ((volatile uint32_t *) (MACA_BASE+0x58))
171 #define MACA_RELCLK ((volatile uint32_t *) (MACA_BASE+0x5c))
172 #define MACA_CPLTIM ((volatile uint32_t *) (MACA_BASE+0x60))
173 #define MACA_SLOTOFFSET ((volatile uint32_t *) (MACA_BASE+0x64))
174 #define MACA_TIMESTAMP ((volatile uint32_t *) (MACA_BASE+0x68))
175 #define MACA_DMARX ((volatile uint32_t *) (MACA_BASE+0x80))
176 #define MACA_DMATX ((volatile uint32_t *) (MACA_BASE+0x84))
177 #define MACA_DMAPOLL ((volatile uint32_t *) (MACA_BASE+0x88))
178 #define MACA_TXLEN ((volatile uint32_t *) (MACA_BASE+0x8c))
179 #define MACA_TXSEQNR ((volatile uint32_t *) (MACA_BASE+0x90))
180 #define MACA_SETRXLVL ((volatile uint32_t *) (MACA_BASE+0x94))
181 #define MACA_GETRXLVL ((volatile uint32_t *) (MACA_BASE+0x98))
182 #define MACA_IRQ ((volatile uint32_t *) (MACA_BASE+0xc0))
183 #define MACA_CLRIRQ ((volatile uint32_t *) (MACA_BASE+0xc4))
184 #define MACA_SETIRQ ((volatile uint32_t *) (MACA_BASE+0xc8))
185 #define MACA_MASKIRQ ((volatile uint32_t *) (MACA_BASE+0xcc))
186 #define MACA_MACPANID ((volatile uint32_t *) (MACA_BASE+0x100))
187 #define MACA_MAC16ADDR ((volatile uint32_t *) (MACA_BASE+0x104))
188 #define MACA_MAC64HI ((volatile uint32_t *) (MACA_BASE+0x108))
189 #define MACA_MAC64LO ((volatile uint32_t *) (MACA_BASE+0x10c))
190 #define MACA_FLTREJ ((volatile uint32_t *) (MACA_BASE+0x110))
191 #define MACA_CLKDIV ((volatile uint32_t *) (MACA_BASE+0x114))
192 #define MACA_WARMUP ((volatile uint32_t *) (MACA_BASE+0x118))
193 #define MACA_PREAMBLE ((volatile uint32_t *) (MACA_BASE+0x11c))
194 #define MACA_WHITESEED ((volatile uint32_t *) (MACA_BASE+0x120))
195 #define MACA_FRAMESYNC0 ((volatile uint32_t *) (MACA_BASE+0x124))
196 #define MACA_FRAMESYNC1 ((volatile uint32_t *) (MACA_BASE+0x128))
197 #define MACA_TXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x140))
198 #define MACA_RXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x144))
199 #define MACA_EOFDELAY ((volatile uint32_t *) (MACA_BASE+0x148))
200 #define MACA_CCADELAY ((volatile uint32_t *) (MACA_BASE+0x14c))
201 #define MACA_RXEND ((volatile uint32_t *) (MACA_BASE+0x150))
202 #define MACA_TXCCADELAY ((volatile uint32_t *) (MACA_BASE+0x154))
203 #define MACA_KEY3 ((volatile uint32_t *) (MACA_BASE+0x158))
204 #define MACA_KEY2 ((volatile uint32_t *) (MACA_BASE+0x15c))
205 #define MACA_KEY1 ((volatile uint32_t *) (MACA_BASE+0x160))
206 #define MACA_KEY0 ((volatile uint32_t *) (MACA_BASE+0x164))
207 #define MACA_OPTIONS ((volatile uint32_t *) (MACA_BASE+0x180))
208 
209 
210 /******************************************************************************/
211 /* everything under this comment is messy, needs cleaning, and will */
212 /* probably change in the future */
213 /******************************************************************************/
214 
215 #define control_pre_count (7<<16) /* preamble reapeat counter */
216 #define control_rst_slot (1<<15) /* reset slot counter */
217 #define control_role (1<<13) /* set if PAN coordinator */
218 #define control_nofc (1<<12) /* set to disable FCS */
219 #define control_prm (1<<11) /* set for promiscuous mode */
220 #define control_relative (1<<10) /* 1 for relative, 0 for absolute */
221 #define control_asap (1<<9) /* 1 start now, 0 timer start */
222 #define control_bcn (1<<8) /* 1 beacon only, 0 for a */
223 #define control_auto (1<<7) /* 1 continuous rx, rx only once */
224 #define control_lfsr (1<<6) /* 1 use polynomial for Turbolink */
225 
226 #define gMACA_Clock_DIV_c 95
227 
228 //rom_base_adr equ 0x00000000 ; rom base address
229 //ram_base_adr equ 0x00400000 ; ram base address
230 //ram0_base_adr equ 0x00400000 ; ram0 base address (2K words = 8K
231 //bytes)
232 //ram1_base_adr equ 0x00402000 ; ram1 base address (6K words = 24K
233 //bytes)
234 //ram2_base_adr equ 0x00408000 ; ram2 base address (8K words = 32K
235 //bytes)
236 //ram3_base_adr equ 0x00410000 ; ram3 base address (8K words
237 enum {
238  cc_success = 0,
239  cc_timeout = 1,
240  cc_channel_busy = 2,
241  cc_crc_fail = 3,
242  cc_aborted = 4,
243  cc_no_ack = 5,
244  cc_no_data = 6,
245  cc_late_start = 7,
246  cc_ext_timeout = 8,
247  cc_ext_pnd_timeout = 9,
248  cc_nc1 = 10,
249  cc_nc2 = 11,
250  cc_nc3 = 12,
251  cc_cc_external_abort= 13,
252  cc_not_completed = 14,
253  cc_bus_error = 15
254 };
255 //control codes for mode bits
256 
257 enum {
258  control_mode_no_cca = 0,
259  control_mode_non_slotted = (1<<3),
260  control_mode_slotted = (1<<4)
261 };
262 //control codes for sequence bits
263 enum {
264  control_seq_nop = 0,
265  control_seq_abort = 1,
266  control_seq_wait = 2,
267  control_seq_tx = 3,
268  control_seq_rx = 4,
269  control_seq_txpoll = 5,
270  control_seq_cca = 6,
271  control_seq_ed = 7
272 };
273 
274 #define maca_version (*((volatile uint32_t *)(0x80004000)))
275 #define maca_reset (*((volatile uint32_t *)(0x80004004)))
276 #define maca_random (*((volatile uint32_t *)(0x80004008)))
277 #define maca_control (*((volatile uint32_t *)(0x8000400c)))
278 #define maca_status (*((volatile uint32_t *)(0x80004010)))
279 #define maca_frmpnd (*((volatile uint32_t *)(0x80004014)))
280 
281 #define maca_edvalue (*((volatile uint32_t *)(0x8000401c)))
282 #define maca_tmren (*((volatile uint32_t *)(0x80004040)))
283 #define maca_tmrdis (*((volatile uint32_t *)(0x80004044)))
284 #define maca_clk (*((volatile uint32_t *)(0x80004048)))
285 #define maca_startclk (*((volatile uint32_t *)(0x8000404c)))
286 #define maca_cplclk (*((volatile uint32_t *)(0x80004050)))
287 #define maca_sftclk (*((volatile uint32_t *)(0x80004054)))
288 #define maca_clkoffset (*((volatile uint32_t *)(0x80004058)))
289 #define maca_relclk (*((volatile uint32_t *)(0x8000405c)))
290 #define maca_cpltim (*((volatile uint32_t *)(0x80004060)))
291 #define maca_slotoffset (*((volatile uint32_t *)(0x80004064)))
292 #define maca_timestamp (*((volatile uint32_t *)(0x80004068)))
293 #define maca_dmarx (*((volatile uint32_t *)(0x80004080)))
294 #define maca_dmatx (*((volatile uint32_t *)(0x80004084)))
295 #define maca_dmatxpoll (*((volatile uint32_t *)(0x80004088)))
296 #define maca_txlen (*((volatile uint32_t *)(0x8000408c)))
297 #define maca_txseqnr (*((volatile uint32_t *)(0x80004090)))
298 #define maca_setrxlvl (*((volatile uint32_t *)(0x80004094)))
299 #define maca_getrxlvl (*((volatile uint32_t *)(0x80004098)))
300 #define maca_irq (*((volatile uint32_t *)(0x800040c0)))
301 #define maca_clrirq (*((volatile uint32_t *)(0x800040c4)))
302 #define maca_setirq (*((volatile uint32_t *)(0x800040c8)))
303 #define maca_maskirq (*((volatile uint32_t *)(0x800040cc)))
304 #define maca_panid (*((volatile uint32_t *)(0x80004100)))
305 #define maca_addr16 (*((volatile uint32_t *)(0x80004104)))
306 #define maca_maca64hi (*((volatile uint32_t *)(0x80004108)))
307 #define maca_maca64lo (*((volatile uint32_t *)(0x8000410c)))
308 #define maca_fltrej (*((volatile uint32_t *)(0x80004110)))
309 #define maca_divider (*((volatile uint32_t *)(0x80004114)))
310 #define maca_warmup (*((volatile uint32_t *)(0x80004118)))
311 #define maca_preamble (*((volatile uint32_t *)(0x8000411c)))
312 #define maca_whiteseed (*((volatile uint32_t *)(0x80004120)))
313 #define maca_framesync (*((volatile uint32_t *)(0x80004124)))
314 #define maca_framesync2 (*((volatile uint32_t *)(0x80004128)))
315 #define maca_txackdelay (*((volatile uint32_t *)(0x80004140)))
316 #define maca_rxackdelay (*((volatile uint32_t *)(0x80004144)))
317 #define maca_eofdelay (*((volatile uint32_t *)(0x80004148)))
318 #define maca_ccadelay (*((volatile uint32_t *)(0x8000414c)))
319 #define maca_rxend (*((volatile uint32_t *)(0x80004150)))
320 #define maca_txccadelay (*((volatile uint32_t *)(0x80004154)))
321 #define maca_key3 (*((volatile uint32_t *)(0x80004158)))
322 #define maca_key2 (*((volatile uint32_t *)(0x80004158)))
323 #define maca_key1 (*((volatile uint32_t *)(0x80004158)))
324 #define maca_key0 (*((volatile uint32_t *)(0x80004158)))
325 
326 
327 typedef union maca_version_reg_tag
328 {
329  struct
330  {
331  uint32_t MINOR:8;
332  uint32_t RESERVED1:8;
333  uint32_t MAJOR:8;
334  uint32_t RESERVED2:8;
335  } Bits;
336  uint32_t Reg;
337 } maca_version_reg_t;
338 
339 #define maca_version_reg_st ((maca_version_reg_t)(maca_version))
340 
341 
342 typedef union maca_reset_reg_tag
343 {
344  struct
345  {
346  uint32_t RESERVED:30;
347  uint32_t CLK_ON:1;
348  uint32_t RST:1;
349  } Bits;
350  uint32_t Reg;
351 } maca_reset_reg_t;
352 
353 #define maca_reset_reg_st ((maca_reset_reg_t)(maca_reset))
354 
355 
356 /* typedef union maca_ctrl_reg_tag */
357 /* { */
358 /* struct */
359 /* { */
360 /* uint32_t RESERVED:11; */
361 /* uint32_t ISM:1; */
362 /* uint32_t PRE_COUNT:4; */
363 /* uint32_t RSTO:1; */
364 /* uint32_t RSV:1; */
365 /* uint32_t ROLE:1; */
366 /* uint32_t NOFC:1; */
367 /* uint32_t PRM:1; */
368 /* uint32_t rel:1; */
369 /* uint32_t ASAP:1; */
370 /* uint32_t BCN:1; */
371 /* uint32_t AUTO:1; */
372 /* uint32_t LFSR:1; */
373 /* uint32_t TM:1; */
374 /* uint32_t MODE:2; */
375 /* uint32_t SEQUENCE:3; */
376 /* } Bits; */
377 /* uint32_t Reg; */
378 /* } maca_ctrl_reg_t; */
379 
380 #define maca_control_ism (1<<20)
381 #define maca_control_zigbee (~maca_control_ism)
382 
383 #define maca_ctrl_reg_st ((maca_ctrl_reg_t *)(&maca_reset))
384 #define _set_maca_test_mode(x) (maca_ctrl_reg_st->Bits.TM = x)
385 #define _set_maca_sequence(x) (maca_ctrl_reg_st->Bits.SEQUENCE = x)
386 #define _set_maca_asap(x) (maca_ctrl_reg_st->Bits.ASAP = x)
387 
388 
389 #define MACA_CTRL_ZIGBEE_MODE (0)
390 #define MACA_CTRL_ISM_MODE (1)
391 #define MACA_CTRL_PRM_NORMAL_MODE (0)
392 #define MACA_CTRL_PRM_PROMISCUOUS_MODE (1)
393 #define MACA_CTRL_BCN_ALL (0)
394 #define MACA_CTRL_BCN_BEACON (1)
395 #define MACA_CTRL_TM_NORMAL (0)
396 #define MACA_CTRL_TM_TEST (1)
397 #define MACA_CTRL_MODE_NO_CCA (0)
398 #define MACA_CTRL_MODE_NON_SLOTTED (1)
399 #define MACA_CTRL_MODE_SLOTTED (2)
400 
401 typedef enum maca_freq_chann_tag
402 {
403  SMAC_CHANN_11 = 0,
404  SMAC_CHANN_12,
405  SMAC_CHANN_13,
406  SMAC_CHANN_14,
407  SMAC_CHANN_15,
408  SMAC_CHANN_16,
409  SMAC_CHANN_17,
410  SMAC_CHANN_18,
411  SMAC_CHANN_19,
412  SMAC_CHANN_20,
413  SMAC_CHANN_21,
414  SMAC_CHANN_22,
415  SMAC_CHANN_23,
416  SMAC_CHANN_24,
417  SMAC_CHANN_25,
418  SMAC_CHANN_26,
419  MAX_SMAC_CHANNELS
420 } maca_freq_chann_t;
421 
422 
423 /* Sequence complete codes */
424 enum maca_complete_code {
425  maca_cc_success = 0,
426  maca_cc_timeout = 1,
427  maca_cc_channel_busy = 2,
428  maca_cc_crc_fail = 3,
429  maca_cc_aborted = 4,
430  maca_cc_no_ack = 5,
431  maca_cc_no_data = 6,
432  maca_cc_late_start = 7,
433  maca_cc_ext_timeout = 8,
434  maca_cc_ext_pnd_timeout = 9,
435  maca_cc_nc1 = 10,
436  maca_cc_nc2 = 11,
437  maca_cc_nc3 = 12,
438  maca_cc_cc_external_abort= 13,
439  maca_cc_not_completed = 14,
440  maca_cc_bus_error = 15
441 };
442 
443 /* control sequence codes */
444 enum maca_ctrl_seq {
445  maca_ctrl_seq_nop = 0,
446  maca_ctrl_seq_abort = 1,
447  maca_ctrl_seq_wait = 2,
448  maca_ctrl_seq_tx = 3,
449  maca_ctrl_seq_rx = 4,
450  maca_ctrl_seq_txpoll = 5,
451  maca_ctrl_seq_cca = 6,
452  maca_ctrl_seq_ed = 7
453 };
454 
455 /* transmission modes */
456 enum maca_ctrl_modes {
457  maca_ctrl_mode_no_cca = 0,
458  maca_ctrl_mode_non_slotted_csma_ca = 1,
459  maca_ctrl_mode_slotted_csma_ca = 2,
460 };
461 
462 /* MACA_CONTROL bits */
463 enum maca_ctrl_bits {
464  maca_ctrl_seq = 0, /* 3 bits */
465  maca_ctrl_mode = 3, /* 2 bits */
466  maca_ctrl_tm = 5,
467  maca_ctrl_lfsr = 6,
468  maca_ctrl_auto = 7,
469  maca_ctrl_bcn = 8,
470  maca_ctrl_asap = 9,
471  maca_ctrl_rel = 10,
472  maca_ctrl_prm = 11,
473  maca_ctrl_nofc = 12,
474  maca_ctrl_role = 13,
475  /* 14 reserved */
476  maca_ctrl_rsto = 15,
477  maca_ctrl_pre_count = 16, /* 4 bits */
478  maca_ctrl_ism = 20,
479 };
480 
481 /* MACA_IRQ bits */
482 enum maca_irqs {
483  maca_irq_acpl = 0,
484  maca_irq_poll = 1,
485  maca_irq_di = 2,
486  maca_irq_wu = 3,
487  maca_irq_rst = 4,
488  maca_irq_lvl = 9,
489  maca_irq_sftclk = 10,
490  maca_irq_flt = 11,
491  maca_irq_crc = 12,
492  maca_irq_cm = 13,
493  maca_irq_sync = 14,
494  maca_irq_strt = 15,
495 };
496 
497 /* MACA_RESET bits */
498 enum maca_reset_bits {
499  maca_reset_rst = 0,
500  maca_reset_clkon = 1,
501 };
502 
503 /* MACA_TMREN bits */
504 enum maca_tmren_bits {
505  maca_tmren_strt = 0,
506  maca_tmren_cpl = 1,
507  maca_tmren_sft = 2,
508 };
509 
510 enum maca_status_bits {
511  maca_status_ovr = 12,
512  maca_status_busy = 13,
513  maca_status_crc = 14,
514  maca_status_to = 15,
515 };
516 
517 #define action_complete_irq() bit_is_set(*MACA_IRQ,maca_irq_acpl)
518 #define filter_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_flt)
519 #define checksum_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_crc)
520 #define data_indication_irq() bit_is_set(*MACA_IRQ,maca_irq_di)
521 #define softclock_irq() bit_is_set(*MACA_IRQ,maca_irq_sftclk)
522 #define poll_irq() bit_is_set(*MACA_IRQ,maca_irq_poll)
523 
524 #define status_is_not_completed() ((*MACA_STATUS & 0xffff) == maca_cc_not_completed)
525 #define status_is_success() ((*MACA_STATUS & 0xffff) == maca_cc_success)
526 
527 #define SMAC_MACA_CNTL_INIT_STATE ( control_prm | control_nofc | control_mode_non_slotted )
528 
529 #define MACA_WRITE(reg, src) (reg = src)
530 #define MACA_READ(reg) reg
531 
532 #endif //MACA_H_
__attribute__
void __attribute__((interrupt))
This ISR handles most of the business interacting with the 1-wire bus.
Definition: onewire.c:174
RST
#define RST
Pin number that corresponds to the RST pin.
Definition: hal.h:251
radio_init
radio_status_t radio_init(bool cal_rc_osc, hal_rx_start_isr_event_handler_t rx_event, hal_trx_end_isr_event_handler_t trx_end_event, radio_rx_callback rx_callback)
Initialize the Transceiver Access Toolbox and lower layers.
Definition: radio.c:160
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