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platform-conf.h
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1 /*
2  * Copyright (c) 2010, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  */
30 
31 /**
32  * \file
33  * A brief description of what this file is
34  * \author
35  * Niclas Finne <nfi@sics.se>
36  * Joakim Eriksson <joakime@sics.se>
37  */
38 
39 #ifndef PLATFORM_CONF_H_
40 #define PLATFORM_CONF_H_
41 
42 /*
43  * Definitions below are dictated by the hardware and not really
44  * changeable!
45  */
46 /* Platform TMOTE_SKY */
47 #define TMOTE_SKY 1
48 
49 #define PLATFORM_HAS_LEDS 1
50 #define PLATFORM_HAS_BUTTON 1
51 #define PLATFORM_HAS_LIGHT 1
52 #define PLATFORM_HAS_BATTERY 1
53 #define PLATFORM_HAS_SHT11 1
54 #define PLATFORM_HAS_RADIO 1
55 
56 /* CPU target speed in Hz */
57 #define F_CPU 3900000uL /*2457600uL*/
58 
59 /* Our clock resolution, this is the same as Unix HZ. */
60 #define CLOCK_CONF_SECOND 128UL
61 
62 #define BAUD2UBR(baud) ((F_CPU/baud))
63 
64 #define CCIF
65 #define CLIF
66 
67 #define HAVE_STDINT_H
68 #include "msp430def.h"
69 
70 
71 /* Types for clocks and uip_stats */
72 typedef unsigned short uip_stats_t;
73 typedef unsigned long clock_time_t;
74 typedef unsigned long off_t;
75 
76 /* the low-level radio driver */
77 #define NETSTACK_CONF_RADIO cc2420_driver
78 
79 /* LED ports */
80 #define LEDS_PxDIR P5DIR
81 #define LEDS_PxOUT P5OUT
82 #define LEDS_CONF_RED 0x10
83 #define LEDS_CONF_GREEN 0x20
84 #define LEDS_CONF_YELLOW 0x40
85 
86 /* DCO speed resynchronization for more robust UART, etc. */
87 #ifndef DCOSYNCH_CONF_ENABLED
88 #define DCOSYNCH_CONF_ENABLED 1
89 #endif /* DCOSYNCH_CONF_ENABLED */
90 #ifndef DCOSYNCH_CONF_PERIOD
91 #define DCOSYNCH_CONF_PERIOD 30
92 #endif /* DCOSYNCH_CONF_PERIOD */
93 
94 #define ROM_ERASE_UNIT_SIZE 512
95 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
96 
97 
98 #define CFS_CONF_OFFSET_TYPE long
99 
100 
101 /* Use the first 64k of external flash for node configuration */
102 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
103 
104 /* Use the second 64k of external flash for codeprop. */
105 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
106 
107 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
108 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
109 
110 #define CFS_RAM_CONF_SIZE 4096
111 
112 /*
113  * SPI bus configuration for the TMote Sky.
114  */
115 
116 /* SPI input/output registers. */
117 #define SPI_TXBUF U0TXBUF
118 #define SPI_RXBUF U0RXBUF
119 
120  /* USART0 Tx ready? */
121 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
122  /* USART0 Rx ready? */
123 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
124  /* USART0 Tx buffer ready? */
125 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
126 
127 #define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
128 #define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
129 #define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
130 
131 /*
132  * SPI bus - M25P80 external flash configuration.
133  */
134 
135 #define FLASH_PWR 3 /* P4.3 Output */
136 #define FLASH_CS 4 /* P4.4 Output */
137 #define FLASH_HOLD 7 /* P4.7 Output */
138 
139 /* Enable/disable flash access to the SPI bus (active low). */
140 
141 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
142 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
143 
144 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
145 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
146 
147 /*
148  * SPI bus - CC2420 pin configuration.
149  */
150 
151 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800
152 
153 /* P1.0 - Input: FIFOP from CC2420 */
154 #define CC2420_FIFOP_PORT(type) P1##type
155 #define CC2420_FIFOP_PIN 0
156 /* P1.3 - Input: FIFO from CC2420 */
157 #define CC2420_FIFO_PORT(type) P1##type
158 #define CC2420_FIFO_PIN 3
159 /* P1.4 - Input: CCA from CC2420 */
160 #define CC2420_CCA_PORT(type) P1##type
161 #define CC2420_CCA_PIN 4
162 /* P4.1 - Input: SFD from CC2420 */
163 #define CC2420_SFD_PORT(type) P4##type
164 #define CC2420_SFD_PIN 1
165 /* P4.2 - Output: SPI Chip Select (CS_N) */
166 #define CC2420_CSN_PORT(type) P4##type
167 #define CC2420_CSN_PIN 2
168 /* P4.5 - Output: VREG_EN to CC2420 */
169 #define CC2420_VREG_PORT(type) P4##type
170 #define CC2420_VREG_PIN 5
171 /* P4.6 - Output: RESET_N to CC2420 */
172 #define CC2420_RESET_PORT(type) P4##type
173 #define CC2420_RESET_PIN 6
174 
175 #define CC2420_IRQ_VECTOR PORT1_VECTOR
176 
177 /* Pin status. */
178 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
179 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
180 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
181 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
182 
183 /* The CC2420 reset pin. */
184 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
185 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
186 
187 /* CC2420 voltage regulator enable pin. */
188 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
189 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
190 
191 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
192 #define CC2420_FIFOP_INT_INIT() do { \
193  CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
194  CC2420_CLEAR_FIFOP_INT(); \
195  } while(0)
196 
197 /* FIFOP on external interrupt 0. */
198 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
199 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
200 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
201 
202 /*
203  * Enables/disables CC2420 access to the SPI bus (not the bus).
204  * (Chip Select)
205  */
206 
207  /* ENABLE CSn (active low) */
208 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
209  /* DISABLE CSn (active low) */
210 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
211 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
212 
213 #endif /* PLATFORM_CONF_H_ */
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