Contiki 3.x
nvic.c
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538-nvic
33  * @{
34  *
35  * \file
36  * Driver for the cc2538 NVIC
37  * All interrupt-related functionality is implemented here
38  */
39 #include "contiki.h"
40 #include "dev/nvic.h"
41 #include "dev/scb.h"
42 #include "reg.h"
43 
44 #include <stdint.h>
45 
46 static uint32_t *interrupt_enable;
47 static uint32_t *interrupt_disable;
48 static uint32_t *interrupt_pend;
49 static uint32_t *interrupt_unpend;
50 /*---------------------------------------------------------------------------*/
51 void
53 {
54  interrupt_enable = (uint32_t *)NVIC_EN0;
55  interrupt_disable = (uint32_t *)NVIC_DIS0;
56  interrupt_pend = (uint32_t *)NVIC_PEND0;
57  interrupt_unpend = (uint32_t *)NVIC_UNPEND0;
58 
59  /* Provide our interrupt table to the NVIC */
60  REG(SCB_VTABLE) = (NVIC_CONF_VTABLE_BASE | NVIC_CONF_VTABLE_OFFSET);
61 }
62 /*---------------------------------------------------------------------------*/
63 void
64 nvic_interrupt_enable(uint32_t intr)
65 {
66  /* Writes of 0 are ignored, which is why we can simply use = */
67  interrupt_enable[intr >> 5] = 1 << (intr & 0x1F);
68 }
69 /*---------------------------------------------------------------------------*/
70 void
71 nvic_interrupt_disable(uint32_t intr)
72 {
73  /* Writes of 0 are ignored, which is why we can simply use = */
74  interrupt_disable[intr >> 5] = 1 << (intr & 0x1F);
75 }
76 /*---------------------------------------------------------------------------*/
77 void
78 nvic_interrupt_en_restore(uint32_t intr, uint8_t v)
79 {
80  if(v != 1) {
81  return;
82  }
83 
84  interrupt_enable[intr >> 5] = 1 << (intr & 0x1F);
85 }
86 /*---------------------------------------------------------------------------*/
87 uint8_t
88 nvic_interrupt_en_save(uint32_t intr)
89 {
90  uint8_t rv = ((interrupt_enable[intr >> 5] & (1 << (intr & 0x1F)))
91  > NVIC_INTERRUPT_DISABLED);
92 
94 
95  return rv;
96 }
97 /*---------------------------------------------------------------------------*/
98 void
99 nvic_interrupt_pend(uint32_t intr)
100 {
101  /* Writes of 0 are ignored, which is why we can simply use = */
102  interrupt_pend[intr >> 5] = 1 << (intr & 0x1F);
103 }
104 /*---------------------------------------------------------------------------*/
105 void
106 nvic_interrupt_unpend(uint32_t intr)
107 {
108  /* Writes of 0 are ignored, which is why we can simply use = */
109  interrupt_unpend[intr >> 5] = 1 << (intr & 0x1F);
110 }
111 /** @} */
#define NVIC_DIS0
Interrupt 0-31 Clear Enable.
Definition: nvic.h:116
void nvic_interrupt_pend(uint32_t intr)
Sets intr to pending.
Definition: nvic.c:99
Header file for the ARM Nested Vectored Interrupt Controller.
void nvic_interrupt_disable(uint32_t intr)
Disables interrupt intr.
Definition: nvic.c:71
Header file for the System Control Block (SCB)
void nvic_init()
Initialises the NVIC driver.
Definition: nvic.c:52
#define SCB_VTABLE
Vector Table Offset.
Definition: scb.h:46
void nvic_interrupt_enable(uint32_t intr)
Enables interrupt intr.
Definition: nvic.c:64
Header file with register manipulation macro definitions.
void nvic_interrupt_unpend(uint32_t intr)
Sets intr to no longer pending.
Definition: nvic.c:106
#define NVIC_UNPEND0
Interrupt 0-31 Clear Pending.
Definition: nvic.h:126
#define NVIC_EN0
Interrupt 0-31 Set Enable.
Definition: nvic.h:111
#define NVIC_PEND0
Interrupt 0-31 Set Pending.
Definition: nvic.h:121
uint8_t nvic_interrupt_en_save(uint32_t intr)
Checks the interrupt enabled status for intr.
Definition: nvic.c:88
void nvic_interrupt_en_restore(uint32_t intr, uint8_t v)
Enables interrupt intr if v &gt; 0.
Definition: nvic.c:78