Contiki 3.x
m25p16.h
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1 /*
2  * Copyright (c) 2010, Loughborough University - Computer Science
3  * All rights reserved.
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27  * SUCH DAMAGE.
28  *
29  * This file is part of the Contiki operating system.
30  */
31 
32 /**
33  * \file
34  * Header file for the control of the M25P16 on sensinode N740s.
35  *
36  * \author
37  * George Oikonomou - <oikonomou@users.sourceforge.net>
38  */
39 
40 #ifndef M25P16_H_
41 #define M25P16_H_
42 
43 /* Instruction Set */
44 #define M25P16_I_WREN 0x06 /* Write Enable */
45 #define M25P16_I_WRDI 0x04 /* Write Disable */
46 #define M25P16_I_RDID 0x9F /* Read Identification */
47 #define M25P16_I_RDSR 0x05 /* Read Status Register */
48 #define M25P16_I_WRSR 0x01 /* Write Status Register */
49 #define M25P16_I_READ 0x03 /* Read Data Bytes */
50 #define M25P16_I_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */
51 #define M25P16_I_PP 0x02 /* Page Program */
52 #define M25P16_I_SE 0xD8 /* Sector Erase */
53 #define M25P16_I_BE 0xC7 /* Bulk Erase */
54 #define M25P16_I_DP 0xB9 /* Deep Power-down */
55 #define M25P16_I_RES 0xAB /* Release from Deep Power-down */
56 
57 /* Dummy Byte - Used in FAST_READ and RES */
58 #define M25P16_DUMMY_BYTE 0x00
59 
60 /* Pins */
61 #define M25P16_PIN_CLOCK P1_5
62 #define M25P16_PIN_SER_I P1_6
63 #define M25P16_PIN_SER_O P1_7
64 
65 /* Status Register Bits */
66 #define M25P16_SR_SRWD 0x80 /* Status Register Write Disable */
67 #define M25P16_SR_BP2 0x10 /* Block Protect 2 */
68 #define M25P16_SR_BP1 0x08 /* Block Protect 1 */
69 #define M25P16_SR_BP0 0x04 /* Block Protect 0 */
70 #define M25P16_SR_BP 0x1C /* All Block Protect Bits */
71 #define M25P16_SR_WEL 0x02 /* Write Enable Latch */
72 #define M25P16_SR_WIP 0x01 /* Write in Progress */
73 
74 /* Do we use READ or FAST_READ to read? Fast by default */
75 #ifdef M25P16_CONF_READ_FAST
76 #define M25P16_READ_FAST M25P16_CONF_READ_FAST
77 #else
78 #define M25P16_READ_FAST 1
79 #endif
80 /*---------------------------------------------------------------------------*/
81 /** \brief Device Identifier
82  *
83  * Holds the value of the device identifier, returned by the RDID instruction.
84  *
85  * After a correct RDID, this structure should hold the following values:
86  * man_id = 0x20, mem_type = 0x20, mem_size = 0x15, uid_len = 0x10.
87  *
88  * UID holds optional Customized Factory Data (CFD) content. The CFD bytes are
89  * read-only and can be programmed with customers data upon their request.
90  * If the customers do not make requests, the devices are shipped with all the
91  * CFD bytes programmed to 0x00.
92  */
93 struct m25p16_rdid {
94  uint8_t man_id; /** Manufacturer ID */
95  uint8_t mem_type; /** Memory Type */
96  uint8_t mem_size; /** Memory Size */
97  uint8_t uid_len; /** Unique ID length */
98  uint8_t uid[16]; /** Unique ID */
99 };
100 /*---------------------------------------------------------------------------*/
101 /**
102  * \brief Retrieve Block Protect Bits from the status register
103  *
104  * This macro returns the software block protect status on the device
105  * by reading the value of the BP bits ([5:3]) in the Status Register
106  */
107 #define M25P16_BP() (m25p16_rdsr() & M25P16_SR_BP)
108 /**
109  * \brief Check for Write in Progress
110  * \retval 1 Write in progress
111  * \retval 0 Write not in progress
112  *
113  * This macro checks if the device is currently in the middle of a write cycle
114  * by reading the value of the WIP bit (bit 0) in the Status Register
115  */
116 #define M25P16_WIP() (m25p16_rdsr() & M25P16_SR_WIP)
117 /**
118  * \brief Check for Write-Enable
119  * \retval 1 Write enabled
120  * \retval 0 Write disabled
121  *
122  * This macro checks if the device is ready to accept a write instruction
123  * by reading the value of the WEL bit (bit 1) in the Status Register
124  */
125 #define M25P16_WEL() (m25p16_rdsr() & M25P16_SR_WEL)
126 /*---------------------------------------------------------------------------*/
127 /**
128  * \brief Write Enable (WREN) instruction.
129  *
130  * Completing a WRDI, PP, SE, BE and WRSR
131  * resets the write enable latch bit, so this instruction should be used every
132  * time before trying to write.
133  */
134 void m25p16_wren();
135 
136 /**
137  * \brief Write Disable (WRDI) instruction
138  */
139 void m25p16_wrdi();
140 
141 /**
142  * \brief Read Identifier (RDID)instruction
143  *
144  * \param rdid Pointer to a struct which will hold the information returned
145  * by the RDID instruction
146  */
147 void m25p16_rdid(struct m25p16_rdid *rdid);
148 
149 /**
150  * \brief Read Status Register (RDSR) instruction
151  *
152  * \return Value of the status register
153  *
154  * Reads and returns the value of the status register on the Flash Chip
155  */
156 uint8_t m25p16_rdsr();
157 
158 /**
159  * \brief Write Status Register (WRSR) instruction
160  * \param val Value to be written to the status register
161  *
162  * This instruction does not afect bits 6, 5, 1 and 0 of the SR.
163  */
164 void m25p16_wrsr(uint8_t val);
165 
166 /**
167  * \brief Read Data Bytes (READ) instruction
168  * \param addr 3 byte array holding the read start address. MSB stored in
169  * addr[0] and LSB in addr[2]
170  * \param buff Pointer to a buffer to hold the read bytes.
171  * \param buff_len Number of bytes to read. buff must be long enough to hold
172  * buff_len bytes
173  *
174  * The bytes will be inverted after being read, so that a value of 0xFF (empty)
175  * in the flash will read as 0x00
176  */
177 void m25p16_read(uint8_t * addr, uint8_t * buff, uint8_t buff_len);
178 
179 /**
180  * \brief Program Page (PP) instruction
181  * \param addr 3 byte array holding the write start address. MSB stored in
182  * addr[0] and LSB in addr[2]
183  * \param buff Pointer to a buffer with the data to be written
184  * \param buff_len Number of bytes to write, Maximum 256 bytes.
185  *
186  * Write BUFF_LEN bytes stored in BUFF to flash, starting from location
187  * ADDR. BUFF_LEN may not exceed 256. ADDR should point to a 3 byte array,
188  * with the address MSB stored in position 0 and LSB in position 2
189  *
190  * If the start address + buff_len exceed page boundaries, the write will
191  * wrap to the start of the same page (the page at addr[2:1]).
192  *
193  * The bytes will be inverted before being written, so that a value of 0xFF
194  * will be written as 0x00 (and subsequently correctly read as 0xFF by READ)
195  *
196  * This function will set the WEL bit on the SR before attempting to write,
197  * so the calling function doesn't need to worry about this.
198  *
199  * This call is asynchronous. It will return before the write cycle has
200  * completed. Thus, user software must check the WIP bit Write In Progress)
201  * before sending further instructions. This can take up to 5 msecs (typical
202  * duration for a 256 byte write is 640 usec)
203  */
204 void m25p16_pp(uint8_t * addr, uint8_t * buff, uint8_t buff_len);
205 
206 /**
207  * \brief Sector Erase (SE) instruction
208  * \param s The number of the sector to be erased
209  *
210  * Delete the entire sector number s, by setting it's contents to all 0xFF
211  * (which will read as 0x00 by READ). The flash is broken down into 32 sectors,
212  * 64 KBytes each.
213  *
214  * This function will set the WEL bit on the SR before attempting to write,
215  * so the calling function doesn't need to worry about this.
216  *
217  * This call is asynchronous. It will return before the write cycle has
218  * completed. Thus, user software must check the WIP bit Write In Progress)
219  * before sending further instructions. This can take up to 3 secs (typical
220  * duration 600 msec)
221  */
222 void m25p16_se(uint8_t s); /* Sector Erase */
223 
224 
225 /**
226  * \brief Bulk Erase (SE) instruction
227  *
228  * Delete the entire memory, by setting it's contents to all 0xFF
229  * (which will read as 0x00 by READ).
230  *
231  * This function will set the WEL bit on the SR before attempting to write,
232  * so the calling function doesn't need to worry about this.
233  *
234  * This call is asynchronous. It will return before the write cycle has
235  * completed. Thus, user software must check the WIP bit Write In Progress)
236  * before sending further instructions.
237  *
238  * This instructions takes a very long time to complete and must be used with
239  * care. It can take up to 40 secs (yes, secs). A typical duration is 13 secs
240  */
241 void m25p16_be();
242 
243 /**
244  * \brief Deep Power Down (DP) instruction
245  *
246  * Puts the device into its lowers power consumption mode (This is not the same
247  * as the stand-by mode caused by de-selecting the device). While the device
248  * is in DP, it will accept no instruction except a RES (Release from DP).
249  *
250  * This call is asynchronous and will return as soon as the instruction
251  * sequence has been written but before the device has actually entered DP
252  *
253  * Dropping to DP takes 3usec and Resuming from DP takes at least 1.8usec, so
254  * this sequence should not be used when the sleep interval is estimated to be
255  * short (read as: don't DP then RES then DP repeatedly)
256  */
257 void m25p16_dp(); /* Deep Power down */
258 
259 /**
260  * \brief Release from Deep Power Down (RES) instruction
261  *
262  * Take the device out of the Deep Power Down mode and bring it to standby.
263  * Does not read the electronic signature.
264  *
265  * This call is synchronous. When it returns the device will be in standby
266  * mode.
267  *
268  * Dropping to DP takes 3usec and Resuming from DP takes at least 1.8usec, so
269  * this sequence should not be used when the sleep interval is estimated to be
270  * short (read as: don't DP then RES then DP repeatedly)
271  */
272 void m25p16_res();
273 
274 /**
275  * \brief Release from Deep Power Down (RES) and Read Electronic
276  * Signature instruction
277  *
278  * \return The value of the electronic signature. This is provided for backward
279  * compatibility and must always be 0x14
280  *
281  * Take the device out of the Deep Power Down mode and bring it to standby.
282  * Does not read the electronic signature.
283  *
284  * This call is synchronous. When it returns the device will be in standby
285  * mode.
286  *
287  * Dropping to DP takes 3usec and Resuming from DP takes at least 1.8usec, so
288  * this sequence should not be used when the sleep interval is estimated to be
289  * short (read as: don't DP then RES then DP repeatedly)
290  */
291 uint8_t m25p16_res_res();
292 
293 #endif /* M25P16_H_ */
uint8_t uid_len
Memory Size.
Definition: m25p16.h:97
uint8_t m25p16_rdsr()
Read Status Register (RDSR) instruction.
Definition: m25p16.c:167
void m25p16_pp(uint8_t *addr, uint8_t *buff, uint8_t buff_len)
Program Page (PP) instruction.
Definition: m25p16.c:224
uint8_t m25p16_res_res()
Release Deep Power Down.
Definition: m25p16.c:300
void m25p16_read(uint8_t *addr, uint8_t *buff, uint8_t buff_len)
Read Data Bytes (READ) instruction.
Definition: m25p16.c:193
void m25p16_wren()
Write Enable (WREN) instruction.
Definition: m25p16.c:131
Device Identifier.
Definition: m25p16.h:93
void m25p16_rdid(struct m25p16_rdid *rdid)
Read Identifier (RDID)instruction.
Definition: m25p16.c:149
uint8_t uid[16]
Unique ID length.
Definition: m25p16.h:98
void m25p16_wrsr(uint8_t val)
Write Status Register (WRSR) instruction.
Definition: m25p16.c:180
uint8_t mem_type
Manufacturer ID.
Definition: m25p16.h:95
void m25p16_dp()
Deep Power Down (DP) instruction.
Definition: m25p16.c:273
void m25p16_se(uint8_t s)
Sector Erase (SE) instruction.
Definition: m25p16.c:248
void m25p16_be()
Bulk Erase (SE) instruction.
Definition: m25p16.c:263
void m25p16_wrdi()
Write Disable (WRDI) instruction.
Definition: m25p16.c:141
uint8_t mem_size
Memory Type.
Definition: m25p16.h:96
void m25p16_res()
Release from Deep Power Down (RES) instruction.
Definition: m25p16.c:284