DWT_Type Struct Reference

Structure type to access the Data Watchpoint and Trace Register (DWT). More...

#include <cpu/arm/common/CMSIS/core_cm3.h>

Data Fields
__IO uint32_t	CTRL
__IO uint32_t	CYCCNT
__IO uint32_t	CPICNT
__IO uint32_t	EXCCNT
__IO uint32_t	SLEEPCNT
__IO uint32_t	LSUCNT
__IO uint32_t	FOLDCNT
__I uint32_t	PCSR
__IO uint32_t	COMP0
__IO uint32_t	MASK0
__IO uint32_t	FUNCTION0
__IO uint32_t	COMP1
__IO uint32_t	MASK1
__IO uint32_t	FUNCTION1
__IO uint32_t	COMP2
__IO uint32_t	MASK2
__IO uint32_t	FUNCTION2
__IO uint32_t	COMP3
__IO uint32_t	MASK3
__IO uint32_t	FUNCTION3

Detailed Description

Structure type to access the Data Watchpoint and Trace Register (DWT).

Definition at line 752 of file core_cm3.h.

Field Documentation

__IO uint32_t DWT_Type::COMP0

Offset: 0x020 (R/W) Comparator Register 0

Definition at line 762 of file core_cm3.h.

__IO uint32_t DWT_Type::COMP1

Offset: 0x030 (R/W) Comparator Register 1

Definition at line 766 of file core_cm3.h.

__IO uint32_t DWT_Type::COMP2

Offset: 0x040 (R/W) Comparator Register 2

Definition at line 770 of file core_cm3.h.

__IO uint32_t DWT_Type::COMP3

Offset: 0x050 (R/W) Comparator Register 3

Definition at line 774 of file core_cm3.h.

__IO uint32_t DWT_Type::CPICNT

Offset: 0x008 (R/W) CPI Count Register

Definition at line 756 of file core_cm3.h.

__IO uint32_t DWT_Type::CTRL

Offset: 0x000 (R/W) Control Register

Definition at line 754 of file core_cm3.h.

__IO uint32_t DWT_Type::CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

Definition at line 755 of file core_cm3.h.

__IO uint32_t DWT_Type::EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

Definition at line 757 of file core_cm3.h.

__IO uint32_t DWT_Type::FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

Definition at line 760 of file core_cm3.h.

__IO uint32_t DWT_Type::FUNCTION0

Offset: 0x028 (R/W) Function Register 0

Definition at line 764 of file core_cm3.h.

__IO uint32_t DWT_Type::FUNCTION1

Offset: 0x038 (R/W) Function Register 1

Definition at line 768 of file core_cm3.h.

__IO uint32_t DWT_Type::FUNCTION2

Offset: 0x048 (R/W) Function Register 2

Definition at line 772 of file core_cm3.h.

__IO uint32_t DWT_Type::FUNCTION3

Offset: 0x058 (R/W) Function Register 3

Definition at line 776 of file core_cm3.h.

__IO uint32_t DWT_Type::LSUCNT

Offset: 0x014 (R/W) LSU Count Register

Definition at line 759 of file core_cm3.h.

__IO uint32_t DWT_Type::MASK0

Offset: 0x024 (R/W) Mask Register 0

Definition at line 763 of file core_cm3.h.

__IO uint32_t DWT_Type::MASK1

Offset: 0x034 (R/W) Mask Register 1

Definition at line 767 of file core_cm3.h.

__IO uint32_t DWT_Type::MASK2

Offset: 0x044 (R/W) Mask Register 2

Definition at line 771 of file core_cm3.h.

__IO uint32_t DWT_Type::MASK3

Offset: 0x054 (R/W) Mask Register 3

Definition at line 775 of file core_cm3.h.

__I uint32_t DWT_Type::PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

Definition at line 761 of file core_cm3.h.

__IO uint32_t DWT_Type::SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register

Definition at line 758 of file core_cm3.h.