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core_cm3.h
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1 /**************************************************************************//**
2  * @file core_cm3.h
3  * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4  * @version V3.30
5  * @date 06. May 2014
6  *
7  * @note
8  *
9  ******************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM3_H_GENERIC
43 #define __CORE_CM3_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50  CMSIS violates the following MISRA-C:2004 rules:
51 
52  \li Required Rule 8.5, object/function definition in header file.<br>
53  Function definitions in header files are used to allow 'inlining'.
54 
55  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56  Unions are used for effective representation of core registers.
57 
58  \li Advisory Rule 19.7, Function-like macro defined.<br>
59  Function-like macros are used to allow more efficient code.
60  */
61 
62 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
66 /** \ingroup Cortex_M3
67  @{
68  */
69 
70 /* CMSIS CM3 definitions */
71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
74  __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75 
76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
77 
78 
79 #if defined ( __CC_ARM )
80  #define __ASM __asm /*!< asm keyword for ARM Compiler */
81  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm /*!< asm keyword for GNU Compiler */
86  #define __INLINE inline /*!< inline keyword for GNU Compiler */
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm /*!< asm keyword for IAR Compiler */
91  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ ) /* Cosmic */
104  #define __packed
105  #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
112 */
113 #define __FPU_USED 0
114 
115 #if defined ( __CC_ARM )
116  #if defined __TARGET_FPU_VFP
117  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118  #endif
119 
120 #elif defined ( __GNUC__ )
121  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
122  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123  #endif
124 
125 #elif defined ( __ICCARM__ )
126  #if defined __ARMVFP__
127  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128  #endif
129 
130 #elif defined ( __TMS470__ )
131  #if defined __TI__VFP_SUPPORT____
132  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
133  #endif
134 
135 #elif defined ( __TASKING__ )
136  #if defined __FPU_VFP__
137  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138  #endif
139 
140 #elif defined ( __CSMC__ ) /* Cosmic */
141  #if ( __CSMC__ & 0x400) // FPU present for parser
142  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
143  #endif
144 #endif
145 
146 #include <stdint.h> /* standard types definitions */
147 #include <core_cmInstr.h> /* Core Instruction Access */
148 #include <core_cmFunc.h> /* Core Function Access */
149 
150 #endif /* __CORE_CM3_H_GENERIC */
151 
152 #ifndef __CMSIS_GENERIC
153 
154 #ifndef __CORE_CM3_H_DEPENDANT
155 #define __CORE_CM3_H_DEPENDANT
156 
157 /* check device defines and use defaults */
158 #if defined __CHECK_DEVICE_DEFINES
159  #ifndef __CM3_REV
160  #define __CM3_REV 0x0200
161  #warning "__CM3_REV not defined in device header file; using default!"
162  #endif
163 
164  #ifndef __MPU_PRESENT
165  #define __MPU_PRESENT 0
166  #warning "__MPU_PRESENT not defined in device header file; using default!"
167  #endif
168 
169  #ifndef __NVIC_PRIO_BITS
170  #define __NVIC_PRIO_BITS 4
171  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
172  #endif
173 
174  #ifndef __Vendor_SysTickConfig
175  #define __Vendor_SysTickConfig 0
176  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
177  #endif
178 #endif
179 
180 /* IO definitions (access restrictions to peripheral registers) */
181 /**
182  \defgroup CMSIS_glob_defs CMSIS Global Defines
183 
184  <strong>IO Type Qualifiers</strong> are used
185  \li to specify the access to peripheral variables.
186  \li for automatic generation of peripheral register debug information.
187 */
188 #ifdef __cplusplus
189  #define __I volatile /*!< Defines 'read only' permissions */
190 #else
191  #define __I volatile const /*!< Defines 'read only' permissions */
192 #endif
193 #define __O volatile /*!< Defines 'write only' permissions */
194 #define __IO volatile /*!< Defines 'read / write' permissions */
195 
196 /*@} end of group Cortex_M3 */
197 
198 
199 
200 /*******************************************************************************
201  * Register Abstraction
202  Core Register contain:
203  - Core Register
204  - Core NVIC Register
205  - Core SCB Register
206  - Core SysTick Register
207  - Core Debug Register
208  - Core MPU Register
209  ******************************************************************************/
210 /** \defgroup CMSIS_core_register Defines and Type Definitions
211  \brief Type definitions and defines for Cortex-M processor based devices.
212 */
213 
214 /** \ingroup CMSIS_core_register
215  \defgroup CMSIS_CORE Status and Control Registers
216  \brief Core Register type definitions.
217  @{
218  */
219 
220 /** \brief Union type to access the Application Program Status Register (APSR).
221  */
222 typedef union
223 {
224  struct
225  {
226 #if (__CORTEX_M != 0x04)
227  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
228 #else
229  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
230  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
231  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
232 #endif
233  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
234  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
235  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
236  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
237  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
238  } b; /*!< Structure used for bit access */
239  uint32_t w; /*!< Type used for word access */
240 } APSR_Type;
241 
242 
243 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
244  */
245 typedef union
246 {
247  struct
248  {
249  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
250  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
251  } b; /*!< Structure used for bit access */
252  uint32_t w; /*!< Type used for word access */
253 } IPSR_Type;
254 
255 
256 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257  */
258 typedef union
259 {
260  struct
261  {
262  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263 #if (__CORTEX_M != 0x04)
264  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
265 #else
266  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
267  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
268  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
269 #endif
270  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
271  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
272  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
273  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
274  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
275  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
276  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
277  } b; /*!< Structure used for bit access */
278  uint32_t w; /*!< Type used for word access */
279 } xPSR_Type;
280 
281 
282 /** \brief Union type to access the Control Registers (CONTROL).
283  */
284 typedef union
285 {
286  struct
287  {
288  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
289  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
290  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
291  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
292  } b; /*!< Structure used for bit access */
293  uint32_t w; /*!< Type used for word access */
294 } CONTROL_Type;
295 
296 /*@} end of group CMSIS_CORE */
297 
298 
299 /** \ingroup CMSIS_core_register
300  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
301  \brief Type definitions for the NVIC Registers
302  @{
303  */
304 
305 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
306  */
307 typedef struct
308 {
309  __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
310  uint32_t RESERVED0[24];
311  __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
312  uint32_t RSERVED1[24];
313  __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
314  uint32_t RESERVED2[24];
315  __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
316  uint32_t RESERVED3[24];
317  __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
318  uint32_t RESERVED4[56];
319  __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
320  uint32_t RESERVED5[644];
321  __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
322 } NVIC_Type;
323 
324 /* Software Triggered Interrupt Register Definitions */
325 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
326 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
327 
328 /*@} end of group CMSIS_NVIC */
329 
330 
331 /** \ingroup CMSIS_core_register
332  \defgroup CMSIS_SCB System Control Block (SCB)
333  \brief Type definitions for the System Control Block Registers
334  @{
335  */
336 
337 /** \brief Structure type to access the System Control Block (SCB).
338  */
339 typedef struct
340 {
341  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
342  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
343  __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
344  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
345  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
346  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
347  __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
348  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
349  __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
350  __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
351  __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
352  __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
353  __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
354  __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
355  __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
356  __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
357  __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
358  __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
359  __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
360  uint32_t RESERVED0[5];
361  __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
362 } SCB_Type;
363 
364 /* SCB CPUID Register Definitions */
365 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
366 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
367 
368 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
369 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
370 
371 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
372 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
373 
374 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
375 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
376 
377 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
378 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
379 
380 /* SCB Interrupt Control State Register Definitions */
381 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
382 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
383 
384 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
385 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
386 
387 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
388 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
389 
390 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
391 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
392 
393 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
394 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
395 
396 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
397 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
398 
399 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
400 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
401 
402 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
403 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
404 
405 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
406 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
407 
408 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
409 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
410 
411 /* SCB Vector Table Offset Register Definitions */
412 #if (__CM3_REV < 0x0201) /* core r2p1 */
413 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
414 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
415 
416 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
417 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
418 #else
419 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
420 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
421 #endif
422 
423 /* SCB Application Interrupt and Reset Control Register Definitions */
424 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
425 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
426 
427 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
428 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
429 
430 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
431 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
432 
433 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
434 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
435 
436 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
437 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
438 
439 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
440 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
441 
442 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
443 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
444 
445 /* SCB System Control Register Definitions */
446 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
447 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
448 
449 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
450 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
451 
452 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
453 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
454 
455 /* SCB Configuration Control Register Definitions */
456 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
457 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
458 
459 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
460 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
461 
462 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
463 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
464 
465 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
466 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
467 
468 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
469 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
470 
471 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
472 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
473 
474 /* SCB System Handler Control and State Register Definitions */
475 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
476 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
477 
478 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
479 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
480 
481 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
482 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
483 
484 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
485 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
486 
487 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
488 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
489 
490 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
491 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
492 
493 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
494 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
495 
496 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
497 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
498 
499 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
500 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
501 
502 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
503 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
504 
505 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
506 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
507 
508 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
509 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
510 
511 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
512 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
513 
514 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
515 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
516 
517 /* SCB Configurable Fault Status Registers Definitions */
518 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
519 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
520 
521 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
522 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
523 
524 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
525 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
526 
527 /* SCB Hard Fault Status Registers Definitions */
528 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
529 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
530 
531 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
532 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
533 
534 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
535 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
536 
537 /* SCB Debug Fault Status Register Definitions */
538 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
539 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
540 
541 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
542 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
543 
544 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
545 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
546 
547 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
548 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
549 
550 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
551 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
552 
553 /*@} end of group CMSIS_SCB */
554 
555 
556 /** \ingroup CMSIS_core_register
557  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
558  \brief Type definitions for the System Control and ID Register not in the SCB
559  @{
560  */
561 
562 /** \brief Structure type to access the System Control and ID Register not in the SCB.
563  */
564 typedef struct
565 {
566  uint32_t RESERVED0[1];
567  __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
568 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
569  __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
570 #else
571  uint32_t RESERVED1[1];
572 #endif
573 } SCnSCB_Type;
574 
575 /* Interrupt Controller Type Register Definitions */
576 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
577 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
578 
579 /* Auxiliary Control Register Definitions */
580 
581 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
582 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
583 
584 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
585 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
586 
587 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
588 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
589 
590 /*@} end of group CMSIS_SCnotSCB */
591 
592 
593 /** \ingroup CMSIS_core_register
594  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
595  \brief Type definitions for the System Timer Registers.
596  @{
597  */
598 
599 /** \brief Structure type to access the System Timer (SysTick).
600  */
601 typedef struct
602 {
603  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
604  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
605  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
606  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
607 } SysTick_Type;
608 
609 /* SysTick Control / Status Register Definitions */
610 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
611 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
612 
613 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
614 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
615 
616 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
617 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
618 
619 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
620 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
621 
622 /* SysTick Reload Register Definitions */
623 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
624 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
625 
626 /* SysTick Current Register Definitions */
627 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
628 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
629 
630 /* SysTick Calibration Register Definitions */
631 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
632 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
633 
634 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
635 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
636 
637 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
638 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
639 
640 /*@} end of group CMSIS_SysTick */
641 
642 
643 /** \ingroup CMSIS_core_register
644  \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
645  \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
646  @{
647  */
648 
649 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
650  */
651 typedef struct
652 {
653  __O union
654  {
655  __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
656  __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
657  __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
658  } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
659  uint32_t RESERVED0[864];
660  __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
661  uint32_t RESERVED1[15];
662  __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
663  uint32_t RESERVED2[15];
664  __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
665  uint32_t RESERVED3[29];
666  __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
667  __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
668  __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
669  uint32_t RESERVED4[43];
670  __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
671  __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
672  uint32_t RESERVED5[6];
673  __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
674  __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
675  __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
676  __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
677  __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
678  __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
679  __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
680  __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
681  __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
682  __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
683  __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
684  __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
685 } ITM_Type;
686 
687 /* ITM Trace Privilege Register Definitions */
688 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
689 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
690 
691 /* ITM Trace Control Register Definitions */
692 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
693 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
694 
695 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
696 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
697 
698 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
699 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
700 
701 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
702 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
703 
704 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
705 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
706 
707 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
708 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
709 
710 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
711 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
712 
713 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
714 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
715 
716 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
717 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
718 
719 /* ITM Integration Write Register Definitions */
720 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
721 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
722 
723 /* ITM Integration Read Register Definitions */
724 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
725 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
726 
727 /* ITM Integration Mode Control Register Definitions */
728 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
729 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
730 
731 /* ITM Lock Status Register Definitions */
732 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
733 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
734 
735 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
736 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
737 
738 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
739 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
740 
741 /*@}*/ /* end of group CMSIS_ITM */
742 
743 
744 /** \ingroup CMSIS_core_register
745  \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
746  \brief Type definitions for the Data Watchpoint and Trace (DWT)
747  @{
748  */
749 
750 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
751  */
752 typedef struct
753 {
754  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
755  __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
756  __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
757  __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
758  __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
759  __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
760  __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
761  __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
762  __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
763  __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
764  __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
765  uint32_t RESERVED0[1];
766  __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
767  __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
768  __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
769  uint32_t RESERVED1[1];
770  __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
771  __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
772  __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
773  uint32_t RESERVED2[1];
774  __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
775  __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
776  __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
777 } DWT_Type;
778 
779 /* DWT Control Register Definitions */
780 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
781 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
782 
783 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
784 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
785 
786 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
787 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
788 
789 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
790 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
791 
792 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
793 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
794 
795 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
796 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
797 
798 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
799 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
800 
801 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
802 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
803 
804 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
805 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
806 
807 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
808 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
809 
810 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
811 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
812 
813 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
814 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
815 
816 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
817 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
818 
819 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
820 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
821 
822 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
823 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
824 
825 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
826 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
827 
828 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
829 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
830 
831 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
832 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
833 
834 /* DWT CPI Count Register Definitions */
835 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
836 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
837 
838 /* DWT Exception Overhead Count Register Definitions */
839 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
840 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
841 
842 /* DWT Sleep Count Register Definitions */
843 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
844 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
845 
846 /* DWT LSU Count Register Definitions */
847 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
848 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
849 
850 /* DWT Folded-instruction Count Register Definitions */
851 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
852 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
853 
854 /* DWT Comparator Mask Register Definitions */
855 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
856 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
857 
858 /* DWT Comparator Function Register Definitions */
859 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
860 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
861 
862 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
863 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
864 
865 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
866 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
867 
868 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
869 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
870 
871 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
872 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
873 
874 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
875 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
876 
877 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
878 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
879 
880 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
881 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
882 
883 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
884 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
885 
886 /*@}*/ /* end of group CMSIS_DWT */
887 
888 
889 /** \ingroup CMSIS_core_register
890  \defgroup CMSIS_TPI Trace Port Interface (TPI)
891  \brief Type definitions for the Trace Port Interface (TPI)
892  @{
893  */
894 
895 /** \brief Structure type to access the Trace Port Interface Register (TPI).
896  */
897 typedef struct
898 {
899  __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
900  __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
901  uint32_t RESERVED0[2];
902  __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
903  uint32_t RESERVED1[55];
904  __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
905  uint32_t RESERVED2[131];
906  __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
907  __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
908  __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
909  uint32_t RESERVED3[759];
910  __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
911  __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
912  __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
913  uint32_t RESERVED4[1];
914  __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
915  __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
916  __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
917  uint32_t RESERVED5[39];
918  __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
919  __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
920  uint32_t RESERVED7[8];
921  __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
922  __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
923 } TPI_Type;
924 
925 /* TPI Asynchronous Clock Prescaler Register Definitions */
926 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
927 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
928 
929 /* TPI Selected Pin Protocol Register Definitions */
930 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
931 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
932 
933 /* TPI Formatter and Flush Status Register Definitions */
934 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
935 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
936 
937 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
938 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
939 
940 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
941 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
942 
943 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
944 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
945 
946 /* TPI Formatter and Flush Control Register Definitions */
947 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
948 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
949 
950 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
951 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
952 
953 /* TPI TRIGGER Register Definitions */
954 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
955 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
956 
957 /* TPI Integration ETM Data Register Definitions (FIFO0) */
958 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
959 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
960 
961 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
962 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
963 
964 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
965 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
966 
967 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
968 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
969 
970 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
971 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
972 
973 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
974 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
975 
976 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
977 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
978 
979 /* TPI ITATBCTR2 Register Definitions */
980 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
981 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
982 
983 /* TPI Integration ITM Data Register Definitions (FIFO1) */
984 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
985 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
986 
987 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
988 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
989 
990 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
991 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
992 
993 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
994 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
995 
996 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
997 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
998 
999 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1000 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1001 
1002 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1003 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
1004 
1005 /* TPI ITATBCTR0 Register Definitions */
1006 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1007 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
1008 
1009 /* TPI Integration Mode Control Register Definitions */
1010 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1011 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
1012 
1013 /* TPI DEVID Register Definitions */
1014 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1015 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1016 
1017 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1018 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1019 
1020 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1021 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1022 
1023 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1024 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1025 
1026 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1027 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1028 
1029 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1030 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1031 
1032 /* TPI DEVTYPE Register Definitions */
1033 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1034 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1035 
1036 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1037 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1038 
1039 /*@}*/ /* end of group CMSIS_TPI */
1040 
1041 
1042 #if (__MPU_PRESENT == 1)
1043 /** \ingroup CMSIS_core_register
1044  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1045  \brief Type definitions for the Memory Protection Unit (MPU)
1046  @{
1047  */
1048 
1049 /** \brief Structure type to access the Memory Protection Unit (MPU).
1050  */
1051 typedef struct
1052 {
1053  __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1054  __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1055  __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1056  __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1057  __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1058  __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1059  __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1060  __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1061  __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1062  __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1063  __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1064 } MPU_Type;
1065 
1066 /* MPU Type Register */
1067 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1068 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1069 
1070 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1071 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1072 
1073 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1074 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1075 
1076 /* MPU Control Register */
1077 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1078 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1079 
1080 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1081 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1082 
1083 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1084 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1085 
1086 /* MPU Region Number Register */
1087 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1088 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1089 
1090 /* MPU Region Base Address Register */
1091 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1092 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1093 
1094 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1095 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1096 
1097 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1098 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1099 
1100 /* MPU Region Attribute and Size Register */
1101 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1102 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1103 
1104 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1105 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1106 
1107 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1108 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1109 
1110 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1111 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1112 
1113 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1114 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1115 
1116 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1117 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1118 
1119 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1120 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1121 
1122 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1123 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1124 
1125 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1126 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1127 
1128 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1129 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1130 
1131 /*@} end of group CMSIS_MPU */
1132 #endif
1133 
1134 
1135 /** \ingroup CMSIS_core_register
1136  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1137  \brief Type definitions for the Core Debug Registers
1138  @{
1139  */
1140 
1141 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1142  */
1143 typedef struct
1144 {
1145  __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1146  __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1147  __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1148  __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1149 } CoreDebug_Type;
1150 
1151 /* Debug Halting Control and Status Register */
1152 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1153 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1154 
1155 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1156 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1157 
1158 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1159 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1160 
1161 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1162 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1163 
1164 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1165 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1166 
1167 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1168 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1169 
1170 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1171 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1172 
1173 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1174 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1175 
1176 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1177 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1178 
1179 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1180 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1181 
1182 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1183 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1184 
1185 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1186 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1187 
1188 /* Debug Core Register Selector Register */
1189 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1190 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1191 
1192 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1193 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1194 
1195 /* Debug Exception and Monitor Control Register */
1196 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1197 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1198 
1199 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1200 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1201 
1202 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1203 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1204 
1205 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1206 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1207 
1208 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1209 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1210 
1211 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1212 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1213 
1214 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1215 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1216 
1217 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1218 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1219 
1220 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1221 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1222 
1223 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1224 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1225 
1226 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1227 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1228 
1229 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1230 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1231 
1232 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1233 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1234 
1235 /*@} end of group CMSIS_CoreDebug */
1236 
1237 
1238 /** \ingroup CMSIS_core_register
1239  \defgroup CMSIS_core_base Core Definitions
1240  \brief Definitions for base addresses, unions, and structures.
1241  @{
1242  */
1243 
1244 /* Memory mapping of Cortex-M3 Hardware */
1245 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1246 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1247 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1248 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1249 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1250 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1251 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1252 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1253 
1254 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1255 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1256 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1257 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1258 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1259 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1260 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1261 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1262 
1263 #if (__MPU_PRESENT == 1)
1264  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1265  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1266 #endif
1267 
1268 /*@} */
1269 
1270 
1271 
1272 /*******************************************************************************
1273  * Hardware Abstraction Layer
1274  Core Function Interface contains:
1275  - Core NVIC Functions
1276  - Core SysTick Functions
1277  - Core Debug Functions
1278  - Core Register Access Functions
1279  ******************************************************************************/
1280 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1281 */
1282 
1283 
1284 
1285 /* ########################## NVIC functions #################################### */
1286 /** \ingroup CMSIS_Core_FunctionInterface
1287  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1288  \brief Functions that manage interrupts and exceptions via the NVIC.
1289  @{
1290  */
1291 
1292 /** \brief Set Priority Grouping
1293 
1294  The function sets the priority grouping field using the required unlock sequence.
1295  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1296  Only values from 0..7 are used.
1297  In case of a conflict between priority grouping and available
1298  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1299 
1300  \param [in] PriorityGroup Priority grouping field.
1301  */
1302 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1303 {
1304  uint32_t reg_value;
1305  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1306 
1307  reg_value = SCB->AIRCR; /* read old register configuration */
1308  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1309  reg_value = (reg_value |
1310  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1311  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1312  SCB->AIRCR = reg_value;
1313 }
1314 
1315 
1316 /** \brief Get Priority Grouping
1317 
1318  The function reads the priority grouping field from the NVIC Interrupt Controller.
1319 
1320  \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1321  */
1322 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1323 {
1324  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1325 }
1326 
1327 
1328 /** \brief Enable External Interrupt
1329 
1330  The function enables a device-specific interrupt in the NVIC interrupt controller.
1331 
1332  \param [in] IRQn External interrupt number. Value cannot be negative.
1333  */
1334 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1335 {
1336  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1337 }
1338 
1339 
1340 /** \brief Disable External Interrupt
1341 
1342  The function disables a device-specific interrupt in the NVIC interrupt controller.
1343 
1344  \param [in] IRQn External interrupt number. Value cannot be negative.
1345  */
1346 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1347 {
1348  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1349 }
1350 
1351 
1352 /** \brief Get Pending Interrupt
1353 
1354  The function reads the pending register in the NVIC and returns the pending bit
1355  for the specified interrupt.
1356 
1357  \param [in] IRQn Interrupt number.
1358 
1359  \return 0 Interrupt status is not pending.
1360  \return 1 Interrupt status is pending.
1361  */
1362 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1363 {
1364  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1365 }
1366 
1367 
1368 /** \brief Set Pending Interrupt
1369 
1370  The function sets the pending bit of an external interrupt.
1371 
1372  \param [in] IRQn Interrupt number. Value cannot be negative.
1373  */
1374 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1375 {
1376  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1377 }
1378 
1379 
1380 /** \brief Clear Pending Interrupt
1381 
1382  The function clears the pending bit of an external interrupt.
1383 
1384  \param [in] IRQn External interrupt number. Value cannot be negative.
1385  */
1386 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1387 {
1388  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1389 }
1390 
1391 
1392 /** \brief Get Active Interrupt
1393 
1394  The function reads the active register in NVIC and returns the active bit.
1395 
1396  \param [in] IRQn Interrupt number.
1397 
1398  \return 0 Interrupt status is not active.
1399  \return 1 Interrupt status is active.
1400  */
1401 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1402 {
1403  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1404 }
1405 
1406 
1407 /** \brief Set Interrupt Priority
1408 
1409  The function sets the priority of an interrupt.
1410 
1411  \note The priority cannot be set for every core interrupt.
1412 
1413  \param [in] IRQn Interrupt number.
1414  \param [in] priority Priority to set.
1415  */
1416 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1417 {
1418  if(IRQn < 0) {
1419  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1420  else {
1421  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1422 }
1423 
1424 
1425 /** \brief Get Interrupt Priority
1426 
1427  The function reads the priority of an interrupt. The interrupt
1428  number can be positive to specify an external (device specific)
1429  interrupt, or negative to specify an internal (core) interrupt.
1430 
1431 
1432  \param [in] IRQn Interrupt number.
1433  \return Interrupt Priority. Value is aligned automatically to the implemented
1434  priority bits of the microcontroller.
1435  */
1436 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1437 {
1438 
1439  if(IRQn < 0) {
1440  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1441  else {
1442  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1443 }
1444 
1445 
1446 /** \brief Encode Priority
1447 
1448  The function encodes the priority for an interrupt with the given priority group,
1449  preemptive priority value, and subpriority value.
1450  In case of a conflict between priority grouping and available
1451  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1452 
1453  \param [in] PriorityGroup Used priority group.
1454  \param [in] PreemptPriority Preemptive priority value (starting from 0).
1455  \param [in] SubPriority Subpriority value (starting from 0).
1456  \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1457  */
1458 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1459 {
1460  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1461  uint32_t PreemptPriorityBits;
1462  uint32_t SubPriorityBits;
1463 
1464  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1465  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1466 
1467  return (
1468  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1469  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1470  );
1471 }
1472 
1473 
1474 /** \brief Decode Priority
1475 
1476  The function decodes an interrupt priority value with a given priority group to
1477  preemptive priority value and subpriority value.
1478  In case of a conflict between priority grouping and available
1479  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1480 
1481  \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1482  \param [in] PriorityGroup Used priority group.
1483  \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1484  \param [out] pSubPriority Subpriority value (starting from 0).
1485  */
1486 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1487 {
1488  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1489  uint32_t PreemptPriorityBits;
1490  uint32_t SubPriorityBits;
1491 
1492  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1493  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1494 
1495  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1496  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1497 }
1498 
1499 
1500 /** \brief System Reset
1501 
1502  The function initiates a system reset request to reset the MCU.
1503  */
1504 __STATIC_INLINE void NVIC_SystemReset(void)
1505 {
1506  __DSB(); /* Ensure all outstanding memory accesses included
1507  buffered write are completed before reset */
1508  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1509  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1510  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1511  __DSB(); /* Ensure completion of memory access */
1512  while(1); /* wait until reset */
1513 }
1514 
1515 /*@} end of CMSIS_Core_NVICFunctions */
1516 
1517 
1518 
1519 /* ################################## SysTick function ############################################ */
1520 /** \ingroup CMSIS_Core_FunctionInterface
1521  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1522  \brief Functions that configure the System.
1523  @{
1524  */
1525 
1526 #if (__Vendor_SysTickConfig == 0)
1527 
1528 /** \brief System Tick Configuration
1529 
1530  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1531  Counter is in free running mode to generate periodic interrupts.
1532 
1533  \param [in] ticks Number of ticks between two interrupts.
1534 
1535  \return 0 Function succeeded.
1536  \return 1 Function failed.
1537 
1538  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1539  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1540  must contain a vendor-specific implementation of this function.
1541 
1542  */
1543 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1544 {
1545  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1546 
1547  SysTick->LOAD = ticks - 1; /* set reload register */
1548  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1549  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1550  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1551  SysTick_CTRL_TICKINT_Msk |
1552  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1553  return (0); /* Function successful */
1554 }
1555 
1556 #endif
1557 
1558 /*@} end of CMSIS_Core_SysTickFunctions */
1559 
1560 
1561 
1562 /* ##################################### Debug In/Output function ########################################### */
1563 /** \ingroup CMSIS_Core_FunctionInterface
1564  \defgroup CMSIS_core_DebugFunctions ITM Functions
1565  \brief Functions that access the ITM debug interface.
1566  @{
1567  */
1568 
1569 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1570 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1571 
1572 
1573 /** \brief ITM Send Character
1574 
1575  The function transmits a character via the ITM channel 0, and
1576  \li Just returns when no debugger is connected that has booked the output.
1577  \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1578 
1579  \param [in] ch Character to transmit.
1580 
1581  \returns Character to transmit.
1582  */
1583 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1584 {
1585  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1586  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1587  {
1588  while (ITM->PORT[0].u32 == 0);
1589  ITM->PORT[0].u8 = (uint8_t) ch;
1590  }
1591  return (ch);
1592 }
1593 
1594 
1595 /** \brief ITM Receive Character
1596 
1597  The function inputs a character via the external variable \ref ITM_RxBuffer.
1598 
1599  \return Received character.
1600  \return -1 No character pending.
1601  */
1602 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1603  int32_t ch = -1; /* no character available */
1604 
1605  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1606  ch = ITM_RxBuffer;
1607  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1608  }
1609 
1610  return (ch);
1611 }
1612 
1613 
1614 /** \brief ITM Check Character
1615 
1616  The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1617 
1618  \return 0 No character available.
1619  \return 1 Character available.
1620  */
1621 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1622 
1623  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1624  return (0); /* no character available */
1625  } else {
1626  return (1); /* character available */
1627  }
1628 }
1629 
1630 /*@} end of CMSIS_core_DebugFunctions */
1631 
1632 #endif /* __CORE_CM3_H_DEPENDANT */
1633 
1634 #ifdef __cplusplus
1635 }
1636 #endif
1637 
1638 #endif /* __CMSIS_GENERIC */
SysTick
#define SysTick
Definition: core_cm3.h:1256
SCB
#define SCB
Definition: core_cm3.h:1255
DWT_Type::COMP3
__IO uint32_t COMP3
Definition: core_cm3.h:774
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:624
ITM_Type::PID0
__I uint32_t PID0
Definition: core_cm3.h:677
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm3.h:717
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm3.h:897
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:535
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm3.h:1570
MPU_Type
MPU - Register Layout Typedef.
Definition: MK60D10.h:5686
TPI_Type::ACPR
__IO uint32_t ACPR
Definition: core_cm3.h:902
SCnSCB_Type::ICTR
__I uint32_t ICTR
Definition: core_cm3.h:567
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:638
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:651
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
SCB_Type::VTOR
__IO uint32_t VTOR
Definition: core_cm3.h:343
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm3.h:433
SCB_Type::DFSR
__IO uint32_t DFSR
Definition: core_cm3.h:351
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm3.h:752
SCB_Type::BFAR
__IO uint32_t BFAR
Definition: core_cm3.h:353
TPI_Type::TRIGGER
__I uint32_t TRIGGER
Definition: core_cm3.h:910
SCB_Type::AFSR
__IO uint32_t AFSR
Definition: core_cm3.h:354
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm3.h:624
ITM_Type::IWR
__O uint32_t IWR
Definition: core_cm3.h:666
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:676
__O
#define __O
Definition: core_cm3.h:193
SCB_Type::HFSR
__IO uint32_t HFSR
Definition: core_cm3.h:350
ITM_Type::PID6
__I uint32_t PID6
Definition: core_cm3.h:675
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:587
TPI_Type::DEVTYPE
__I uint32_t DEVTYPE
Definition: core_cm3.h:922
DWT_Type::FOLDCNT
__IO uint32_t FOLDCNT
Definition: core_cm3.h:760
DWT_Type::FUNCTION2
__IO uint32_t FUNCTION2
Definition: core_cm3.h:772
SCB_Type::CPACR
__IO uint32_t CPACR
Definition: core_cm3.h:361
DWT_Type::FUNCTION0
__IO uint32_t FUNCTION0
Definition: core_cm3.h:764
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:547
SCB_Type::MMFAR
__IO uint32_t MMFAR
Definition: core_cm3.h:352
TPI_Type::DEVID
__I uint32_t DEVID
Definition: core_cm3.h:921
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:300
DWT_Type::COMP2
__IO uint32_t COMP2
Definition: core_cm3.h:770
ITM_Type::IRR
__I uint32_t IRR
Definition: core_cm3.h:667
DWT_Type::CPICNT
__IO uint32_t CPICNT
Definition: core_cm3.h:756
DWT_Type::SLEEPCNT
__IO uint32_t SLEEPCNT
Definition: core_cm3.h:758
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:563
DWT_Type::MASK0
__IO uint32_t MASK0
Definition: core_cm3.h:763
TPI_Type::FIFO1
__I uint32_t FIFO1
Definition: core_cm3.h:915
TPI_Type::SSPSR
__IO uint32_t SSPSR
Definition: core_cm3.h:899
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:1143
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:430
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm3.h:1458
ITM_Type::u8
__O uint8_t u8
Definition: core_cm3.h:655
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm3.h:1602
ITM_Type::u32
__O uint32_t u32
Definition: core_cm3.h:657
__I
#define __I
Definition: core_cm3.h:191
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:564
SCB_Type::ADR
__I uint32_t ADR
Definition: core_cm3.h:357
ITM_Type::CID1
__I uint32_t CID1
Definition: core_cm3.h:682
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:575
TPI_Type::CLAIMSET
__IO uint32_t CLAIMSET
Definition: core_cm3.h:918
TPI_Type::FSCR
__I uint32_t FSCR
Definition: core_cm3.h:908
DWT_Type::PCSR
__I uint32_t PCSR
Definition: core_cm3.h:761
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm3.h:617
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:238
ITM_Type::LSR
__I uint32_t LSR
Definition: core_cm3.h:671
ITM_Type::CID2
__I uint32_t CID2
Definition: core_cm3.h:683
TPI_Type::CLAIMCLR
__IO uint32_t CLAIMCLR
Definition: core_cm3.h:919
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_cm3.h:1583
TPI_Type::CSPSR
__IO uint32_t CSPSR
Definition: core_cm3.h:900
ITM_Type::u16
__O uint16_t u16
Definition: core_cm3.h:656
DWT_Type::MASK1
__IO uint32_t MASK1
Definition: core_cm3.h:767
ITM
#define ITM
Definition: core_cm3.h:1258
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: ADuCRF101.h:135
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm3.h:1401
TPI_Type::ITCTRL
__IO uint32_t ITCTRL
Definition: core_cm3.h:916
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm3.h:1302
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:251
ITM_Type::IMCR
__IO uint32_t IMCR
Definition: core_cm3.h:668
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm3.h:614
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
DWT_Type::COMP0
__IO uint32_t COMP0
Definition: core_cm3.h:762
CoreDebug_Type::DEMCR
__IO uint32_t DEMCR
Definition: core_cm3.h:1148
IRQn_Type
IRQn_Type
Definition: ADuCRF101.h:69
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Definition: core_cm3.h:1486
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm3.h:437
TPI_Type::FIFO0
__I uint32_t FIFO0
Definition: core_cm3.h:911
DWT_Type::EXCCNT
__IO uint32_t EXCCNT
Definition: core_cm3.h:757
DWT_Type::FUNCTION1
__IO uint32_t FUNCTION1
Definition: core_cm3.h:768
ITM_Type::PID7
__I uint32_t PID7
Definition: core_cm3.h:676
ITM_Type::PID3
__I uint32_t PID3
Definition: core_cm3.h:680
ITM_Type::TPR
__IO uint32_t TPR
Definition: core_cm3.h:662
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm3.h:425
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:277
DWT_Type::MASK3
__IO uint32_t MASK3
Definition: core_cm3.h:775
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm3.h:1621
CoreDebug_Type::DCRSR
__O uint32_t DCRSR
Definition: core_cm3.h:1146
ITM_Type::CID3
__I uint32_t CID3
Definition: core_cm3.h:684
ITM_Type::LAR
__O uint32_t LAR
Definition: core_cm3.h:670
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:602
DWT_Type::CYCCNT
__IO uint32_t CYCCNT
Definition: core_cm3.h:755
DWT_Type::LSUCNT
__IO uint32_t LSUCNT
Definition: core_cm3.h:759
IRQn
IRQn
Interrupt Number Definitions.
Definition: MK60D10.h:83
TPI_Type::ITATBCTR2
__I uint32_t ITATBCTR2
Definition: core_cm3.h:912
DWT_Type::COMP1
__IO uint32_t COMP1
Definition: core_cm3.h:766
SCB_Type::CFSR
__IO uint32_t CFSR
Definition: core_cm3.h:349
ITM_Type::TCR
__IO uint32_t TCR
Definition: core_cm3.h:664
DWT_Type::CTRL
__IO uint32_t CTRL
Definition: core_cm3.h:754
CoreDebug_Type::DCRDR
__IO uint32_t DCRDR
Definition: core_cm3.h:1147
ITM_Type::PID2
__I uint32_t PID2
Definition: core_cm3.h:679
TPI_Type::ITATBCTR0
__I uint32_t ITATBCTR0
Definition: core_cm3.h:914
ITM_Type::PID5
__I uint32_t PID5
Definition: core_cm3.h:674
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm3.h:424
TPI_Type::FFSR
__I uint32_t FFSR
Definition: core_cm3.h:906
ITM_Type::CID0
__I uint32_t CID0
Definition: core_cm3.h:681
NVIC
#define NVIC
Definition: core_cm3.h:1257
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm3.h:434
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm3.h:620
DWT_Type::MASK2
__IO uint32_t MASK2
Definition: core_cm3.h:771
SCB_Type::DFR
__I uint32_t DFR
Definition: core_cm3.h:356
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm3.h:1322
TPI_Type::FFCR
__IO uint32_t FFCR
Definition: core_cm3.h:907
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:215
ITM_Type::TER
__IO uint32_t TER
Definition: core_cm3.h:660
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:325
ITM_Type::PID1
__I uint32_t PID1
Definition: core_cm3.h:678
ITM_Type::PID4
__I uint32_t PID4
Definition: core_cm3.h:673
TPI_Type::SPPR
__IO uint32_t SPPR
Definition: core_cm3.h:904
DWT_Type::FUNCTION3
__IO uint32_t FUNCTION3
Definition: core_cm3.h:776
__IO
#define __IO
Definition: core_cm3.h:194
CoreDebug_Type::DHCSR
__IO uint32_t DHCSR
Definition: core_cm3.h:1145
NVIC_Type::STIR
__O uint32_t STIR
Definition: core_cm3.h:321
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