I2S_Type Struct Reference

I2S - Register Layout Typedef. More...

#include <cpu/arm/k60/include/MK60D10.h>

Data Fields
__IO uint32_t	TCSR
	SAI Transmit Control Register, offset: 0x0.
__IO uint32_t	TCR1
	SAI Transmit Configuration 1 Register, offset: 0x4.
__IO uint32_t	TCR2
	SAI Transmit Configuration 2 Register, offset: 0x8.
__IO uint32_t	TCR3
	SAI Transmit Configuration 3 Register, offset: 0xC.
__IO uint32_t	TCR4
	SAI Transmit Configuration 4 Register, offset: 0x10.
__IO uint32_t	TCR5
	SAI Transmit Configuration 5 Register, offset: 0x14.
__O uint32_t	TDR [2]
	SAI Transmit Data Register, array offset: 0x20, array step: 0x4.
__I uint32_t	TFR [2]
	SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4.
__IO uint32_t	TMR
	SAI Transmit Mask Register, offset: 0x60.
__IO uint32_t	RCSR
	SAI Receive Control Register, offset: 0x80.
__IO uint32_t	RCR1
	SAI Receive Configuration 1 Register, offset: 0x84.
__IO uint32_t	RCR2
	SAI Receive Configuration 2 Register, offset: 0x88.
__IO uint32_t	RCR3
	SAI Receive Configuration 3 Register, offset: 0x8C.
__IO uint32_t	RCR4
	SAI Receive Configuration 4 Register, offset: 0x90.
__IO uint32_t	RCR5
	SAI Receive Configuration 5 Register, offset: 0x94.
__I uint32_t	RDR [2]
	SAI Receive Data Register, array offset: 0xA0, array step: 0x4.
__I uint32_t	RFR [2]
	SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4.
__IO uint32_t	RMR
	SAI Receive Mask Register, offset: 0xE0.
__IO uint32_t	MCR
	SAI MCLK Control Register, offset: 0x100.
__IO uint32_t	MDR
	SAI MCLK Divide Register, offset: 0x104.
__IO uint32_t	TX0
	I2S Transmit Data Registers 0, offset: 0x0.
__IO uint32_t	TX1
	I2S Transmit Data Registers 1, offset: 0x4.
__IO uint32_t	RX0
	I2S Receive Data Registers 0, offset: 0x8.
__IO uint32_t	RX1
	I2S Receive Data Registers 1, offset: 0xC.
__IO uint32_t	CR
	I2S Control Register, offset: 0x10.
__IO uint32_t	ISR
	I2S Interrupt Status Register, offset: 0x14.
__IO uint32_t	IER
	I2S Interrupt Enable Register, offset: 0x18.
__IO uint32_t	TCR
	I2S Transmit Configuration Register, offset: 0x1C.
__IO uint32_t	RCR
	I2S Receive Configuration Register, offset: 0x20.
__IO uint32_t	TCCR
	I2S Transmit Clock Control Registers, offset: 0x24.
__IO uint32_t	RCCR
	I2S Receive Clock Control Registers, offset: 0x28.
__IO uint32_t	FCSR
	I2S FIFO Control/Status Register, offset: 0x2C.
__IO uint32_t	ACNT
	I2S AC97 Control Register, offset: 0x38.
__IO uint32_t	ACADD
	I2S AC97 Command Address Register, offset: 0x3C.
__IO uint32_t	ACDAT
	I2S AC97 Command Data Register, offset: 0x40.
__IO uint32_t	ATAG
	I2S AC97 Tag Register, offset: 0x44.
__IO uint32_t	TMSK
	I2S Transmit Time Slot Mask Register, offset: 0x48.
__IO uint32_t	RMSK
	I2S Receive Time Slot Mask Register, offset: 0x4C.
__I uint32_t	ACCST
	I2S AC97 Channel Status Register, offset: 0x50.
__IO uint32_t	ACCEN
	I2S AC97 Channel Enable Register, offset: 0x54.
__IO uint32_t	ACCDIS
	I2S AC97 Channel Disable Register, offset: 0x58.

Detailed Description

I2S - Register Layout Typedef.

Definition at line 4849 of file MK60D10.h.