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MK60D10.h
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1 /*
2 ** ###################################################################
3 ** Processors: MK60DN512VLL10
4 ** MK60DX256VLL10
5 ** MK60DN256VLL10
6 ** MK60DN512VLQ10
7 ** MK60DN256VLQ10
8 ** MK60DX256VLQ10
9 ** MK60DN512VMC10
10 ** MK60DN256VMC10
11 ** MK60DX256VMC10
12 ** MK60DN512VMD10
13 ** MK60DX256VMD10
14 ** MK60DN256VMD10
15 **
16 ** Compilers: ARM Compiler
17 ** Freescale C/C++ for Embedded ARM
18 ** GNU C Compiler
19 ** IAR ANSI C/C++ Compiler for ARM
20 **
21 ** Reference manual: K60P144M100SF2V2RM Rev. 2, Jun 2012
22 ** Version: rev. 1.3, 2012-10-29
23 **
24 ** Abstract:
25 ** CMSIS Peripheral Access Layer for MK60D10
26 **
27 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
28 **
29 ** http: www.freescale.com
30 ** mail: support@freescale.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2012-01-03)
34 ** Initial version
35 ** - rev. 1.1 (2012-04-13)
36 ** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
37 ** Added new #define symbols <peripheralType>_BASE_PTRS.
38 ** - rev. 1.2 (2012-07-09)
39 ** UART0 - Fixed register definition - CEA709.1-B (LON) registers added.
40 ** - rev. 1.3 (2012-10-29)
41 ** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012
42 **
43 ** ###################################################################
44 */
45 
46 /**
47  * @file MK60D10.h
48  * @version 1.3
49  * @date 2012-10-29
50  * @brief CMSIS Peripheral Access Layer for MK60D10
51  *
52  * CMSIS Peripheral Access Layer for MK60D10
53  */
54 
55 #if !defined(MK60D10_H_)
56 #define MK60D10_H_ /**< Symbol preventing repeated inclusion */
57 
58 /** Memory map major version (memory maps with equal major version number are
59  * compatible) */
60 #define MCU_MEM_MAP_VERSION 0x0100u
61 /** Memory map minor version */
62 #define MCU_MEM_MAP_VERSION_MINOR 0x0003u
63 
64 /**
65  * @brief Macro to access a single bit of a peripheral register (bit band region
66  * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
67  * @param Reg Register to access.
68  * @param Bit Bit number to access.
69  * @return Value of the targeted bit in the bit band region.
70  */
71 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
72 
73 /* ----------------------------------------------------------------------------
74  -- Interrupt vector numbers
75  ---------------------------------------------------------------------------- */
76 
77 /**
78  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
79  * @{
80  */
81 
82 /** Interrupt Number Definitions */
83 typedef enum IRQn {
84  /* Core interrupts */
85  NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
86  HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
87  MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
88  BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
89  UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
90  SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
91  DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
92  PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
93  SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
94 
95  /* Device specific interrupts */
96  DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
97  DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
98  DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
99  DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
100  DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
101  DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
102  DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
103  DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
104  DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
105  DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
106  DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
107  DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
108  DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
109  DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
110  DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
111  DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
112  DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
113  MCM_IRQn = 17, /**< Normal Interrupt */
114  FTFL_IRQn = 18, /**< FTFL Interrupt */
115  Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
116  LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
117  LLW_IRQn = 21, /**< Low Leakage Wakeup */
118  Watchdog_IRQn = 22, /**< WDOG Interrupt */
119  RNG_IRQn = 23, /**< RNGB Interrupt */
120  I2C0_IRQn = 24, /**< I2C0 interrupt */
121  I2C1_IRQn = 25, /**< I2C1 interrupt */
122  SPI0_IRQn = 26, /**< SPI0 Interrupt */
123  SPI1_IRQn = 27, /**< SPI1 Interrupt */
124  SPI2_IRQn = 28, /**< SPI2 Interrupt */
125  CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */
126  CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */
127  CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */
128  CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */
129  CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */
130  CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */
131  I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */
132  I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */
133  CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd message buffers interrupt */
134  CAN1_Bus_Off_IRQn = 38, /**< CAN1 bus off interrupt */
135  CAN1_Error_IRQn = 39, /**< CAN1 error interrupt */
136  CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx warning interrupt */
137  CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx warning interrupt */
138  CAN1_Wake_Up_IRQn = 42, /**< CAN1 wake up interrupt */
139  Reserved59_IRQn = 43, /**< Reserved interrupt 59 */
140  UART0_LON_IRQn = 44, /**< UART0 LON interrupt */
141  UART0_RX_TX_IRQn = 45, /**< UART0 Receive/Transmit interrupt */
142  UART0_ERR_IRQn = 46, /**< UART0 Error interrupt */
143  UART1_RX_TX_IRQn = 47, /**< UART1 Receive/Transmit interrupt */
144  UART1_ERR_IRQn = 48, /**< UART1 Error interrupt */
145  UART2_RX_TX_IRQn = 49, /**< UART2 Receive/Transmit interrupt */
146  UART2_ERR_IRQn = 50, /**< UART2 Error interrupt */
147  UART3_RX_TX_IRQn = 51, /**< UART3 Receive/Transmit interrupt */
148  UART3_ERR_IRQn = 52, /**< UART3 Error interrupt */
149  UART4_RX_TX_IRQn = 53, /**< UART4 Receive/Transmit interrupt */
150  UART4_ERR_IRQn = 54, /**< UART4 Error interrupt */
151  UART5_RX_TX_IRQn = 55, /**< UART5 Receive/Transmit interrupt */
152  UART5_ERR_IRQn = 56, /**< UART5 Error interrupt */
153  ADC0_IRQn = 57, /**< ADC0 interrupt */
154  ADC1_IRQn = 58, /**< ADC1 interrupt */
155  CMP0_IRQn = 59, /**< CMP0 interrupt */
156  CMP1_IRQn = 60, /**< CMP1 interrupt */
157  CMP2_IRQn = 61, /**< CMP2 interrupt */
158  FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
159  FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
160  FTM2_IRQn = 64, /**< FTM2 fault, overflow and channels interrupt */
161  CMT_IRQn = 65, /**< CMT interrupt */
162  RTC_IRQn = 66, /**< RTC interrupt */
163  RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */
164  PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
165  PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
166  PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
167  PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
168  PDB0_IRQn = 72, /**< PDB0 Interrupt */
169  USB0_IRQn = 73, /**< USB0 interrupt */
170  USBDCD_IRQn = 74, /**< USBDCD Interrupt */
171  ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
172  ENET_Transmit_IRQn = 76, /**< Ethernet MAC Transmit Interrupt */
173  ENET_Receive_IRQn = 77, /**< Ethernet MAC Receive Interrupt */
174  ENET_Error_IRQn = 78, /**< Ethernet MAC Error and miscelaneous Interrupt */
175  Reserved95_IRQn = 79, /**< Reserved interrupt 95 */
176  SDHC_IRQn = 80, /**< SDHC Interrupt */
177  DAC0_IRQn = 81, /**< DAC0 interrupt */
178  DAC1_IRQn = 82, /**< DAC1 interrupt */
179  TSI0_IRQn = 83, /**< TSI0 Interrupt */
180  MCG_IRQn = 84, /**< MCG Interrupt */
181  LPTimer_IRQn = 85, /**< LPTimer interrupt */
182  Reserved102_IRQn = 86, /**< Reserved interrupt 102 */
183  PORTA_IRQn = 87, /**< Port A interrupt */
184  PORTB_IRQn = 88, /**< Port B interrupt */
185  PORTC_IRQn = 89, /**< Port C interrupt */
186  PORTD_IRQn = 90, /**< Port D interrupt */
187  PORTE_IRQn = 91, /**< Port E interrupt */
188  Reserved108_IRQn = 92, /**< Reserved interrupt 108 */
189  Reserved109_IRQn = 93, /**< Reserved interrupt 109 */
190  SWI_IRQn = 94, /**< Software interrupt */
191  Reserved111_IRQn = 95, /**< Reserved interrupt 111 */
192  Reserved112_IRQn = 96, /**< Reserved interrupt 112 */
193  Reserved113_IRQn = 97, /**< Reserved interrupt 113 */
194  Reserved114_IRQn = 98, /**< Reserved interrupt 114 */
195  Reserved115_IRQn = 99, /**< Reserved interrupt 115 */
196  Reserved116_IRQn = 100, /**< Reserved interrupt 116 */
197  Reserved117_IRQn = 101, /**< Reserved interrupt 117 */
198  Reserved118_IRQn = 102, /**< Reserved interrupt 118 */
199  Reserved119_IRQn = 103 /**< Reserved interrupt 119 */
200 } IRQn_Type;
201 
202 /**
203  * @}
204  */ /* end of group Interrupt_vector_numbers */
205 
206 
207 /* ----------------------------------------------------------------------------
208  -- Cortex M4 Core Configuration
209  ---------------------------------------------------------------------------- */
210 
211 /**
212  * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
213  * @{
214  */
215 
216 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
217 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
218 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
219 
220 #include "core_cm4.h" /* Core Peripheral Access Layer */
221 #include "system_MK60D10.h" /* Device specific configuration file */
222 
223 /**
224  * @}
225  */ /* end of group Cortex_Core_Configuration */
226 
227 
228 /* ----------------------------------------------------------------------------
229  -- Device Peripheral Access Layer
230  ---------------------------------------------------------------------------- */
231 
232 /**
233  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
234  * @{
235  */
236 
237 
238 /*
239 ** Start of section using anonymous unions
240 */
241 
242 #if defined(__ARMCC_VERSION)
243  #pragma push
244  #pragma anon_unions
245 #elif defined(__CWCC__)
246  #pragma push
247  #pragma cpp_extensions on
248 #elif defined(__GNUC__)
249  /* anonymous unions are enabled by default */
250 #elif defined(__IAR_SYSTEMS_ICC__)
251  #pragma language=extended
252 #else
253  #error Not supported compiler type
254 #endif
255 
256 /* ----------------------------------------------------------------------------
257  -- ADC Peripheral Access Layer
258  ---------------------------------------------------------------------------- */
259 
260 /**
261  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
262  * @{
263  */
264 
265 /** ADC - Register Layout Typedef */
266 typedef struct {
267  __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
268  __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
269  __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
270  __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
271  __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
272  __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
273  __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
274  __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
275  __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
276  __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
277  __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
278  __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
279  __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
280  __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
281  __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
282  __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
283  __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
284  __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
285  __IO uint32_t PGA; /**< ADC PGA Register, offset: 0x50 */
286  __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
287  __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
288  __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
289  __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
290  __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
291  __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
292  __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
293 } ADC_Type;
294 
295 /* ----------------------------------------------------------------------------
296  -- ADC Register Masks
297  ---------------------------------------------------------------------------- */
298 
299 /**
300  * @addtogroup ADC_Register_Masks ADC Register Masks
301  * @{
302  */
303 
304 /* SC1 Bit Fields */
305 #define ADC_SC1_ADCH_MASK 0x1Fu
306 #define ADC_SC1_ADCH_SHIFT 0
307 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
308 #define ADC_SC1_DIFF_MASK 0x20u
309 #define ADC_SC1_DIFF_SHIFT 5
310 #define ADC_SC1_AIEN_MASK 0x40u
311 #define ADC_SC1_AIEN_SHIFT 6
312 #define ADC_SC1_COCO_MASK 0x80u
313 #define ADC_SC1_COCO_SHIFT 7
314 /* CFG1 Bit Fields */
315 #define ADC_CFG1_ADICLK_MASK 0x3u
316 #define ADC_CFG1_ADICLK_SHIFT 0
317 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
318 #define ADC_CFG1_MODE_MASK 0xCu
319 #define ADC_CFG1_MODE_SHIFT 2
320 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
321 #define ADC_CFG1_ADLSMP_MASK 0x10u
322 #define ADC_CFG1_ADLSMP_SHIFT 4
323 #define ADC_CFG1_ADIV_MASK 0x60u
324 #define ADC_CFG1_ADIV_SHIFT 5
325 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
326 #define ADC_CFG1_ADLPC_MASK 0x80u
327 #define ADC_CFG1_ADLPC_SHIFT 7
328 /* CFG2 Bit Fields */
329 #define ADC_CFG2_ADLSTS_MASK 0x3u
330 #define ADC_CFG2_ADLSTS_SHIFT 0
331 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
332 #define ADC_CFG2_ADHSC_MASK 0x4u
333 #define ADC_CFG2_ADHSC_SHIFT 2
334 #define ADC_CFG2_ADACKEN_MASK 0x8u
335 #define ADC_CFG2_ADACKEN_SHIFT 3
336 #define ADC_CFG2_MUXSEL_MASK 0x10u
337 #define ADC_CFG2_MUXSEL_SHIFT 4
338 /* R Bit Fields */
339 #define ADC_R_D_MASK 0xFFFFu
340 #define ADC_R_D_SHIFT 0
341 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
342 /* CV1 Bit Fields */
343 #define ADC_CV1_CV_MASK 0xFFFFu
344 #define ADC_CV1_CV_SHIFT 0
345 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
346 /* CV2 Bit Fields */
347 #define ADC_CV2_CV_MASK 0xFFFFu
348 #define ADC_CV2_CV_SHIFT 0
349 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
350 /* SC2 Bit Fields */
351 #define ADC_SC2_REFSEL_MASK 0x3u
352 #define ADC_SC2_REFSEL_SHIFT 0
353 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
354 #define ADC_SC2_DMAEN_MASK 0x4u
355 #define ADC_SC2_DMAEN_SHIFT 2
356 #define ADC_SC2_ACREN_MASK 0x8u
357 #define ADC_SC2_ACREN_SHIFT 3
358 #define ADC_SC2_ACFGT_MASK 0x10u
359 #define ADC_SC2_ACFGT_SHIFT 4
360 #define ADC_SC2_ACFE_MASK 0x20u
361 #define ADC_SC2_ACFE_SHIFT 5
362 #define ADC_SC2_ADTRG_MASK 0x40u
363 #define ADC_SC2_ADTRG_SHIFT 6
364 #define ADC_SC2_ADACT_MASK 0x80u
365 #define ADC_SC2_ADACT_SHIFT 7
366 /* SC3 Bit Fields */
367 #define ADC_SC3_AVGS_MASK 0x3u
368 #define ADC_SC3_AVGS_SHIFT 0
369 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
370 #define ADC_SC3_AVGE_MASK 0x4u
371 #define ADC_SC3_AVGE_SHIFT 2
372 #define ADC_SC3_ADCO_MASK 0x8u
373 #define ADC_SC3_ADCO_SHIFT 3
374 #define ADC_SC3_CALF_MASK 0x40u
375 #define ADC_SC3_CALF_SHIFT 6
376 #define ADC_SC3_CAL_MASK 0x80u
377 #define ADC_SC3_CAL_SHIFT 7
378 /* OFS Bit Fields */
379 #define ADC_OFS_OFS_MASK 0xFFFFu
380 #define ADC_OFS_OFS_SHIFT 0
381 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
382 /* PG Bit Fields */
383 #define ADC_PG_PG_MASK 0xFFFFu
384 #define ADC_PG_PG_SHIFT 0
385 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
386 /* MG Bit Fields */
387 #define ADC_MG_MG_MASK 0xFFFFu
388 #define ADC_MG_MG_SHIFT 0
389 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
390 /* CLPD Bit Fields */
391 #define ADC_CLPD_CLPD_MASK 0x3Fu
392 #define ADC_CLPD_CLPD_SHIFT 0
393 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
394 /* CLPS Bit Fields */
395 #define ADC_CLPS_CLPS_MASK 0x3Fu
396 #define ADC_CLPS_CLPS_SHIFT 0
397 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
398 /* CLP4 Bit Fields */
399 #define ADC_CLP4_CLP4_MASK 0x3FFu
400 #define ADC_CLP4_CLP4_SHIFT 0
401 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
402 /* CLP3 Bit Fields */
403 #define ADC_CLP3_CLP3_MASK 0x1FFu
404 #define ADC_CLP3_CLP3_SHIFT 0
405 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
406 /* CLP2 Bit Fields */
407 #define ADC_CLP2_CLP2_MASK 0xFFu
408 #define ADC_CLP2_CLP2_SHIFT 0
409 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
410 /* CLP1 Bit Fields */
411 #define ADC_CLP1_CLP1_MASK 0x7Fu
412 #define ADC_CLP1_CLP1_SHIFT 0
413 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
414 /* CLP0 Bit Fields */
415 #define ADC_CLP0_CLP0_MASK 0x3Fu
416 #define ADC_CLP0_CLP0_SHIFT 0
417 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
418 /* PGA Bit Fields */
419 #define ADC_PGA_PGAG_MASK 0xF0000u
420 #define ADC_PGA_PGAG_SHIFT 16
421 #define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
422 #define ADC_PGA_PGALPb_MASK 0x100000u
423 #define ADC_PGA_PGALPb_SHIFT 20
424 #define ADC_PGA_PGAEN_MASK 0x800000u
425 #define ADC_PGA_PGAEN_SHIFT 23
426 /* CLMD Bit Fields */
427 #define ADC_CLMD_CLMD_MASK 0x3Fu
428 #define ADC_CLMD_CLMD_SHIFT 0
429 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
430 /* CLMS Bit Fields */
431 #define ADC_CLMS_CLMS_MASK 0x3Fu
432 #define ADC_CLMS_CLMS_SHIFT 0
433 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
434 /* CLM4 Bit Fields */
435 #define ADC_CLM4_CLM4_MASK 0x3FFu
436 #define ADC_CLM4_CLM4_SHIFT 0
437 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
438 /* CLM3 Bit Fields */
439 #define ADC_CLM3_CLM3_MASK 0x1FFu
440 #define ADC_CLM3_CLM3_SHIFT 0
441 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
442 /* CLM2 Bit Fields */
443 #define ADC_CLM2_CLM2_MASK 0xFFu
444 #define ADC_CLM2_CLM2_SHIFT 0
445 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
446 /* CLM1 Bit Fields */
447 #define ADC_CLM1_CLM1_MASK 0x7Fu
448 #define ADC_CLM1_CLM1_SHIFT 0
449 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
450 /* CLM0 Bit Fields */
451 #define ADC_CLM0_CLM0_MASK 0x3Fu
452 #define ADC_CLM0_CLM0_SHIFT 0
453 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
454 
455 /**
456  * @}
457  */ /* end of group ADC_Register_Masks */
458 
459 
460 /* ADC - Peripheral instance base addresses */
461 /** Peripheral ADC0 base address */
462 #define ADC0_BASE (0x4003B000u)
463 /** Peripheral ADC0 base pointer */
464 #define ADC0 ((ADC_Type *)ADC0_BASE)
465 /** Peripheral ADC1 base address */
466 #define ADC1_BASE (0x400BB000u)
467 /** Peripheral ADC1 base pointer */
468 #define ADC1 ((ADC_Type *)ADC1_BASE)
469 /** Array initializer of ADC peripheral base pointers */
470 #define ADC_BASES { ADC0, ADC1 }
471 
472 /**
473  * @}
474  */ /* end of group ADC_Peripheral_Access_Layer */
475 
476 
477 /* ----------------------------------------------------------------------------
478  -- AIPS Peripheral Access Layer
479  ---------------------------------------------------------------------------- */
480 
481 /**
482  * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
483  * @{
484  */
485 
486 /** AIPS - Register Layout Typedef */
487 typedef struct {
488  __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
489  uint8_t RESERVED_0[28];
490  __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
491  __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
492  __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
493  __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
494  uint8_t RESERVED_1[16];
495  __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
496  __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
497  __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
498  __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
499  __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
500  __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
501  __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
502  __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
503  __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
504  __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
505  __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
506  __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
507 } AIPS_Type;
508 
509 /* ----------------------------------------------------------------------------
510  -- AIPS Register Masks
511  ---------------------------------------------------------------------------- */
512 
513 /**
514  * @addtogroup AIPS_Register_Masks AIPS Register Masks
515  * @{
516  */
517 
518 /* MPRA Bit Fields */
519 #define AIPS_MPRA_MPL5_MASK 0x100u
520 #define AIPS_MPRA_MPL5_SHIFT 8
521 #define AIPS_MPRA_MTW5_MASK 0x200u
522 #define AIPS_MPRA_MTW5_SHIFT 9
523 #define AIPS_MPRA_MTR5_MASK 0x400u
524 #define AIPS_MPRA_MTR5_SHIFT 10
525 #define AIPS_MPRA_MPL4_MASK 0x1000u
526 #define AIPS_MPRA_MPL4_SHIFT 12
527 #define AIPS_MPRA_MTW4_MASK 0x2000u
528 #define AIPS_MPRA_MTW4_SHIFT 13
529 #define AIPS_MPRA_MTR4_MASK 0x4000u
530 #define AIPS_MPRA_MTR4_SHIFT 14
531 #define AIPS_MPRA_MPL3_MASK 0x10000u
532 #define AIPS_MPRA_MPL3_SHIFT 16
533 #define AIPS_MPRA_MTW3_MASK 0x20000u
534 #define AIPS_MPRA_MTW3_SHIFT 17
535 #define AIPS_MPRA_MTR3_MASK 0x40000u
536 #define AIPS_MPRA_MTR3_SHIFT 18
537 #define AIPS_MPRA_MPL2_MASK 0x100000u
538 #define AIPS_MPRA_MPL2_SHIFT 20
539 #define AIPS_MPRA_MTW2_MASK 0x200000u
540 #define AIPS_MPRA_MTW2_SHIFT 21
541 #define AIPS_MPRA_MTR2_MASK 0x400000u
542 #define AIPS_MPRA_MTR2_SHIFT 22
543 #define AIPS_MPRA_MPL1_MASK 0x1000000u
544 #define AIPS_MPRA_MPL1_SHIFT 24
545 #define AIPS_MPRA_MTW1_MASK 0x2000000u
546 #define AIPS_MPRA_MTW1_SHIFT 25
547 #define AIPS_MPRA_MTR1_MASK 0x4000000u
548 #define AIPS_MPRA_MTR1_SHIFT 26
549 #define AIPS_MPRA_MPL0_MASK 0x10000000u
550 #define AIPS_MPRA_MPL0_SHIFT 28
551 #define AIPS_MPRA_MTW0_MASK 0x20000000u
552 #define AIPS_MPRA_MTW0_SHIFT 29
553 #define AIPS_MPRA_MTR0_MASK 0x40000000u
554 #define AIPS_MPRA_MTR0_SHIFT 30
555 /* PACRA Bit Fields */
556 #define AIPS_PACRA_TP7_MASK 0x1u
557 #define AIPS_PACRA_TP7_SHIFT 0
558 #define AIPS_PACRA_WP7_MASK 0x2u
559 #define AIPS_PACRA_WP7_SHIFT 1
560 #define AIPS_PACRA_SP7_MASK 0x4u
561 #define AIPS_PACRA_SP7_SHIFT 2
562 #define AIPS_PACRA_TP6_MASK 0x10u
563 #define AIPS_PACRA_TP6_SHIFT 4
564 #define AIPS_PACRA_WP6_MASK 0x20u
565 #define AIPS_PACRA_WP6_SHIFT 5
566 #define AIPS_PACRA_SP6_MASK 0x40u
567 #define AIPS_PACRA_SP6_SHIFT 6
568 #define AIPS_PACRA_TP5_MASK 0x100u
569 #define AIPS_PACRA_TP5_SHIFT 8
570 #define AIPS_PACRA_WP5_MASK 0x200u
571 #define AIPS_PACRA_WP5_SHIFT 9
572 #define AIPS_PACRA_SP5_MASK 0x400u
573 #define AIPS_PACRA_SP5_SHIFT 10
574 #define AIPS_PACRA_TP4_MASK 0x1000u
575 #define AIPS_PACRA_TP4_SHIFT 12
576 #define AIPS_PACRA_WP4_MASK 0x2000u
577 #define AIPS_PACRA_WP4_SHIFT 13
578 #define AIPS_PACRA_SP4_MASK 0x4000u
579 #define AIPS_PACRA_SP4_SHIFT 14
580 #define AIPS_PACRA_TP3_MASK 0x10000u
581 #define AIPS_PACRA_TP3_SHIFT 16
582 #define AIPS_PACRA_WP3_MASK 0x20000u
583 #define AIPS_PACRA_WP3_SHIFT 17
584 #define AIPS_PACRA_SP3_MASK 0x40000u
585 #define AIPS_PACRA_SP3_SHIFT 18
586 #define AIPS_PACRA_TP2_MASK 0x100000u
587 #define AIPS_PACRA_TP2_SHIFT 20
588 #define AIPS_PACRA_WP2_MASK 0x200000u
589 #define AIPS_PACRA_WP2_SHIFT 21
590 #define AIPS_PACRA_SP2_MASK 0x400000u
591 #define AIPS_PACRA_SP2_SHIFT 22
592 #define AIPS_PACRA_TP1_MASK 0x1000000u
593 #define AIPS_PACRA_TP1_SHIFT 24
594 #define AIPS_PACRA_WP1_MASK 0x2000000u
595 #define AIPS_PACRA_WP1_SHIFT 25
596 #define AIPS_PACRA_SP1_MASK 0x4000000u
597 #define AIPS_PACRA_SP1_SHIFT 26
598 #define AIPS_PACRA_TP0_MASK 0x10000000u
599 #define AIPS_PACRA_TP0_SHIFT 28
600 #define AIPS_PACRA_WP0_MASK 0x20000000u
601 #define AIPS_PACRA_WP0_SHIFT 29
602 #define AIPS_PACRA_SP0_MASK 0x40000000u
603 #define AIPS_PACRA_SP0_SHIFT 30
604 /* PACRB Bit Fields */
605 #define AIPS_PACRB_TP7_MASK 0x1u
606 #define AIPS_PACRB_TP7_SHIFT 0
607 #define AIPS_PACRB_WP7_MASK 0x2u
608 #define AIPS_PACRB_WP7_SHIFT 1
609 #define AIPS_PACRB_SP7_MASK 0x4u
610 #define AIPS_PACRB_SP7_SHIFT 2
611 #define AIPS_PACRB_TP6_MASK 0x10u
612 #define AIPS_PACRB_TP6_SHIFT 4
613 #define AIPS_PACRB_WP6_MASK 0x20u
614 #define AIPS_PACRB_WP6_SHIFT 5
615 #define AIPS_PACRB_SP6_MASK 0x40u
616 #define AIPS_PACRB_SP6_SHIFT 6
617 #define AIPS_PACRB_TP5_MASK 0x100u
618 #define AIPS_PACRB_TP5_SHIFT 8
619 #define AIPS_PACRB_WP5_MASK 0x200u
620 #define AIPS_PACRB_WP5_SHIFT 9
621 #define AIPS_PACRB_SP5_MASK 0x400u
622 #define AIPS_PACRB_SP5_SHIFT 10
623 #define AIPS_PACRB_TP4_MASK 0x1000u
624 #define AIPS_PACRB_TP4_SHIFT 12
625 #define AIPS_PACRB_WP4_MASK 0x2000u
626 #define AIPS_PACRB_WP4_SHIFT 13
627 #define AIPS_PACRB_SP4_MASK 0x4000u
628 #define AIPS_PACRB_SP4_SHIFT 14
629 #define AIPS_PACRB_TP3_MASK 0x10000u
630 #define AIPS_PACRB_TP3_SHIFT 16
631 #define AIPS_PACRB_WP3_MASK 0x20000u
632 #define AIPS_PACRB_WP3_SHIFT 17
633 #define AIPS_PACRB_SP3_MASK 0x40000u
634 #define AIPS_PACRB_SP3_SHIFT 18
635 #define AIPS_PACRB_TP2_MASK 0x100000u
636 #define AIPS_PACRB_TP2_SHIFT 20
637 #define AIPS_PACRB_WP2_MASK 0x200000u
638 #define AIPS_PACRB_WP2_SHIFT 21
639 #define AIPS_PACRB_SP2_MASK 0x400000u
640 #define AIPS_PACRB_SP2_SHIFT 22
641 #define AIPS_PACRB_TP1_MASK 0x1000000u
642 #define AIPS_PACRB_TP1_SHIFT 24
643 #define AIPS_PACRB_WP1_MASK 0x2000000u
644 #define AIPS_PACRB_WP1_SHIFT 25
645 #define AIPS_PACRB_SP1_MASK 0x4000000u
646 #define AIPS_PACRB_SP1_SHIFT 26
647 #define AIPS_PACRB_TP0_MASK 0x10000000u
648 #define AIPS_PACRB_TP0_SHIFT 28
649 #define AIPS_PACRB_WP0_MASK 0x20000000u
650 #define AIPS_PACRB_WP0_SHIFT 29
651 #define AIPS_PACRB_SP0_MASK 0x40000000u
652 #define AIPS_PACRB_SP0_SHIFT 30
653 /* PACRC Bit Fields */
654 #define AIPS_PACRC_TP7_MASK 0x1u
655 #define AIPS_PACRC_TP7_SHIFT 0
656 #define AIPS_PACRC_WP7_MASK 0x2u
657 #define AIPS_PACRC_WP7_SHIFT 1
658 #define AIPS_PACRC_SP7_MASK 0x4u
659 #define AIPS_PACRC_SP7_SHIFT 2
660 #define AIPS_PACRC_TP6_MASK 0x10u
661 #define AIPS_PACRC_TP6_SHIFT 4
662 #define AIPS_PACRC_WP6_MASK 0x20u
663 #define AIPS_PACRC_WP6_SHIFT 5
664 #define AIPS_PACRC_SP6_MASK 0x40u
665 #define AIPS_PACRC_SP6_SHIFT 6
666 #define AIPS_PACRC_TP5_MASK 0x100u
667 #define AIPS_PACRC_TP5_SHIFT 8
668 #define AIPS_PACRC_WP5_MASK 0x200u
669 #define AIPS_PACRC_WP5_SHIFT 9
670 #define AIPS_PACRC_SP5_MASK 0x400u
671 #define AIPS_PACRC_SP5_SHIFT 10
672 #define AIPS_PACRC_TP4_MASK 0x1000u
673 #define AIPS_PACRC_TP4_SHIFT 12
674 #define AIPS_PACRC_WP4_MASK 0x2000u
675 #define AIPS_PACRC_WP4_SHIFT 13
676 #define AIPS_PACRC_SP4_MASK 0x4000u
677 #define AIPS_PACRC_SP4_SHIFT 14
678 #define AIPS_PACRC_TP3_MASK 0x10000u
679 #define AIPS_PACRC_TP3_SHIFT 16
680 #define AIPS_PACRC_WP3_MASK 0x20000u
681 #define AIPS_PACRC_WP3_SHIFT 17
682 #define AIPS_PACRC_SP3_MASK 0x40000u
683 #define AIPS_PACRC_SP3_SHIFT 18
684 #define AIPS_PACRC_TP2_MASK 0x100000u
685 #define AIPS_PACRC_TP2_SHIFT 20
686 #define AIPS_PACRC_WP2_MASK 0x200000u
687 #define AIPS_PACRC_WP2_SHIFT 21
688 #define AIPS_PACRC_SP2_MASK 0x400000u
689 #define AIPS_PACRC_SP2_SHIFT 22
690 #define AIPS_PACRC_TP1_MASK 0x1000000u
691 #define AIPS_PACRC_TP1_SHIFT 24
692 #define AIPS_PACRC_WP1_MASK 0x2000000u
693 #define AIPS_PACRC_WP1_SHIFT 25
694 #define AIPS_PACRC_SP1_MASK 0x4000000u
695 #define AIPS_PACRC_SP1_SHIFT 26
696 #define AIPS_PACRC_TP0_MASK 0x10000000u
697 #define AIPS_PACRC_TP0_SHIFT 28
698 #define AIPS_PACRC_WP0_MASK 0x20000000u
699 #define AIPS_PACRC_WP0_SHIFT 29
700 #define AIPS_PACRC_SP0_MASK 0x40000000u
701 #define AIPS_PACRC_SP0_SHIFT 30
702 /* PACRD Bit Fields */
703 #define AIPS_PACRD_TP7_MASK 0x1u
704 #define AIPS_PACRD_TP7_SHIFT 0
705 #define AIPS_PACRD_WP7_MASK 0x2u
706 #define AIPS_PACRD_WP7_SHIFT 1
707 #define AIPS_PACRD_SP7_MASK 0x4u
708 #define AIPS_PACRD_SP7_SHIFT 2
709 #define AIPS_PACRD_TP6_MASK 0x10u
710 #define AIPS_PACRD_TP6_SHIFT 4
711 #define AIPS_PACRD_WP6_MASK 0x20u
712 #define AIPS_PACRD_WP6_SHIFT 5
713 #define AIPS_PACRD_SP6_MASK 0x40u
714 #define AIPS_PACRD_SP6_SHIFT 6
715 #define AIPS_PACRD_TP5_MASK 0x100u
716 #define AIPS_PACRD_TP5_SHIFT 8
717 #define AIPS_PACRD_WP5_MASK 0x200u
718 #define AIPS_PACRD_WP5_SHIFT 9
719 #define AIPS_PACRD_SP5_MASK 0x400u
720 #define AIPS_PACRD_SP5_SHIFT 10
721 #define AIPS_PACRD_TP4_MASK 0x1000u
722 #define AIPS_PACRD_TP4_SHIFT 12
723 #define AIPS_PACRD_WP4_MASK 0x2000u
724 #define AIPS_PACRD_WP4_SHIFT 13
725 #define AIPS_PACRD_SP4_MASK 0x4000u
726 #define AIPS_PACRD_SP4_SHIFT 14
727 #define AIPS_PACRD_TP3_MASK 0x10000u
728 #define AIPS_PACRD_TP3_SHIFT 16
729 #define AIPS_PACRD_WP3_MASK 0x20000u
730 #define AIPS_PACRD_WP3_SHIFT 17
731 #define AIPS_PACRD_SP3_MASK 0x40000u
732 #define AIPS_PACRD_SP3_SHIFT 18
733 #define AIPS_PACRD_TP2_MASK 0x100000u
734 #define AIPS_PACRD_TP2_SHIFT 20
735 #define AIPS_PACRD_WP2_MASK 0x200000u
736 #define AIPS_PACRD_WP2_SHIFT 21
737 #define AIPS_PACRD_SP2_MASK 0x400000u
738 #define AIPS_PACRD_SP2_SHIFT 22
739 #define AIPS_PACRD_TP1_MASK 0x1000000u
740 #define AIPS_PACRD_TP1_SHIFT 24
741 #define AIPS_PACRD_WP1_MASK 0x2000000u
742 #define AIPS_PACRD_WP1_SHIFT 25
743 #define AIPS_PACRD_SP1_MASK 0x4000000u
744 #define AIPS_PACRD_SP1_SHIFT 26
745 #define AIPS_PACRD_TP0_MASK 0x10000000u
746 #define AIPS_PACRD_TP0_SHIFT 28
747 #define AIPS_PACRD_WP0_MASK 0x20000000u
748 #define AIPS_PACRD_WP0_SHIFT 29
749 #define AIPS_PACRD_SP0_MASK 0x40000000u
750 #define AIPS_PACRD_SP0_SHIFT 30
751 /* PACRE Bit Fields */
752 #define AIPS_PACRE_TP7_MASK 0x1u
753 #define AIPS_PACRE_TP7_SHIFT 0
754 #define AIPS_PACRE_WP7_MASK 0x2u
755 #define AIPS_PACRE_WP7_SHIFT 1
756 #define AIPS_PACRE_SP7_MASK 0x4u
757 #define AIPS_PACRE_SP7_SHIFT 2
758 #define AIPS_PACRE_TP6_MASK 0x10u
759 #define AIPS_PACRE_TP6_SHIFT 4
760 #define AIPS_PACRE_WP6_MASK 0x20u
761 #define AIPS_PACRE_WP6_SHIFT 5
762 #define AIPS_PACRE_SP6_MASK 0x40u
763 #define AIPS_PACRE_SP6_SHIFT 6
764 #define AIPS_PACRE_TP5_MASK 0x100u
765 #define AIPS_PACRE_TP5_SHIFT 8
766 #define AIPS_PACRE_WP5_MASK 0x200u
767 #define AIPS_PACRE_WP5_SHIFT 9
768 #define AIPS_PACRE_SP5_MASK 0x400u
769 #define AIPS_PACRE_SP5_SHIFT 10
770 #define AIPS_PACRE_TP4_MASK 0x1000u
771 #define AIPS_PACRE_TP4_SHIFT 12
772 #define AIPS_PACRE_WP4_MASK 0x2000u
773 #define AIPS_PACRE_WP4_SHIFT 13
774 #define AIPS_PACRE_SP4_MASK 0x4000u
775 #define AIPS_PACRE_SP4_SHIFT 14
776 #define AIPS_PACRE_TP3_MASK 0x10000u
777 #define AIPS_PACRE_TP3_SHIFT 16
778 #define AIPS_PACRE_WP3_MASK 0x20000u
779 #define AIPS_PACRE_WP3_SHIFT 17
780 #define AIPS_PACRE_SP3_MASK 0x40000u
781 #define AIPS_PACRE_SP3_SHIFT 18
782 #define AIPS_PACRE_TP2_MASK 0x100000u
783 #define AIPS_PACRE_TP2_SHIFT 20
784 #define AIPS_PACRE_WP2_MASK 0x200000u
785 #define AIPS_PACRE_WP2_SHIFT 21
786 #define AIPS_PACRE_SP2_MASK 0x400000u
787 #define AIPS_PACRE_SP2_SHIFT 22
788 #define AIPS_PACRE_TP1_MASK 0x1000000u
789 #define AIPS_PACRE_TP1_SHIFT 24
790 #define AIPS_PACRE_WP1_MASK 0x2000000u
791 #define AIPS_PACRE_WP1_SHIFT 25
792 #define AIPS_PACRE_SP1_MASK 0x4000000u
793 #define AIPS_PACRE_SP1_SHIFT 26
794 #define AIPS_PACRE_TP0_MASK 0x10000000u
795 #define AIPS_PACRE_TP0_SHIFT 28
796 #define AIPS_PACRE_WP0_MASK 0x20000000u
797 #define AIPS_PACRE_WP0_SHIFT 29
798 #define AIPS_PACRE_SP0_MASK 0x40000000u
799 #define AIPS_PACRE_SP0_SHIFT 30
800 /* PACRF Bit Fields */
801 #define AIPS_PACRF_TP7_MASK 0x1u
802 #define AIPS_PACRF_TP7_SHIFT 0
803 #define AIPS_PACRF_WP7_MASK 0x2u
804 #define AIPS_PACRF_WP7_SHIFT 1
805 #define AIPS_PACRF_SP7_MASK 0x4u
806 #define AIPS_PACRF_SP7_SHIFT 2
807 #define AIPS_PACRF_TP6_MASK 0x10u
808 #define AIPS_PACRF_TP6_SHIFT 4
809 #define AIPS_PACRF_WP6_MASK 0x20u
810 #define AIPS_PACRF_WP6_SHIFT 5
811 #define AIPS_PACRF_SP6_MASK 0x40u
812 #define AIPS_PACRF_SP6_SHIFT 6
813 #define AIPS_PACRF_TP5_MASK 0x100u
814 #define AIPS_PACRF_TP5_SHIFT 8
815 #define AIPS_PACRF_WP5_MASK 0x200u
816 #define AIPS_PACRF_WP5_SHIFT 9
817 #define AIPS_PACRF_SP5_MASK 0x400u
818 #define AIPS_PACRF_SP5_SHIFT 10
819 #define AIPS_PACRF_TP4_MASK 0x1000u
820 #define AIPS_PACRF_TP4_SHIFT 12
821 #define AIPS_PACRF_WP4_MASK 0x2000u
822 #define AIPS_PACRF_WP4_SHIFT 13
823 #define AIPS_PACRF_SP4_MASK 0x4000u
824 #define AIPS_PACRF_SP4_SHIFT 14
825 #define AIPS_PACRF_TP3_MASK 0x10000u
826 #define AIPS_PACRF_TP3_SHIFT 16
827 #define AIPS_PACRF_WP3_MASK 0x20000u
828 #define AIPS_PACRF_WP3_SHIFT 17
829 #define AIPS_PACRF_SP3_MASK 0x40000u
830 #define AIPS_PACRF_SP3_SHIFT 18
831 #define AIPS_PACRF_TP2_MASK 0x100000u
832 #define AIPS_PACRF_TP2_SHIFT 20
833 #define AIPS_PACRF_WP2_MASK 0x200000u
834 #define AIPS_PACRF_WP2_SHIFT 21
835 #define AIPS_PACRF_SP2_MASK 0x400000u
836 #define AIPS_PACRF_SP2_SHIFT 22
837 #define AIPS_PACRF_TP1_MASK 0x1000000u
838 #define AIPS_PACRF_TP1_SHIFT 24
839 #define AIPS_PACRF_WP1_MASK 0x2000000u
840 #define AIPS_PACRF_WP1_SHIFT 25
841 #define AIPS_PACRF_SP1_MASK 0x4000000u
842 #define AIPS_PACRF_SP1_SHIFT 26
843 #define AIPS_PACRF_TP0_MASK 0x10000000u
844 #define AIPS_PACRF_TP0_SHIFT 28
845 #define AIPS_PACRF_WP0_MASK 0x20000000u
846 #define AIPS_PACRF_WP0_SHIFT 29
847 #define AIPS_PACRF_SP0_MASK 0x40000000u
848 #define AIPS_PACRF_SP0_SHIFT 30
849 /* PACRG Bit Fields */
850 #define AIPS_PACRG_TP7_MASK 0x1u
851 #define AIPS_PACRG_TP7_SHIFT 0
852 #define AIPS_PACRG_WP7_MASK 0x2u
853 #define AIPS_PACRG_WP7_SHIFT 1
854 #define AIPS_PACRG_SP7_MASK 0x4u
855 #define AIPS_PACRG_SP7_SHIFT 2
856 #define AIPS_PACRG_TP6_MASK 0x10u
857 #define AIPS_PACRG_TP6_SHIFT 4
858 #define AIPS_PACRG_WP6_MASK 0x20u
859 #define AIPS_PACRG_WP6_SHIFT 5
860 #define AIPS_PACRG_SP6_MASK 0x40u
861 #define AIPS_PACRG_SP6_SHIFT 6
862 #define AIPS_PACRG_TP5_MASK 0x100u
863 #define AIPS_PACRG_TP5_SHIFT 8
864 #define AIPS_PACRG_WP5_MASK 0x200u
865 #define AIPS_PACRG_WP5_SHIFT 9
866 #define AIPS_PACRG_SP5_MASK 0x400u
867 #define AIPS_PACRG_SP5_SHIFT 10
868 #define AIPS_PACRG_TP4_MASK 0x1000u
869 #define AIPS_PACRG_TP4_SHIFT 12
870 #define AIPS_PACRG_WP4_MASK 0x2000u
871 #define AIPS_PACRG_WP4_SHIFT 13
872 #define AIPS_PACRG_SP4_MASK 0x4000u
873 #define AIPS_PACRG_SP4_SHIFT 14
874 #define AIPS_PACRG_TP3_MASK 0x10000u
875 #define AIPS_PACRG_TP3_SHIFT 16
876 #define AIPS_PACRG_WP3_MASK 0x20000u
877 #define AIPS_PACRG_WP3_SHIFT 17
878 #define AIPS_PACRG_SP3_MASK 0x40000u
879 #define AIPS_PACRG_SP3_SHIFT 18
880 #define AIPS_PACRG_TP2_MASK 0x100000u
881 #define AIPS_PACRG_TP2_SHIFT 20
882 #define AIPS_PACRG_WP2_MASK 0x200000u
883 #define AIPS_PACRG_WP2_SHIFT 21
884 #define AIPS_PACRG_SP2_MASK 0x400000u
885 #define AIPS_PACRG_SP2_SHIFT 22
886 #define AIPS_PACRG_TP1_MASK 0x1000000u
887 #define AIPS_PACRG_TP1_SHIFT 24
888 #define AIPS_PACRG_WP1_MASK 0x2000000u
889 #define AIPS_PACRG_WP1_SHIFT 25
890 #define AIPS_PACRG_SP1_MASK 0x4000000u
891 #define AIPS_PACRG_SP1_SHIFT 26
892 #define AIPS_PACRG_TP0_MASK 0x10000000u
893 #define AIPS_PACRG_TP0_SHIFT 28
894 #define AIPS_PACRG_WP0_MASK 0x20000000u
895 #define AIPS_PACRG_WP0_SHIFT 29
896 #define AIPS_PACRG_SP0_MASK 0x40000000u
897 #define AIPS_PACRG_SP0_SHIFT 30
898 /* PACRH Bit Fields */
899 #define AIPS_PACRH_TP7_MASK 0x1u
900 #define AIPS_PACRH_TP7_SHIFT 0
901 #define AIPS_PACRH_WP7_MASK 0x2u
902 #define AIPS_PACRH_WP7_SHIFT 1
903 #define AIPS_PACRH_SP7_MASK 0x4u
904 #define AIPS_PACRH_SP7_SHIFT 2
905 #define AIPS_PACRH_TP6_MASK 0x10u
906 #define AIPS_PACRH_TP6_SHIFT 4
907 #define AIPS_PACRH_WP6_MASK 0x20u
908 #define AIPS_PACRH_WP6_SHIFT 5
909 #define AIPS_PACRH_SP6_MASK 0x40u
910 #define AIPS_PACRH_SP6_SHIFT 6
911 #define AIPS_PACRH_TP5_MASK 0x100u
912 #define AIPS_PACRH_TP5_SHIFT 8
913 #define AIPS_PACRH_WP5_MASK 0x200u
914 #define AIPS_PACRH_WP5_SHIFT 9
915 #define AIPS_PACRH_SP5_MASK 0x400u
916 #define AIPS_PACRH_SP5_SHIFT 10
917 #define AIPS_PACRH_TP4_MASK 0x1000u
918 #define AIPS_PACRH_TP4_SHIFT 12
919 #define AIPS_PACRH_WP4_MASK 0x2000u
920 #define AIPS_PACRH_WP4_SHIFT 13
921 #define AIPS_PACRH_SP4_MASK 0x4000u
922 #define AIPS_PACRH_SP4_SHIFT 14
923 #define AIPS_PACRH_TP3_MASK 0x10000u
924 #define AIPS_PACRH_TP3_SHIFT 16
925 #define AIPS_PACRH_WP3_MASK 0x20000u
926 #define AIPS_PACRH_WP3_SHIFT 17
927 #define AIPS_PACRH_SP3_MASK 0x40000u
928 #define AIPS_PACRH_SP3_SHIFT 18
929 #define AIPS_PACRH_TP2_MASK 0x100000u
930 #define AIPS_PACRH_TP2_SHIFT 20
931 #define AIPS_PACRH_WP2_MASK 0x200000u
932 #define AIPS_PACRH_WP2_SHIFT 21
933 #define AIPS_PACRH_SP2_MASK 0x400000u
934 #define AIPS_PACRH_SP2_SHIFT 22
935 #define AIPS_PACRH_TP1_MASK 0x1000000u
936 #define AIPS_PACRH_TP1_SHIFT 24
937 #define AIPS_PACRH_WP1_MASK 0x2000000u
938 #define AIPS_PACRH_WP1_SHIFT 25
939 #define AIPS_PACRH_SP1_MASK 0x4000000u
940 #define AIPS_PACRH_SP1_SHIFT 26
941 #define AIPS_PACRH_TP0_MASK 0x10000000u
942 #define AIPS_PACRH_TP0_SHIFT 28
943 #define AIPS_PACRH_WP0_MASK 0x20000000u
944 #define AIPS_PACRH_WP0_SHIFT 29
945 #define AIPS_PACRH_SP0_MASK 0x40000000u
946 #define AIPS_PACRH_SP0_SHIFT 30
947 /* PACRI Bit Fields */
948 #define AIPS_PACRI_TP7_MASK 0x1u
949 #define AIPS_PACRI_TP7_SHIFT 0
950 #define AIPS_PACRI_WP7_MASK 0x2u
951 #define AIPS_PACRI_WP7_SHIFT 1
952 #define AIPS_PACRI_SP7_MASK 0x4u
953 #define AIPS_PACRI_SP7_SHIFT 2
954 #define AIPS_PACRI_TP6_MASK 0x10u
955 #define AIPS_PACRI_TP6_SHIFT 4
956 #define AIPS_PACRI_WP6_MASK 0x20u
957 #define AIPS_PACRI_WP6_SHIFT 5
958 #define AIPS_PACRI_SP6_MASK 0x40u
959 #define AIPS_PACRI_SP6_SHIFT 6
960 #define AIPS_PACRI_TP5_MASK 0x100u
961 #define AIPS_PACRI_TP5_SHIFT 8
962 #define AIPS_PACRI_WP5_MASK 0x200u
963 #define AIPS_PACRI_WP5_SHIFT 9
964 #define AIPS_PACRI_SP5_MASK 0x400u
965 #define AIPS_PACRI_SP5_SHIFT 10
966 #define AIPS_PACRI_TP4_MASK 0x1000u
967 #define AIPS_PACRI_TP4_SHIFT 12
968 #define AIPS_PACRI_WP4_MASK 0x2000u
969 #define AIPS_PACRI_WP4_SHIFT 13
970 #define AIPS_PACRI_SP4_MASK 0x4000u
971 #define AIPS_PACRI_SP4_SHIFT 14
972 #define AIPS_PACRI_TP3_MASK 0x10000u
973 #define AIPS_PACRI_TP3_SHIFT 16
974 #define AIPS_PACRI_WP3_MASK 0x20000u
975 #define AIPS_PACRI_WP3_SHIFT 17
976 #define AIPS_PACRI_SP3_MASK 0x40000u
977 #define AIPS_PACRI_SP3_SHIFT 18
978 #define AIPS_PACRI_TP2_MASK 0x100000u
979 #define AIPS_PACRI_TP2_SHIFT 20
980 #define AIPS_PACRI_WP2_MASK 0x200000u
981 #define AIPS_PACRI_WP2_SHIFT 21
982 #define AIPS_PACRI_SP2_MASK 0x400000u
983 #define AIPS_PACRI_SP2_SHIFT 22
984 #define AIPS_PACRI_TP1_MASK 0x1000000u
985 #define AIPS_PACRI_TP1_SHIFT 24
986 #define AIPS_PACRI_WP1_MASK 0x2000000u
987 #define AIPS_PACRI_WP1_SHIFT 25
988 #define AIPS_PACRI_SP1_MASK 0x4000000u
989 #define AIPS_PACRI_SP1_SHIFT 26
990 #define AIPS_PACRI_TP0_MASK 0x10000000u
991 #define AIPS_PACRI_TP0_SHIFT 28
992 #define AIPS_PACRI_WP0_MASK 0x20000000u
993 #define AIPS_PACRI_WP0_SHIFT 29
994 #define AIPS_PACRI_SP0_MASK 0x40000000u
995 #define AIPS_PACRI_SP0_SHIFT 30
996 /* PACRJ Bit Fields */
997 #define AIPS_PACRJ_TP7_MASK 0x1u
998 #define AIPS_PACRJ_TP7_SHIFT 0
999 #define AIPS_PACRJ_WP7_MASK 0x2u
1000 #define AIPS_PACRJ_WP7_SHIFT 1
1001 #define AIPS_PACRJ_SP7_MASK 0x4u
1002 #define AIPS_PACRJ_SP7_SHIFT 2
1003 #define AIPS_PACRJ_TP6_MASK 0x10u
1004 #define AIPS_PACRJ_TP6_SHIFT 4
1005 #define AIPS_PACRJ_WP6_MASK 0x20u
1006 #define AIPS_PACRJ_WP6_SHIFT 5
1007 #define AIPS_PACRJ_SP6_MASK 0x40u
1008 #define AIPS_PACRJ_SP6_SHIFT 6
1009 #define AIPS_PACRJ_TP5_MASK 0x100u
1010 #define AIPS_PACRJ_TP5_SHIFT 8
1011 #define AIPS_PACRJ_WP5_MASK 0x200u
1012 #define AIPS_PACRJ_WP5_SHIFT 9
1013 #define AIPS_PACRJ_SP5_MASK 0x400u
1014 #define AIPS_PACRJ_SP5_SHIFT 10
1015 #define AIPS_PACRJ_TP4_MASK 0x1000u
1016 #define AIPS_PACRJ_TP4_SHIFT 12
1017 #define AIPS_PACRJ_WP4_MASK 0x2000u
1018 #define AIPS_PACRJ_WP4_SHIFT 13
1019 #define AIPS_PACRJ_SP4_MASK 0x4000u
1020 #define AIPS_PACRJ_SP4_SHIFT 14
1021 #define AIPS_PACRJ_TP3_MASK 0x10000u
1022 #define AIPS_PACRJ_TP3_SHIFT 16
1023 #define AIPS_PACRJ_WP3_MASK 0x20000u
1024 #define AIPS_PACRJ_WP3_SHIFT 17
1025 #define AIPS_PACRJ_SP3_MASK 0x40000u
1026 #define AIPS_PACRJ_SP3_SHIFT 18
1027 #define AIPS_PACRJ_TP2_MASK 0x100000u
1028 #define AIPS_PACRJ_TP2_SHIFT 20
1029 #define AIPS_PACRJ_WP2_MASK 0x200000u
1030 #define AIPS_PACRJ_WP2_SHIFT 21
1031 #define AIPS_PACRJ_SP2_MASK 0x400000u
1032 #define AIPS_PACRJ_SP2_SHIFT 22
1033 #define AIPS_PACRJ_TP1_MASK 0x1000000u
1034 #define AIPS_PACRJ_TP1_SHIFT 24
1035 #define AIPS_PACRJ_WP1_MASK 0x2000000u
1036 #define AIPS_PACRJ_WP1_SHIFT 25
1037 #define AIPS_PACRJ_SP1_MASK 0x4000000u
1038 #define AIPS_PACRJ_SP1_SHIFT 26
1039 #define AIPS_PACRJ_TP0_MASK 0x10000000u
1040 #define AIPS_PACRJ_TP0_SHIFT 28
1041 #define AIPS_PACRJ_WP0_MASK 0x20000000u
1042 #define AIPS_PACRJ_WP0_SHIFT 29
1043 #define AIPS_PACRJ_SP0_MASK 0x40000000u
1044 #define AIPS_PACRJ_SP0_SHIFT 30
1045 /* PACRK Bit Fields */
1046 #define AIPS_PACRK_TP7_MASK 0x1u
1047 #define AIPS_PACRK_TP7_SHIFT 0
1048 #define AIPS_PACRK_WP7_MASK 0x2u
1049 #define AIPS_PACRK_WP7_SHIFT 1
1050 #define AIPS_PACRK_SP7_MASK 0x4u
1051 #define AIPS_PACRK_SP7_SHIFT 2
1052 #define AIPS_PACRK_TP6_MASK 0x10u
1053 #define AIPS_PACRK_TP6_SHIFT 4
1054 #define AIPS_PACRK_WP6_MASK 0x20u
1055 #define AIPS_PACRK_WP6_SHIFT 5
1056 #define AIPS_PACRK_SP6_MASK 0x40u
1057 #define AIPS_PACRK_SP6_SHIFT 6
1058 #define AIPS_PACRK_TP5_MASK 0x100u
1059 #define AIPS_PACRK_TP5_SHIFT 8
1060 #define AIPS_PACRK_WP5_MASK 0x200u
1061 #define AIPS_PACRK_WP5_SHIFT 9
1062 #define AIPS_PACRK_SP5_MASK 0x400u
1063 #define AIPS_PACRK_SP5_SHIFT 10
1064 #define AIPS_PACRK_TP4_MASK 0x1000u
1065 #define AIPS_PACRK_TP4_SHIFT 12
1066 #define AIPS_PACRK_WP4_MASK 0x2000u
1067 #define AIPS_PACRK_WP4_SHIFT 13
1068 #define AIPS_PACRK_SP4_MASK 0x4000u
1069 #define AIPS_PACRK_SP4_SHIFT 14
1070 #define AIPS_PACRK_TP3_MASK 0x10000u
1071 #define AIPS_PACRK_TP3_SHIFT 16
1072 #define AIPS_PACRK_WP3_MASK 0x20000u
1073 #define AIPS_PACRK_WP3_SHIFT 17
1074 #define AIPS_PACRK_SP3_MASK 0x40000u
1075 #define AIPS_PACRK_SP3_SHIFT 18
1076 #define AIPS_PACRK_TP2_MASK 0x100000u
1077 #define AIPS_PACRK_TP2_SHIFT 20
1078 #define AIPS_PACRK_WP2_MASK 0x200000u
1079 #define AIPS_PACRK_WP2_SHIFT 21
1080 #define AIPS_PACRK_SP2_MASK 0x400000u
1081 #define AIPS_PACRK_SP2_SHIFT 22
1082 #define AIPS_PACRK_TP1_MASK 0x1000000u
1083 #define AIPS_PACRK_TP1_SHIFT 24
1084 #define AIPS_PACRK_WP1_MASK 0x2000000u
1085 #define AIPS_PACRK_WP1_SHIFT 25
1086 #define AIPS_PACRK_SP1_MASK 0x4000000u
1087 #define AIPS_PACRK_SP1_SHIFT 26
1088 #define AIPS_PACRK_TP0_MASK 0x10000000u
1089 #define AIPS_PACRK_TP0_SHIFT 28
1090 #define AIPS_PACRK_WP0_MASK 0x20000000u
1091 #define AIPS_PACRK_WP0_SHIFT 29
1092 #define AIPS_PACRK_SP0_MASK 0x40000000u
1093 #define AIPS_PACRK_SP0_SHIFT 30
1094 /* PACRL Bit Fields */
1095 #define AIPS_PACRL_TP7_MASK 0x1u
1096 #define AIPS_PACRL_TP7_SHIFT 0
1097 #define AIPS_PACRL_WP7_MASK 0x2u
1098 #define AIPS_PACRL_WP7_SHIFT 1
1099 #define AIPS_PACRL_SP7_MASK 0x4u
1100 #define AIPS_PACRL_SP7_SHIFT 2
1101 #define AIPS_PACRL_TP6_MASK 0x10u
1102 #define AIPS_PACRL_TP6_SHIFT 4
1103 #define AIPS_PACRL_WP6_MASK 0x20u
1104 #define AIPS_PACRL_WP6_SHIFT 5
1105 #define AIPS_PACRL_SP6_MASK 0x40u
1106 #define AIPS_PACRL_SP6_SHIFT 6
1107 #define AIPS_PACRL_TP5_MASK 0x100u
1108 #define AIPS_PACRL_TP5_SHIFT 8
1109 #define AIPS_PACRL_WP5_MASK 0x200u
1110 #define AIPS_PACRL_WP5_SHIFT 9
1111 #define AIPS_PACRL_SP5_MASK 0x400u
1112 #define AIPS_PACRL_SP5_SHIFT 10
1113 #define AIPS_PACRL_TP4_MASK 0x1000u
1114 #define AIPS_PACRL_TP4_SHIFT 12
1115 #define AIPS_PACRL_WP4_MASK 0x2000u
1116 #define AIPS_PACRL_WP4_SHIFT 13
1117 #define AIPS_PACRL_SP4_MASK 0x4000u
1118 #define AIPS_PACRL_SP4_SHIFT 14
1119 #define AIPS_PACRL_TP3_MASK 0x10000u
1120 #define AIPS_PACRL_TP3_SHIFT 16
1121 #define AIPS_PACRL_WP3_MASK 0x20000u
1122 #define AIPS_PACRL_WP3_SHIFT 17
1123 #define AIPS_PACRL_SP3_MASK 0x40000u
1124 #define AIPS_PACRL_SP3_SHIFT 18
1125 #define AIPS_PACRL_TP2_MASK 0x100000u
1126 #define AIPS_PACRL_TP2_SHIFT 20
1127 #define AIPS_PACRL_WP2_MASK 0x200000u
1128 #define AIPS_PACRL_WP2_SHIFT 21
1129 #define AIPS_PACRL_SP2_MASK 0x400000u
1130 #define AIPS_PACRL_SP2_SHIFT 22
1131 #define AIPS_PACRL_TP1_MASK 0x1000000u
1132 #define AIPS_PACRL_TP1_SHIFT 24
1133 #define AIPS_PACRL_WP1_MASK 0x2000000u
1134 #define AIPS_PACRL_WP1_SHIFT 25
1135 #define AIPS_PACRL_SP1_MASK 0x4000000u
1136 #define AIPS_PACRL_SP1_SHIFT 26
1137 #define AIPS_PACRL_TP0_MASK 0x10000000u
1138 #define AIPS_PACRL_TP0_SHIFT 28
1139 #define AIPS_PACRL_WP0_MASK 0x20000000u
1140 #define AIPS_PACRL_WP0_SHIFT 29
1141 #define AIPS_PACRL_SP0_MASK 0x40000000u
1142 #define AIPS_PACRL_SP0_SHIFT 30
1143 /* PACRM Bit Fields */
1144 #define AIPS_PACRM_TP7_MASK 0x1u
1145 #define AIPS_PACRM_TP7_SHIFT 0
1146 #define AIPS_PACRM_WP7_MASK 0x2u
1147 #define AIPS_PACRM_WP7_SHIFT 1
1148 #define AIPS_PACRM_SP7_MASK 0x4u
1149 #define AIPS_PACRM_SP7_SHIFT 2
1150 #define AIPS_PACRM_TP6_MASK 0x10u
1151 #define AIPS_PACRM_TP6_SHIFT 4
1152 #define AIPS_PACRM_WP6_MASK 0x20u
1153 #define AIPS_PACRM_WP6_SHIFT 5
1154 #define AIPS_PACRM_SP6_MASK 0x40u
1155 #define AIPS_PACRM_SP6_SHIFT 6
1156 #define AIPS_PACRM_TP5_MASK 0x100u
1157 #define AIPS_PACRM_TP5_SHIFT 8
1158 #define AIPS_PACRM_WP5_MASK 0x200u
1159 #define AIPS_PACRM_WP5_SHIFT 9
1160 #define AIPS_PACRM_SP5_MASK 0x400u
1161 #define AIPS_PACRM_SP5_SHIFT 10
1162 #define AIPS_PACRM_TP4_MASK 0x1000u
1163 #define AIPS_PACRM_TP4_SHIFT 12
1164 #define AIPS_PACRM_WP4_MASK 0x2000u
1165 #define AIPS_PACRM_WP4_SHIFT 13
1166 #define AIPS_PACRM_SP4_MASK 0x4000u
1167 #define AIPS_PACRM_SP4_SHIFT 14
1168 #define AIPS_PACRM_TP3_MASK 0x10000u
1169 #define AIPS_PACRM_TP3_SHIFT 16
1170 #define AIPS_PACRM_WP3_MASK 0x20000u
1171 #define AIPS_PACRM_WP3_SHIFT 17
1172 #define AIPS_PACRM_SP3_MASK 0x40000u
1173 #define AIPS_PACRM_SP3_SHIFT 18
1174 #define AIPS_PACRM_TP2_MASK 0x100000u
1175 #define AIPS_PACRM_TP2_SHIFT 20
1176 #define AIPS_PACRM_WP2_MASK 0x200000u
1177 #define AIPS_PACRM_WP2_SHIFT 21
1178 #define AIPS_PACRM_SP2_MASK 0x400000u
1179 #define AIPS_PACRM_SP2_SHIFT 22
1180 #define AIPS_PACRM_TP1_MASK 0x1000000u
1181 #define AIPS_PACRM_TP1_SHIFT 24
1182 #define AIPS_PACRM_WP1_MASK 0x2000000u
1183 #define AIPS_PACRM_WP1_SHIFT 25
1184 #define AIPS_PACRM_SP1_MASK 0x4000000u
1185 #define AIPS_PACRM_SP1_SHIFT 26
1186 #define AIPS_PACRM_TP0_MASK 0x10000000u
1187 #define AIPS_PACRM_TP0_SHIFT 28
1188 #define AIPS_PACRM_WP0_MASK 0x20000000u
1189 #define AIPS_PACRM_WP0_SHIFT 29
1190 #define AIPS_PACRM_SP0_MASK 0x40000000u
1191 #define AIPS_PACRM_SP0_SHIFT 30
1192 /* PACRN Bit Fields */
1193 #define AIPS_PACRN_TP7_MASK 0x1u
1194 #define AIPS_PACRN_TP7_SHIFT 0
1195 #define AIPS_PACRN_WP7_MASK 0x2u
1196 #define AIPS_PACRN_WP7_SHIFT 1
1197 #define AIPS_PACRN_SP7_MASK 0x4u
1198 #define AIPS_PACRN_SP7_SHIFT 2
1199 #define AIPS_PACRN_TP6_MASK 0x10u
1200 #define AIPS_PACRN_TP6_SHIFT 4
1201 #define AIPS_PACRN_WP6_MASK 0x20u
1202 #define AIPS_PACRN_WP6_SHIFT 5
1203 #define AIPS_PACRN_SP6_MASK 0x40u
1204 #define AIPS_PACRN_SP6_SHIFT 6
1205 #define AIPS_PACRN_TP5_MASK 0x100u
1206 #define AIPS_PACRN_TP5_SHIFT 8
1207 #define AIPS_PACRN_WP5_MASK 0x200u
1208 #define AIPS_PACRN_WP5_SHIFT 9
1209 #define AIPS_PACRN_SP5_MASK 0x400u
1210 #define AIPS_PACRN_SP5_SHIFT 10
1211 #define AIPS_PACRN_TP4_MASK 0x1000u
1212 #define AIPS_PACRN_TP4_SHIFT 12
1213 #define AIPS_PACRN_WP4_MASK 0x2000u
1214 #define AIPS_PACRN_WP4_SHIFT 13
1215 #define AIPS_PACRN_SP4_MASK 0x4000u
1216 #define AIPS_PACRN_SP4_SHIFT 14
1217 #define AIPS_PACRN_TP3_MASK 0x10000u
1218 #define AIPS_PACRN_TP3_SHIFT 16
1219 #define AIPS_PACRN_WP3_MASK 0x20000u
1220 #define AIPS_PACRN_WP3_SHIFT 17
1221 #define AIPS_PACRN_SP3_MASK 0x40000u
1222 #define AIPS_PACRN_SP3_SHIFT 18
1223 #define AIPS_PACRN_TP2_MASK 0x100000u
1224 #define AIPS_PACRN_TP2_SHIFT 20
1225 #define AIPS_PACRN_WP2_MASK 0x200000u
1226 #define AIPS_PACRN_WP2_SHIFT 21
1227 #define AIPS_PACRN_SP2_MASK 0x400000u
1228 #define AIPS_PACRN_SP2_SHIFT 22
1229 #define AIPS_PACRN_TP1_MASK 0x1000000u
1230 #define AIPS_PACRN_TP1_SHIFT 24
1231 #define AIPS_PACRN_WP1_MASK 0x2000000u
1232 #define AIPS_PACRN_WP1_SHIFT 25
1233 #define AIPS_PACRN_SP1_MASK 0x4000000u
1234 #define AIPS_PACRN_SP1_SHIFT 26
1235 #define AIPS_PACRN_TP0_MASK 0x10000000u
1236 #define AIPS_PACRN_TP0_SHIFT 28
1237 #define AIPS_PACRN_WP0_MASK 0x20000000u
1238 #define AIPS_PACRN_WP0_SHIFT 29
1239 #define AIPS_PACRN_SP0_MASK 0x40000000u
1240 #define AIPS_PACRN_SP0_SHIFT 30
1241 /* PACRO Bit Fields */
1242 #define AIPS_PACRO_TP7_MASK 0x1u
1243 #define AIPS_PACRO_TP7_SHIFT 0
1244 #define AIPS_PACRO_WP7_MASK 0x2u
1245 #define AIPS_PACRO_WP7_SHIFT 1
1246 #define AIPS_PACRO_SP7_MASK 0x4u
1247 #define AIPS_PACRO_SP7_SHIFT 2
1248 #define AIPS_PACRO_TP6_MASK 0x10u
1249 #define AIPS_PACRO_TP6_SHIFT 4
1250 #define AIPS_PACRO_WP6_MASK 0x20u
1251 #define AIPS_PACRO_WP6_SHIFT 5
1252 #define AIPS_PACRO_SP6_MASK 0x40u
1253 #define AIPS_PACRO_SP6_SHIFT 6
1254 #define AIPS_PACRO_TP5_MASK 0x100u
1255 #define AIPS_PACRO_TP5_SHIFT 8
1256 #define AIPS_PACRO_WP5_MASK 0x200u
1257 #define AIPS_PACRO_WP5_SHIFT 9
1258 #define AIPS_PACRO_SP5_MASK 0x400u
1259 #define AIPS_PACRO_SP5_SHIFT 10
1260 #define AIPS_PACRO_TP4_MASK 0x1000u
1261 #define AIPS_PACRO_TP4_SHIFT 12
1262 #define AIPS_PACRO_WP4_MASK 0x2000u
1263 #define AIPS_PACRO_WP4_SHIFT 13
1264 #define AIPS_PACRO_SP4_MASK 0x4000u
1265 #define AIPS_PACRO_SP4_SHIFT 14
1266 #define AIPS_PACRO_TP3_MASK 0x10000u
1267 #define AIPS_PACRO_TP3_SHIFT 16
1268 #define AIPS_PACRO_WP3_MASK 0x20000u
1269 #define AIPS_PACRO_WP3_SHIFT 17
1270 #define AIPS_PACRO_SP3_MASK 0x40000u
1271 #define AIPS_PACRO_SP3_SHIFT 18
1272 #define AIPS_PACRO_TP2_MASK 0x100000u
1273 #define AIPS_PACRO_TP2_SHIFT 20
1274 #define AIPS_PACRO_WP2_MASK 0x200000u
1275 #define AIPS_PACRO_WP2_SHIFT 21
1276 #define AIPS_PACRO_SP2_MASK 0x400000u
1277 #define AIPS_PACRO_SP2_SHIFT 22
1278 #define AIPS_PACRO_TP1_MASK 0x1000000u
1279 #define AIPS_PACRO_TP1_SHIFT 24
1280 #define AIPS_PACRO_WP1_MASK 0x2000000u
1281 #define AIPS_PACRO_WP1_SHIFT 25
1282 #define AIPS_PACRO_SP1_MASK 0x4000000u
1283 #define AIPS_PACRO_SP1_SHIFT 26
1284 #define AIPS_PACRO_TP0_MASK 0x10000000u
1285 #define AIPS_PACRO_TP0_SHIFT 28
1286 #define AIPS_PACRO_WP0_MASK 0x20000000u
1287 #define AIPS_PACRO_WP0_SHIFT 29
1288 #define AIPS_PACRO_SP0_MASK 0x40000000u
1289 #define AIPS_PACRO_SP0_SHIFT 30
1290 /* PACRP Bit Fields */
1291 #define AIPS_PACRP_TP7_MASK 0x1u
1292 #define AIPS_PACRP_TP7_SHIFT 0
1293 #define AIPS_PACRP_WP7_MASK 0x2u
1294 #define AIPS_PACRP_WP7_SHIFT 1
1295 #define AIPS_PACRP_SP7_MASK 0x4u
1296 #define AIPS_PACRP_SP7_SHIFT 2
1297 #define AIPS_PACRP_TP6_MASK 0x10u
1298 #define AIPS_PACRP_TP6_SHIFT 4
1299 #define AIPS_PACRP_WP6_MASK 0x20u
1300 #define AIPS_PACRP_WP6_SHIFT 5
1301 #define AIPS_PACRP_SP6_MASK 0x40u
1302 #define AIPS_PACRP_SP6_SHIFT 6
1303 #define AIPS_PACRP_TP5_MASK 0x100u
1304 #define AIPS_PACRP_TP5_SHIFT 8
1305 #define AIPS_PACRP_WP5_MASK 0x200u
1306 #define AIPS_PACRP_WP5_SHIFT 9
1307 #define AIPS_PACRP_SP5_MASK 0x400u
1308 #define AIPS_PACRP_SP5_SHIFT 10
1309 #define AIPS_PACRP_TP4_MASK 0x1000u
1310 #define AIPS_PACRP_TP4_SHIFT 12
1311 #define AIPS_PACRP_WP4_MASK 0x2000u
1312 #define AIPS_PACRP_WP4_SHIFT 13
1313 #define AIPS_PACRP_SP4_MASK 0x4000u
1314 #define AIPS_PACRP_SP4_SHIFT 14
1315 #define AIPS_PACRP_TP3_MASK 0x10000u
1316 #define AIPS_PACRP_TP3_SHIFT 16
1317 #define AIPS_PACRP_WP3_MASK 0x20000u
1318 #define AIPS_PACRP_WP3_SHIFT 17
1319 #define AIPS_PACRP_SP3_MASK 0x40000u
1320 #define AIPS_PACRP_SP3_SHIFT 18
1321 #define AIPS_PACRP_TP2_MASK 0x100000u
1322 #define AIPS_PACRP_TP2_SHIFT 20
1323 #define AIPS_PACRP_WP2_MASK 0x200000u
1324 #define AIPS_PACRP_WP2_SHIFT 21
1325 #define AIPS_PACRP_SP2_MASK 0x400000u
1326 #define AIPS_PACRP_SP2_SHIFT 22
1327 #define AIPS_PACRP_TP1_MASK 0x1000000u
1328 #define AIPS_PACRP_TP1_SHIFT 24
1329 #define AIPS_PACRP_WP1_MASK 0x2000000u
1330 #define AIPS_PACRP_WP1_SHIFT 25
1331 #define AIPS_PACRP_SP1_MASK 0x4000000u
1332 #define AIPS_PACRP_SP1_SHIFT 26
1333 #define AIPS_PACRP_TP0_MASK 0x10000000u
1334 #define AIPS_PACRP_TP0_SHIFT 28
1335 #define AIPS_PACRP_WP0_MASK 0x20000000u
1336 #define AIPS_PACRP_WP0_SHIFT 29
1337 #define AIPS_PACRP_SP0_MASK 0x40000000u
1338 #define AIPS_PACRP_SP0_SHIFT 30
1339 
1340 /**
1341  * @}
1342  */ /* end of group AIPS_Register_Masks */
1343 
1344 
1345 /* AIPS - Peripheral instance base addresses */
1346 /** Peripheral AIPS0 base address */
1347 #define AIPS0_BASE (0x40000000u)
1348 /** Peripheral AIPS0 base pointer */
1349 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
1350 /** Peripheral AIPS1 base address */
1351 #define AIPS1_BASE (0x40080000u)
1352 /** Peripheral AIPS1 base pointer */
1353 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
1354 /** Array initializer of AIPS peripheral base pointers */
1355 #define AIPS_BASES { AIPS0, AIPS1 }
1356 
1357 /**
1358  * @}
1359  */ /* end of group AIPS_Peripheral_Access_Layer */
1360 
1361 
1362 /* ----------------------------------------------------------------------------
1363  -- AXBS Peripheral Access Layer
1364  ---------------------------------------------------------------------------- */
1365 
1366 /**
1367  * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
1368  * @{
1369  */
1370 
1371 /** AXBS - Register Layout Typedef */
1372 typedef struct {
1373  struct { /* offset: 0x0, array step: 0x100 */
1374  __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
1375  uint8_t RESERVED_0[12];
1376  __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
1377  uint8_t RESERVED_1[236];
1378  } SLAVE[5];
1379  uint8_t RESERVED_0[768];
1380  __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
1381  uint8_t RESERVED_1[252];
1382  __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
1383  uint8_t RESERVED_2[252];
1384  __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
1385  uint8_t RESERVED_3[252];
1386  __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
1387  uint8_t RESERVED_4[252];
1388  __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
1389  uint8_t RESERVED_5[252];
1390  __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
1391 } AXBS_Type;
1392 
1393 /* ----------------------------------------------------------------------------
1394  -- AXBS Register Masks
1395  ---------------------------------------------------------------------------- */
1396 
1397 /**
1398  * @addtogroup AXBS_Register_Masks AXBS Register Masks
1399  * @{
1400  */
1401 
1402 /* PRS Bit Fields */
1403 #define AXBS_PRS_M0_MASK 0x7u
1404 #define AXBS_PRS_M0_SHIFT 0
1405 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
1406 #define AXBS_PRS_M1_MASK 0x70u
1407 #define AXBS_PRS_M1_SHIFT 4
1408 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
1409 #define AXBS_PRS_M2_MASK 0x700u
1410 #define AXBS_PRS_M2_SHIFT 8
1411 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
1412 #define AXBS_PRS_M3_MASK 0x7000u
1413 #define AXBS_PRS_M3_SHIFT 12
1414 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
1415 #define AXBS_PRS_M4_MASK 0x70000u
1416 #define AXBS_PRS_M4_SHIFT 16
1417 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
1418 #define AXBS_PRS_M5_MASK 0x700000u
1419 #define AXBS_PRS_M5_SHIFT 20
1420 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
1421 /* CRS Bit Fields */
1422 #define AXBS_CRS_PARK_MASK 0x7u
1423 #define AXBS_CRS_PARK_SHIFT 0
1424 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
1425 #define AXBS_CRS_PCTL_MASK 0x30u
1426 #define AXBS_CRS_PCTL_SHIFT 4
1427 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
1428 #define AXBS_CRS_ARB_MASK 0x300u
1429 #define AXBS_CRS_ARB_SHIFT 8
1430 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
1431 #define AXBS_CRS_HLP_MASK 0x40000000u
1432 #define AXBS_CRS_HLP_SHIFT 30
1433 #define AXBS_CRS_RO_MASK 0x80000000u
1434 #define AXBS_CRS_RO_SHIFT 31
1435 /* MGPCR0 Bit Fields */
1436 #define AXBS_MGPCR0_AULB_MASK 0x7u
1437 #define AXBS_MGPCR0_AULB_SHIFT 0
1438 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
1439 /* MGPCR1 Bit Fields */
1440 #define AXBS_MGPCR1_AULB_MASK 0x7u
1441 #define AXBS_MGPCR1_AULB_SHIFT 0
1442 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
1443 /* MGPCR2 Bit Fields */
1444 #define AXBS_MGPCR2_AULB_MASK 0x7u
1445 #define AXBS_MGPCR2_AULB_SHIFT 0
1446 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
1447 /* MGPCR3 Bit Fields */
1448 #define AXBS_MGPCR3_AULB_MASK 0x7u
1449 #define AXBS_MGPCR3_AULB_SHIFT 0
1450 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
1451 /* MGPCR4 Bit Fields */
1452 #define AXBS_MGPCR4_AULB_MASK 0x7u
1453 #define AXBS_MGPCR4_AULB_SHIFT 0
1454 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
1455 /* MGPCR5 Bit Fields */
1456 #define AXBS_MGPCR5_AULB_MASK 0x7u
1457 #define AXBS_MGPCR5_AULB_SHIFT 0
1458 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
1459 
1460 /**
1461  * @}
1462  */ /* end of group AXBS_Register_Masks */
1463 
1464 
1465 /* AXBS - Peripheral instance base addresses */
1466 /** Peripheral AXBS base address */
1467 #define AXBS_BASE (0x40004000u)
1468 /** Peripheral AXBS base pointer */
1469 #define AXBS ((AXBS_Type *)AXBS_BASE)
1470 /** Array initializer of AXBS peripheral base pointers */
1471 #define AXBS_BASES { AXBS }
1472 
1473 /**
1474  * @}
1475  */ /* end of group AXBS_Peripheral_Access_Layer */
1476 
1477 
1478 /* ----------------------------------------------------------------------------
1479  -- CAN Peripheral Access Layer
1480  ---------------------------------------------------------------------------- */
1481 
1482 /**
1483  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1484  * @{
1485  */
1486 
1487 /** CAN - Register Layout Typedef */
1488 typedef struct {
1489  __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
1490  __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
1491  __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
1492  uint8_t RESERVED_0[4];
1493  __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
1494  __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
1495  __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
1496  __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
1497  __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
1498  uint8_t RESERVED_1[4];
1499  __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
1500  uint8_t RESERVED_2[4];
1501  __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
1502  __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
1503  __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
1504  uint8_t RESERVED_3[8];
1505  __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
1506  __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
1507  __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
1508  uint8_t RESERVED_4[48];
1509  struct { /* offset: 0x80, array step: 0x10 */
1510  __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
1511  __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
1512  __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
1513  __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
1514  } MB[16];
1515  uint8_t RESERVED_5[1792];
1516  __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
1517 } CAN_Type;
1518 
1519 /* ----------------------------------------------------------------------------
1520  -- CAN Register Masks
1521  ---------------------------------------------------------------------------- */
1522 
1523 /**
1524  * @addtogroup CAN_Register_Masks CAN Register Masks
1525  * @{
1526  */
1527 
1528 /* MCR Bit Fields */
1529 #define CAN_MCR_MAXMB_MASK 0x7Fu
1530 #define CAN_MCR_MAXMB_SHIFT 0
1531 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
1532 #define CAN_MCR_IDAM_MASK 0x300u
1533 #define CAN_MCR_IDAM_SHIFT 8
1534 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
1535 #define CAN_MCR_AEN_MASK 0x1000u
1536 #define CAN_MCR_AEN_SHIFT 12
1537 #define CAN_MCR_LPRIOEN_MASK 0x2000u
1538 #define CAN_MCR_LPRIOEN_SHIFT 13
1539 #define CAN_MCR_IRMQ_MASK 0x10000u
1540 #define CAN_MCR_IRMQ_SHIFT 16
1541 #define CAN_MCR_SRXDIS_MASK 0x20000u
1542 #define CAN_MCR_SRXDIS_SHIFT 17
1543 #define CAN_MCR_WAKSRC_MASK 0x80000u
1544 #define CAN_MCR_WAKSRC_SHIFT 19
1545 #define CAN_MCR_LPMACK_MASK 0x100000u
1546 #define CAN_MCR_LPMACK_SHIFT 20
1547 #define CAN_MCR_WRNEN_MASK 0x200000u
1548 #define CAN_MCR_WRNEN_SHIFT 21
1549 #define CAN_MCR_SLFWAK_MASK 0x400000u
1550 #define CAN_MCR_SLFWAK_SHIFT 22
1551 #define CAN_MCR_SUPV_MASK 0x800000u
1552 #define CAN_MCR_SUPV_SHIFT 23
1553 #define CAN_MCR_FRZACK_MASK 0x1000000u
1554 #define CAN_MCR_FRZACK_SHIFT 24
1555 #define CAN_MCR_SOFTRST_MASK 0x2000000u
1556 #define CAN_MCR_SOFTRST_SHIFT 25
1557 #define CAN_MCR_WAKMSK_MASK 0x4000000u
1558 #define CAN_MCR_WAKMSK_SHIFT 26
1559 #define CAN_MCR_NOTRDY_MASK 0x8000000u
1560 #define CAN_MCR_NOTRDY_SHIFT 27
1561 #define CAN_MCR_HALT_MASK 0x10000000u
1562 #define CAN_MCR_HALT_SHIFT 28
1563 #define CAN_MCR_RFEN_MASK 0x20000000u
1564 #define CAN_MCR_RFEN_SHIFT 29
1565 #define CAN_MCR_FRZ_MASK 0x40000000u
1566 #define CAN_MCR_FRZ_SHIFT 30
1567 #define CAN_MCR_MDIS_MASK 0x80000000u
1568 #define CAN_MCR_MDIS_SHIFT 31
1569 /* CTRL1 Bit Fields */
1570 #define CAN_CTRL1_PROPSEG_MASK 0x7u
1571 #define CAN_CTRL1_PROPSEG_SHIFT 0
1572 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
1573 #define CAN_CTRL1_LOM_MASK 0x8u
1574 #define CAN_CTRL1_LOM_SHIFT 3
1575 #define CAN_CTRL1_LBUF_MASK 0x10u
1576 #define CAN_CTRL1_LBUF_SHIFT 4
1577 #define CAN_CTRL1_TSYN_MASK 0x20u
1578 #define CAN_CTRL1_TSYN_SHIFT 5
1579 #define CAN_CTRL1_BOFFREC_MASK 0x40u
1580 #define CAN_CTRL1_BOFFREC_SHIFT 6
1581 #define CAN_CTRL1_SMP_MASK 0x80u
1582 #define CAN_CTRL1_SMP_SHIFT 7
1583 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
1584 #define CAN_CTRL1_RWRNMSK_SHIFT 10
1585 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
1586 #define CAN_CTRL1_TWRNMSK_SHIFT 11
1587 #define CAN_CTRL1_LPB_MASK 0x1000u
1588 #define CAN_CTRL1_LPB_SHIFT 12
1589 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1590 #define CAN_CTRL1_CLKSRC_SHIFT 13
1591 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1592 #define CAN_CTRL1_ERRMSK_SHIFT 14
1593 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1594 #define CAN_CTRL1_BOFFMSK_SHIFT 15
1595 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1596 #define CAN_CTRL1_PSEG2_SHIFT 16
1597 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1598 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1599 #define CAN_CTRL1_PSEG1_SHIFT 19
1600 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1601 #define CAN_CTRL1_RJW_MASK 0xC00000u
1602 #define CAN_CTRL1_RJW_SHIFT 22
1603 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1604 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
1605 #define CAN_CTRL1_PRESDIV_SHIFT 24
1606 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
1607 /* TIMER Bit Fields */
1608 #define CAN_TIMER_TIMER_MASK 0xFFFFu
1609 #define CAN_TIMER_TIMER_SHIFT 0
1610 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
1611 /* RXMGMASK Bit Fields */
1612 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
1613 #define CAN_RXMGMASK_MG_SHIFT 0
1614 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
1615 /* RX14MASK Bit Fields */
1616 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
1617 #define CAN_RX14MASK_RX14M_SHIFT 0
1618 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
1619 /* RX15MASK Bit Fields */
1620 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
1621 #define CAN_RX15MASK_RX15M_SHIFT 0
1622 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
1623 /* ECR Bit Fields */
1624 #define CAN_ECR_TXERRCNT_MASK 0xFFu
1625 #define CAN_ECR_TXERRCNT_SHIFT 0
1626 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
1627 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
1628 #define CAN_ECR_RXERRCNT_SHIFT 8
1629 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
1630 /* ESR1 Bit Fields */
1631 #define CAN_ESR1_WAKINT_MASK 0x1u
1632 #define CAN_ESR1_WAKINT_SHIFT 0
1633 #define CAN_ESR1_ERRINT_MASK 0x2u
1634 #define CAN_ESR1_ERRINT_SHIFT 1
1635 #define CAN_ESR1_BOFFINT_MASK 0x4u
1636 #define CAN_ESR1_BOFFINT_SHIFT 2
1637 #define CAN_ESR1_RX_MASK 0x8u
1638 #define CAN_ESR1_RX_SHIFT 3
1639 #define CAN_ESR1_FLTCONF_MASK 0x30u
1640 #define CAN_ESR1_FLTCONF_SHIFT 4
1641 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
1642 #define CAN_ESR1_TX_MASK 0x40u
1643 #define CAN_ESR1_TX_SHIFT 6
1644 #define CAN_ESR1_IDLE_MASK 0x80u
1645 #define CAN_ESR1_IDLE_SHIFT 7
1646 #define CAN_ESR1_RXWRN_MASK 0x100u
1647 #define CAN_ESR1_RXWRN_SHIFT 8
1648 #define CAN_ESR1_TXWRN_MASK 0x200u
1649 #define CAN_ESR1_TXWRN_SHIFT 9
1650 #define CAN_ESR1_STFERR_MASK 0x400u
1651 #define CAN_ESR1_STFERR_SHIFT 10
1652 #define CAN_ESR1_FRMERR_MASK 0x800u
1653 #define CAN_ESR1_FRMERR_SHIFT 11
1654 #define CAN_ESR1_CRCERR_MASK 0x1000u
1655 #define CAN_ESR1_CRCERR_SHIFT 12
1656 #define CAN_ESR1_ACKERR_MASK 0x2000u
1657 #define CAN_ESR1_ACKERR_SHIFT 13
1658 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
1659 #define CAN_ESR1_BIT0ERR_SHIFT 14
1660 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
1661 #define CAN_ESR1_BIT1ERR_SHIFT 15
1662 #define CAN_ESR1_RWRNINT_MASK 0x10000u
1663 #define CAN_ESR1_RWRNINT_SHIFT 16
1664 #define CAN_ESR1_TWRNINT_MASK 0x20000u
1665 #define CAN_ESR1_TWRNINT_SHIFT 17
1666 #define CAN_ESR1_SYNCH_MASK 0x40000u
1667 #define CAN_ESR1_SYNCH_SHIFT 18
1668 /* IMASK1 Bit Fields */
1669 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
1670 #define CAN_IMASK1_BUFLM_SHIFT 0
1671 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
1672 /* IFLAG1 Bit Fields */
1673 #define CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu
1674 #define CAN_IFLAG1_BUF4TO0I_SHIFT 0
1675 #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
1676 #define CAN_IFLAG1_BUF5I_MASK 0x20u
1677 #define CAN_IFLAG1_BUF5I_SHIFT 5
1678 #define CAN_IFLAG1_BUF6I_MASK 0x40u
1679 #define CAN_IFLAG1_BUF6I_SHIFT 6
1680 #define CAN_IFLAG1_BUF7I_MASK 0x80u
1681 #define CAN_IFLAG1_BUF7I_SHIFT 7
1682 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
1683 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
1684 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
1685 /* CTRL2 Bit Fields */
1686 #define CAN_CTRL2_EACEN_MASK 0x10000u
1687 #define CAN_CTRL2_EACEN_SHIFT 16
1688 #define CAN_CTRL2_RRS_MASK 0x20000u
1689 #define CAN_CTRL2_RRS_SHIFT 17
1690 #define CAN_CTRL2_MRP_MASK 0x40000u
1691 #define CAN_CTRL2_MRP_SHIFT 18
1692 #define CAN_CTRL2_TASD_MASK 0xF80000u
1693 #define CAN_CTRL2_TASD_SHIFT 19
1694 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
1695 #define CAN_CTRL2_RFFN_MASK 0xF000000u
1696 #define CAN_CTRL2_RFFN_SHIFT 24
1697 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
1698 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
1699 #define CAN_CTRL2_WRMFRZ_SHIFT 28
1700 /* ESR2 Bit Fields */
1701 #define CAN_ESR2_IMB_MASK 0x2000u
1702 #define CAN_ESR2_IMB_SHIFT 13
1703 #define CAN_ESR2_VPS_MASK 0x4000u
1704 #define CAN_ESR2_VPS_SHIFT 14
1705 #define CAN_ESR2_LPTM_MASK 0x7F0000u
1706 #define CAN_ESR2_LPTM_SHIFT 16
1707 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
1708 /* CRCR Bit Fields */
1709 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
1710 #define CAN_CRCR_TXCRC_SHIFT 0
1711 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
1712 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
1713 #define CAN_CRCR_MBCRC_SHIFT 16
1714 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
1715 /* RXFGMASK Bit Fields */
1716 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
1717 #define CAN_RXFGMASK_FGM_SHIFT 0
1718 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
1719 /* RXFIR Bit Fields */
1720 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
1721 #define CAN_RXFIR_IDHIT_SHIFT 0
1722 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
1723 /* CS Bit Fields */
1724 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
1725 #define CAN_CS_TIME_STAMP_SHIFT 0
1726 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
1727 #define CAN_CS_DLC_MASK 0xF0000u
1728 #define CAN_CS_DLC_SHIFT 16
1729 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
1730 #define CAN_CS_RTR_MASK 0x100000u
1731 #define CAN_CS_RTR_SHIFT 20
1732 #define CAN_CS_IDE_MASK 0x200000u
1733 #define CAN_CS_IDE_SHIFT 21
1734 #define CAN_CS_SRR_MASK 0x400000u
1735 #define CAN_CS_SRR_SHIFT 22
1736 #define CAN_CS_CODE_MASK 0xF000000u
1737 #define CAN_CS_CODE_SHIFT 24
1738 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
1739 /* ID Bit Fields */
1740 #define CAN_ID_EXT_MASK 0x3FFFFu
1741 #define CAN_ID_EXT_SHIFT 0
1742 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
1743 #define CAN_ID_STD_MASK 0x1FFC0000u
1744 #define CAN_ID_STD_SHIFT 18
1745 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
1746 #define CAN_ID_PRIO_MASK 0xE0000000u
1747 #define CAN_ID_PRIO_SHIFT 29
1748 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
1749 /* WORD0 Bit Fields */
1750 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
1751 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
1752 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
1753 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
1754 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
1755 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
1756 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
1757 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
1758 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
1759 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
1760 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
1761 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
1762 /* WORD1 Bit Fields */
1763 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
1764 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
1765 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
1766 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
1767 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
1768 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
1769 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
1770 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
1771 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
1772 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
1773 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
1774 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
1775 /* RXIMR Bit Fields */
1776 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
1777 #define CAN_RXIMR_MI_SHIFT 0
1778 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
1779 
1780 /**
1781  * @}
1782  */ /* end of group CAN_Register_Masks */
1783 
1784 
1785 /* CAN - Peripheral instance base addresses */
1786 /** Peripheral CAN0 base address */
1787 #define CAN0_BASE (0x40024000u)
1788 /** Peripheral CAN0 base pointer */
1789 #define CAN0 ((CAN_Type *)CAN0_BASE)
1790 /** Peripheral CAN1 base address */
1791 #define CAN1_BASE (0x400A4000u)
1792 /** Peripheral CAN1 base pointer */
1793 #define CAN1 ((CAN_Type *)CAN1_BASE)
1794 /** Array initializer of CAN peripheral base pointers */
1795 #define CAN_BASES { CAN0, CAN1 }
1796 
1797 /**
1798  * @}
1799  */ /* end of group CAN_Peripheral_Access_Layer */
1800 
1801 
1802 /* ----------------------------------------------------------------------------
1803  -- CAU Peripheral Access Layer
1804  ---------------------------------------------------------------------------- */
1805 
1806 /**
1807  * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
1808  * @{
1809  */
1810 
1811 /** CAU - Register Layout Typedef */
1812 typedef struct {
1813  __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
1814  uint8_t RESERVED_0[2048];
1815  __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
1816  __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
1817  __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
1818  uint8_t RESERVED_1[20];
1819  __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
1820  __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
1821  __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
1822  uint8_t RESERVED_2[20];
1823  __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
1824  __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
1825  __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
1826  uint8_t RESERVED_3[20];
1827  __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
1828  __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
1829  __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
1830  uint8_t RESERVED_4[84];
1831  __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
1832  __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
1833  __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
1834  uint8_t RESERVED_5[20];
1835  __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
1836  __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
1837  __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
1838  uint8_t RESERVED_6[276];
1839  __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
1840  __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
1841  __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
1842  uint8_t RESERVED_7[20];
1843  __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
1844  __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
1845  __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
1846 } CAU_Type;
1847 
1848 /* ----------------------------------------------------------------------------
1849  -- CAU Register Masks
1850  ---------------------------------------------------------------------------- */
1851 
1852 /**
1853  * @addtogroup CAU_Register_Masks CAU Register Masks
1854  * @{
1855  */
1856 
1857 /* LDR_CASR Bit Fields */
1858 #define CAU_LDR_CASR_IC_MASK 0x1u
1859 #define CAU_LDR_CASR_IC_SHIFT 0
1860 #define CAU_LDR_CASR_DPE_MASK 0x2u
1861 #define CAU_LDR_CASR_DPE_SHIFT 1
1862 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
1863 #define CAU_LDR_CASR_VER_SHIFT 28
1864 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
1865 /* STR_CASR Bit Fields */
1866 #define CAU_STR_CASR_IC_MASK 0x1u
1867 #define CAU_STR_CASR_IC_SHIFT 0
1868 #define CAU_STR_CASR_DPE_MASK 0x2u
1869 #define CAU_STR_CASR_DPE_SHIFT 1
1870 #define CAU_STR_CASR_VER_MASK 0xF0000000u
1871 #define CAU_STR_CASR_VER_SHIFT 28
1872 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
1873 /* ADR_CASR Bit Fields */
1874 #define CAU_ADR_CASR_IC_MASK 0x1u
1875 #define CAU_ADR_CASR_IC_SHIFT 0
1876 #define CAU_ADR_CASR_DPE_MASK 0x2u
1877 #define CAU_ADR_CASR_DPE_SHIFT 1
1878 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
1879 #define CAU_ADR_CASR_VER_SHIFT 28
1880 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
1881 /* RADR_CASR Bit Fields */
1882 #define CAU_RADR_CASR_IC_MASK 0x1u
1883 #define CAU_RADR_CASR_IC_SHIFT 0
1884 #define CAU_RADR_CASR_DPE_MASK 0x2u
1885 #define CAU_RADR_CASR_DPE_SHIFT 1
1886 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
1887 #define CAU_RADR_CASR_VER_SHIFT 28
1888 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
1889 /* XOR_CASR Bit Fields */
1890 #define CAU_XOR_CASR_IC_MASK 0x1u
1891 #define CAU_XOR_CASR_IC_SHIFT 0
1892 #define CAU_XOR_CASR_DPE_MASK 0x2u
1893 #define CAU_XOR_CASR_DPE_SHIFT 1
1894 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
1895 #define CAU_XOR_CASR_VER_SHIFT 28
1896 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
1897 /* ROTL_CASR Bit Fields */
1898 #define CAU_ROTL_CASR_IC_MASK 0x1u
1899 #define CAU_ROTL_CASR_IC_SHIFT 0
1900 #define CAU_ROTL_CASR_DPE_MASK 0x2u
1901 #define CAU_ROTL_CASR_DPE_SHIFT 1
1902 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
1903 #define CAU_ROTL_CASR_VER_SHIFT 28
1904 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
1905 /* AESC_CASR Bit Fields */
1906 #define CAU_AESC_CASR_IC_MASK 0x1u
1907 #define CAU_AESC_CASR_IC_SHIFT 0
1908 #define CAU_AESC_CASR_DPE_MASK 0x2u
1909 #define CAU_AESC_CASR_DPE_SHIFT 1
1910 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
1911 #define CAU_AESC_CASR_VER_SHIFT 28
1912 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
1913 /* AESIC_CASR Bit Fields */
1914 #define CAU_AESIC_CASR_IC_MASK 0x1u
1915 #define CAU_AESIC_CASR_IC_SHIFT 0
1916 #define CAU_AESIC_CASR_DPE_MASK 0x2u
1917 #define CAU_AESIC_CASR_DPE_SHIFT 1
1918 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
1919 #define CAU_AESIC_CASR_VER_SHIFT 28
1920 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
1921 
1922 /**
1923  * @}
1924  */ /* end of group CAU_Register_Masks */
1925 
1926 
1927 /* CAU - Peripheral instance base addresses */
1928 /** Peripheral CAU base address */
1929 #define CAU_BASE (0xE0081000u)
1930 /** Peripheral CAU base pointer */
1931 #define CAU ((CAU_Type *)CAU_BASE)
1932 /** Array initializer of CAU peripheral base pointers */
1933 #define CAU_BASES { CAU }
1934 
1935 /**
1936  * @}
1937  */ /* end of group CAU_Peripheral_Access_Layer */
1938 
1939 
1940 /* ----------------------------------------------------------------------------
1941  -- CMP Peripheral Access Layer
1942  ---------------------------------------------------------------------------- */
1943 
1944 /**
1945  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
1946  * @{
1947  */
1948 
1949 /** CMP - Register Layout Typedef */
1950 typedef struct {
1951  __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
1952  __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
1953  __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
1954  __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
1955  __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
1956  __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
1957 } CMP_Type;
1958 
1959 /* ----------------------------------------------------------------------------
1960  -- CMP Register Masks
1961  ---------------------------------------------------------------------------- */
1962 
1963 /**
1964  * @addtogroup CMP_Register_Masks CMP Register Masks
1965  * @{
1966  */
1967 
1968 /* CR0 Bit Fields */
1969 #define CMP_CR0_HYSTCTR_MASK 0x3u
1970 #define CMP_CR0_HYSTCTR_SHIFT 0
1971 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
1972 #define CMP_CR0_FILTER_CNT_MASK 0x70u
1973 #define CMP_CR0_FILTER_CNT_SHIFT 4
1974 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
1975 /* CR1 Bit Fields */
1976 #define CMP_CR1_EN_MASK 0x1u
1977 #define CMP_CR1_EN_SHIFT 0
1978 #define CMP_CR1_OPE_MASK 0x2u
1979 #define CMP_CR1_OPE_SHIFT 1
1980 #define CMP_CR1_COS_MASK 0x4u
1981 #define CMP_CR1_COS_SHIFT 2
1982 #define CMP_CR1_INV_MASK 0x8u
1983 #define CMP_CR1_INV_SHIFT 3
1984 #define CMP_CR1_PMODE_MASK 0x10u
1985 #define CMP_CR1_PMODE_SHIFT 4
1986 #define CMP_CR1_WE_MASK 0x40u
1987 #define CMP_CR1_WE_SHIFT 6
1988 #define CMP_CR1_SE_MASK 0x80u
1989 #define CMP_CR1_SE_SHIFT 7
1990 /* FPR Bit Fields */
1991 #define CMP_FPR_FILT_PER_MASK 0xFFu
1992 #define CMP_FPR_FILT_PER_SHIFT 0
1993 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
1994 /* SCR Bit Fields */
1995 #define CMP_SCR_COUT_MASK 0x1u
1996 #define CMP_SCR_COUT_SHIFT 0
1997 #define CMP_SCR_CFF_MASK 0x2u
1998 #define CMP_SCR_CFF_SHIFT 1
1999 #define CMP_SCR_CFR_MASK 0x4u
2000 #define CMP_SCR_CFR_SHIFT 2
2001 #define CMP_SCR_IEF_MASK 0x8u
2002 #define CMP_SCR_IEF_SHIFT 3
2003 #define CMP_SCR_IER_MASK 0x10u
2004 #define CMP_SCR_IER_SHIFT 4
2005 #define CMP_SCR_DMAEN_MASK 0x40u
2006 #define CMP_SCR_DMAEN_SHIFT 6
2007 /* DACCR Bit Fields */
2008 #define CMP_DACCR_VOSEL_MASK 0x3Fu
2009 #define CMP_DACCR_VOSEL_SHIFT 0
2010 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
2011 #define CMP_DACCR_VRSEL_MASK 0x40u
2012 #define CMP_DACCR_VRSEL_SHIFT 6
2013 #define CMP_DACCR_DACEN_MASK 0x80u
2014 #define CMP_DACCR_DACEN_SHIFT 7
2015 /* MUXCR Bit Fields */
2016 #define CMP_MUXCR_MSEL_MASK 0x7u
2017 #define CMP_MUXCR_MSEL_SHIFT 0
2018 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
2019 #define CMP_MUXCR_PSEL_MASK 0x38u
2020 #define CMP_MUXCR_PSEL_SHIFT 3
2021 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
2022 #define CMP_MUXCR_PSTM_MASK 0x40u
2023 #define CMP_MUXCR_PSTM_SHIFT 6
2024 
2025 /**
2026  * @}
2027  */ /* end of group CMP_Register_Masks */
2028 
2029 
2030 /* CMP - Peripheral instance base addresses */
2031 /** Peripheral CMP0 base address */
2032 #define CMP0_BASE (0x40073000u)
2033 /** Peripheral CMP0 base pointer */
2034 #define CMP0 ((CMP_Type *)CMP0_BASE)
2035 /** Peripheral CMP1 base address */
2036 #define CMP1_BASE (0x40073008u)
2037 /** Peripheral CMP1 base pointer */
2038 #define CMP1 ((CMP_Type *)CMP1_BASE)
2039 /** Peripheral CMP2 base address */
2040 #define CMP2_BASE (0x40073010u)
2041 /** Peripheral CMP2 base pointer */
2042 #define CMP2 ((CMP_Type *)CMP2_BASE)
2043 /** Array initializer of CMP peripheral base pointers */
2044 #define CMP_BASES { CMP0, CMP1, CMP2 }
2045 
2046 /**
2047  * @}
2048  */ /* end of group CMP_Peripheral_Access_Layer */
2049 
2050 
2051 /* ----------------------------------------------------------------------------
2052  -- CMT Peripheral Access Layer
2053  ---------------------------------------------------------------------------- */
2054 
2055 /**
2056  * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
2057  * @{
2058  */
2059 
2060 /** CMT - Register Layout Typedef */
2061 typedef struct {
2062  __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
2063  __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
2064  __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
2065  __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
2066  __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
2067  __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
2068  __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
2069  __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
2070  __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
2071  __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
2072  __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
2073  __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
2074 } CMT_Type;
2075 
2076 /* ----------------------------------------------------------------------------
2077  -- CMT Register Masks
2078  ---------------------------------------------------------------------------- */
2079 
2080 /**
2081  * @addtogroup CMT_Register_Masks CMT Register Masks
2082  * @{
2083  */
2084 
2085 /* CGH1 Bit Fields */
2086 #define CMT_CGH1_PH_MASK 0xFFu
2087 #define CMT_CGH1_PH_SHIFT 0
2088 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
2089 /* CGL1 Bit Fields */
2090 #define CMT_CGL1_PL_MASK 0xFFu
2091 #define CMT_CGL1_PL_SHIFT 0
2092 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
2093 /* CGH2 Bit Fields */
2094 #define CMT_CGH2_SH_MASK 0xFFu
2095 #define CMT_CGH2_SH_SHIFT 0
2096 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
2097 /* CGL2 Bit Fields */
2098 #define CMT_CGL2_SL_MASK 0xFFu
2099 #define CMT_CGL2_SL_SHIFT 0
2100 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
2101 /* OC Bit Fields */
2102 #define CMT_OC_IROPEN_MASK 0x20u
2103 #define CMT_OC_IROPEN_SHIFT 5
2104 #define CMT_OC_CMTPOL_MASK 0x40u
2105 #define CMT_OC_CMTPOL_SHIFT 6
2106 #define CMT_OC_IROL_MASK 0x80u
2107 #define CMT_OC_IROL_SHIFT 7
2108 /* MSC Bit Fields */
2109 #define CMT_MSC_MCGEN_MASK 0x1u
2110 #define CMT_MSC_MCGEN_SHIFT 0
2111 #define CMT_MSC_EOCIE_MASK 0x2u
2112 #define CMT_MSC_EOCIE_SHIFT 1
2113 #define CMT_MSC_FSK_MASK 0x4u
2114 #define CMT_MSC_FSK_SHIFT 2
2115 #define CMT_MSC_BASE_MASK 0x8u
2116 #define CMT_MSC_BASE_SHIFT 3
2117 #define CMT_MSC_EXSPC_MASK 0x10u
2118 #define CMT_MSC_EXSPC_SHIFT 4
2119 #define CMT_MSC_CMTDIV_MASK 0x60u
2120 #define CMT_MSC_CMTDIV_SHIFT 5
2121 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
2122 #define CMT_MSC_EOCF_MASK 0x80u
2123 #define CMT_MSC_EOCF_SHIFT 7
2124 /* CMD1 Bit Fields */
2125 #define CMT_CMD1_MB_MASK 0xFFu
2126 #define CMT_CMD1_MB_SHIFT 0
2127 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
2128 /* CMD2 Bit Fields */
2129 #define CMT_CMD2_MB_MASK 0xFFu
2130 #define CMT_CMD2_MB_SHIFT 0
2131 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
2132 /* CMD3 Bit Fields */
2133 #define CMT_CMD3_SB_MASK 0xFFu
2134 #define CMT_CMD3_SB_SHIFT 0
2135 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
2136 /* CMD4 Bit Fields */
2137 #define CMT_CMD4_SB_MASK 0xFFu
2138 #define CMT_CMD4_SB_SHIFT 0
2139 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
2140 /* PPS Bit Fields */
2141 #define CMT_PPS_PPSDIV_MASK 0xFu
2142 #define CMT_PPS_PPSDIV_SHIFT 0
2143 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
2144 /* DMA Bit Fields */
2145 #define CMT_DMA_DMA_MASK 0x1u
2146 #define CMT_DMA_DMA_SHIFT 0
2147 
2148 /**
2149  * @}
2150  */ /* end of group CMT_Register_Masks */
2151 
2152 
2153 /* CMT - Peripheral instance base addresses */
2154 /** Peripheral CMT base address */
2155 #define CMT_BASE (0x40062000u)
2156 /** Peripheral CMT base pointer */
2157 #define CMT ((CMT_Type *)CMT_BASE)
2158 /** Array initializer of CMT peripheral base pointers */
2159 #define CMT_BASES { CMT }
2160 
2161 /**
2162  * @}
2163  */ /* end of group CMT_Peripheral_Access_Layer */
2164 
2165 
2166 /* ----------------------------------------------------------------------------
2167  -- CRC Peripheral Access Layer
2168  ---------------------------------------------------------------------------- */
2169 
2170 /**
2171  * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2172  * @{
2173  */
2174 
2175 /** CRC - Register Layout Typedef */
2176 typedef struct {
2177  union { /* offset: 0x0 */
2178  struct { /* offset: 0x0 */
2179  __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
2180  __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
2181  } ACCESS16BIT;
2182  __IO uint32_t CRC; /**< CRC Data register, offset: 0x0 */
2183  struct { /* offset: 0x0 */
2184  __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
2185  __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
2186  __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
2187  __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
2188  } ACCESS8BIT;
2189  };
2190  union { /* offset: 0x4 */
2191  struct { /* offset: 0x4 */
2192  __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
2193  __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
2194  } GPOLY_ACCESS16BIT;
2195  __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
2196  struct { /* offset: 0x4 */
2197  __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
2198  __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
2199  __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
2200  __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
2201  } GPOLY_ACCESS8BIT;
2202  };
2203  union { /* offset: 0x8 */
2204  __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
2205  struct { /* offset: 0x8 */
2206  uint8_t RESERVED_0[3];
2207  __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
2208  } CTRL_ACCESS8BIT;
2209  };
2210 } CRC_Type;
2211 
2212 /* ----------------------------------------------------------------------------
2213  -- CRC Register Masks
2214  ---------------------------------------------------------------------------- */
2215 
2216 /**
2217  * @addtogroup CRC_Register_Masks CRC Register Masks
2218  * @{
2219  */
2220 
2221 /* CRCL Bit Fields */
2222 #define CRC_CRCL_CRCL_MASK 0xFFFFu
2223 #define CRC_CRCL_CRCL_SHIFT 0
2224 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
2225 /* CRCH Bit Fields */
2226 #define CRC_CRCH_CRCH_MASK 0xFFFFu
2227 #define CRC_CRCH_CRCH_SHIFT 0
2228 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
2229 /* CRC Bit Fields */
2230 #define CRC_CRC_LL_MASK 0xFFu
2231 #define CRC_CRC_LL_SHIFT 0
2232 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
2233 #define CRC_CRC_LU_MASK 0xFF00u
2234 #define CRC_CRC_LU_SHIFT 8
2235 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
2236 #define CRC_CRC_HL_MASK 0xFF0000u
2237 #define CRC_CRC_HL_SHIFT 16
2238 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
2239 #define CRC_CRC_HU_MASK 0xFF000000u
2240 #define CRC_CRC_HU_SHIFT 24
2241 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
2242 /* CRCLL Bit Fields */
2243 #define CRC_CRCLL_CRCLL_MASK 0xFFu
2244 #define CRC_CRCLL_CRCLL_SHIFT 0
2245 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
2246 /* CRCLU Bit Fields */
2247 #define CRC_CRCLU_CRCLU_MASK 0xFFu
2248 #define CRC_CRCLU_CRCLU_SHIFT 0
2249 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
2250 /* CRCHL Bit Fields */
2251 #define CRC_CRCHL_CRCHL_MASK 0xFFu
2252 #define CRC_CRCHL_CRCHL_SHIFT 0
2253 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
2254 /* CRCHU Bit Fields */
2255 #define CRC_CRCHU_CRCHU_MASK 0xFFu
2256 #define CRC_CRCHU_CRCHU_SHIFT 0
2257 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
2258 /* GPOLYL Bit Fields */
2259 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
2260 #define CRC_GPOLYL_GPOLYL_SHIFT 0
2261 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
2262 /* GPOLYH Bit Fields */
2263 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
2264 #define CRC_GPOLYH_GPOLYH_SHIFT 0
2265 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
2266 /* GPOLY Bit Fields */
2267 #define CRC_GPOLY_LOW_MASK 0xFFFFu
2268 #define CRC_GPOLY_LOW_SHIFT 0
2269 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
2270 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
2271 #define CRC_GPOLY_HIGH_SHIFT 16
2272 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
2273 /* GPOLYLL Bit Fields */
2274 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
2275 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
2276 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
2277 /* GPOLYLU Bit Fields */
2278 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
2279 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
2280 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
2281 /* GPOLYHL Bit Fields */
2282 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
2283 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
2284 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
2285 /* GPOLYHU Bit Fields */
2286 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
2287 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
2288 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
2289 /* CTRL Bit Fields */
2290 #define CRC_CTRL_TCRC_MASK 0x1000000u
2291 #define CRC_CTRL_TCRC_SHIFT 24
2292 #define CRC_CTRL_WAS_MASK 0x2000000u
2293 #define CRC_CTRL_WAS_SHIFT 25
2294 #define CRC_CTRL_FXOR_MASK 0x4000000u
2295 #define CRC_CTRL_FXOR_SHIFT 26
2296 #define CRC_CTRL_TOTR_MASK 0x30000000u
2297 #define CRC_CTRL_TOTR_SHIFT 28
2298 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
2299 #define CRC_CTRL_TOT_MASK 0xC0000000u
2300 #define CRC_CTRL_TOT_SHIFT 30
2301 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
2302 /* CTRLHU Bit Fields */
2303 #define CRC_CTRLHU_TCRC_MASK 0x1u
2304 #define CRC_CTRLHU_TCRC_SHIFT 0
2305 #define CRC_CTRLHU_WAS_MASK 0x2u
2306 #define CRC_CTRLHU_WAS_SHIFT 1
2307 #define CRC_CTRLHU_FXOR_MASK 0x4u
2308 #define CRC_CTRLHU_FXOR_SHIFT 2
2309 #define CRC_CTRLHU_TOTR_MASK 0x30u
2310 #define CRC_CTRLHU_TOTR_SHIFT 4
2311 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
2312 #define CRC_CTRLHU_TOT_MASK 0xC0u
2313 #define CRC_CTRLHU_TOT_SHIFT 6
2314 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
2315 
2316 /**
2317  * @}
2318  */ /* end of group CRC_Register_Masks */
2319 
2320 
2321 /* CRC - Peripheral instance base addresses */
2322 /** Peripheral CRC base address */
2323 #define CRC_BASE (0x40032000u)
2324 /** Peripheral CRC base pointer */
2325 #define CRC0 ((CRC_Type *)CRC_BASE)
2326 /** Array initializer of CRC peripheral base pointers */
2327 #define CRC_BASES { CRC0 }
2328 
2329 /**
2330  * @}
2331  */ /* end of group CRC_Peripheral_Access_Layer */
2332 
2333 
2334 /* ----------------------------------------------------------------------------
2335  -- DAC Peripheral Access Layer
2336  ---------------------------------------------------------------------------- */
2337 
2338 /**
2339  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2340  * @{
2341  */
2342 
2343 /** DAC - Register Layout Typedef */
2344 typedef struct {
2345  struct { /* offset: 0x0, array step: 0x2 */
2346  __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
2347  __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
2348  } DAT[16];
2349  __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
2350  __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
2351  __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
2352  __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
2353 } DAC_Type;
2354 
2355 /* ----------------------------------------------------------------------------
2356  -- DAC Register Masks
2357  ---------------------------------------------------------------------------- */
2358 
2359 /**
2360  * @addtogroup DAC_Register_Masks DAC Register Masks
2361  * @{
2362  */
2363 
2364 /* DATL Bit Fields */
2365 #define DAC_DATL_DATA0_MASK 0xFFu
2366 #define DAC_DATL_DATA0_SHIFT 0
2367 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
2368 /* DATH Bit Fields */
2369 #define DAC_DATH_DATA1_MASK 0xFu
2370 #define DAC_DATH_DATA1_SHIFT 0
2371 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
2372 /* SR Bit Fields */
2373 #define DAC_SR_DACBFRPBF_MASK 0x1u
2374 #define DAC_SR_DACBFRPBF_SHIFT 0
2375 #define DAC_SR_DACBFRPTF_MASK 0x2u
2376 #define DAC_SR_DACBFRPTF_SHIFT 1
2377 #define DAC_SR_DACBFWMF_MASK 0x4u
2378 #define DAC_SR_DACBFWMF_SHIFT 2
2379 /* C0 Bit Fields */
2380 #define DAC_C0_DACBBIEN_MASK 0x1u
2381 #define DAC_C0_DACBBIEN_SHIFT 0
2382 #define DAC_C0_DACBTIEN_MASK 0x2u
2383 #define DAC_C0_DACBTIEN_SHIFT 1
2384 #define DAC_C0_DACBWIEN_MASK 0x4u
2385 #define DAC_C0_DACBWIEN_SHIFT 2
2386 #define DAC_C0_LPEN_MASK 0x8u
2387 #define DAC_C0_LPEN_SHIFT 3
2388 #define DAC_C0_DACSWTRG_MASK 0x10u
2389 #define DAC_C0_DACSWTRG_SHIFT 4
2390 #define DAC_C0_DACTRGSEL_MASK 0x20u
2391 #define DAC_C0_DACTRGSEL_SHIFT 5
2392 #define DAC_C0_DACRFS_MASK 0x40u
2393 #define DAC_C0_DACRFS_SHIFT 6
2394 #define DAC_C0_DACEN_MASK 0x80u
2395 #define DAC_C0_DACEN_SHIFT 7
2396 /* C1 Bit Fields */
2397 #define DAC_C1_DACBFEN_MASK 0x1u
2398 #define DAC_C1_DACBFEN_SHIFT 0
2399 #define DAC_C1_DACBFMD_MASK 0x6u
2400 #define DAC_C1_DACBFMD_SHIFT 1
2401 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
2402 #define DAC_C1_DACBFWM_MASK 0x18u
2403 #define DAC_C1_DACBFWM_SHIFT 3
2404 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
2405 #define DAC_C1_DMAEN_MASK 0x80u
2406 #define DAC_C1_DMAEN_SHIFT 7
2407 /* C2 Bit Fields */
2408 #define DAC_C2_DACBFUP_MASK 0xFu
2409 #define DAC_C2_DACBFUP_SHIFT 0
2410 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
2411 #define DAC_C2_DACBFRP_MASK 0xF0u
2412 #define DAC_C2_DACBFRP_SHIFT 4
2413 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
2414 
2415 /**
2416  * @}
2417  */ /* end of group DAC_Register_Masks */
2418 
2419 
2420 /* DAC - Peripheral instance base addresses */
2421 /** Peripheral DAC0 base address */
2422 #define DAC0_BASE (0x400CC000u)
2423 /** Peripheral DAC0 base pointer */
2424 #define DAC0 ((DAC_Type *)DAC0_BASE)
2425 /** Peripheral DAC1 base address */
2426 #define DAC1_BASE (0x400CD000u)
2427 /** Peripheral DAC1 base pointer */
2428 #define DAC1 ((DAC_Type *)DAC1_BASE)
2429 /** Array initializer of DAC peripheral base pointers */
2430 #define DAC_BASES { DAC0, DAC1 }
2431 
2432 /**
2433  * @}
2434  */ /* end of group DAC_Peripheral_Access_Layer */
2435 
2436 
2437 /* ----------------------------------------------------------------------------
2438  -- DMA Peripheral Access Layer
2439  ---------------------------------------------------------------------------- */
2440 
2441 /**
2442  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2443  * @{
2444  */
2445 
2446 /** DMA - Register Layout Typedef */
2447 typedef struct {
2448  __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2449  __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
2450  uint8_t RESERVED_0[4];
2451  __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2452  uint8_t RESERVED_1[4];
2453  __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2454  __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2455  __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
2456  __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
2457  __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2458  __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
2459  __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
2460  __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
2461  __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
2462  uint8_t RESERVED_2[4];
2463  __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2464  uint8_t RESERVED_3[4];
2465  __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2466  uint8_t RESERVED_4[4];
2467  __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2468  uint8_t RESERVED_5[200];
2469  __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
2470  __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
2471  __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
2472  __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
2473  __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
2474  __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
2475  __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
2476  __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
2477  __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
2478  __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
2479  __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
2480  __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
2481  __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
2482  __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
2483  __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
2484  __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
2485  uint8_t RESERVED_6[3824];
2486  struct { /* offset: 0x1000, array step: 0x20 */
2487  __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2488  __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2489  __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2490  union { /* offset: 0x1008, array step: 0x20 */
2491  __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
2492  __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
2493  __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
2494  };
2495  __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2496  __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2497  __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2498  union { /* offset: 0x1016, array step: 0x20 */
2499  __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
2500  __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
2501  };
2502  __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
2503  __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2504  union { /* offset: 0x101E, array step: 0x20 */
2505  __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
2506  __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
2507  };
2508  } TCD[16];
2509 } DMA_Type;
2510 
2511 /* ----------------------------------------------------------------------------
2512  -- DMA Register Masks
2513  ---------------------------------------------------------------------------- */
2514 
2515 /**
2516  * @addtogroup DMA_Register_Masks DMA Register Masks
2517  * @{
2518  */
2519 
2520 /* CR Bit Fields */
2521 #define DMA_CR_EDBG_MASK 0x2u
2522 #define DMA_CR_EDBG_SHIFT 1
2523 #define DMA_CR_ERCA_MASK 0x4u
2524 #define DMA_CR_ERCA_SHIFT 2
2525 #define DMA_CR_HOE_MASK 0x10u
2526 #define DMA_CR_HOE_SHIFT 4
2527 #define DMA_CR_HALT_MASK 0x20u
2528 #define DMA_CR_HALT_SHIFT 5
2529 #define DMA_CR_CLM_MASK 0x40u
2530 #define DMA_CR_CLM_SHIFT 6
2531 #define DMA_CR_EMLM_MASK 0x80u
2532 #define DMA_CR_EMLM_SHIFT 7
2533 #define DMA_CR_ECX_MASK 0x10000u
2534 #define DMA_CR_ECX_SHIFT 16
2535 #define DMA_CR_CX_MASK 0x20000u
2536 #define DMA_CR_CX_SHIFT 17
2537 /* ES Bit Fields */
2538 #define DMA_ES_DBE_MASK 0x1u
2539 #define DMA_ES_DBE_SHIFT 0
2540 #define DMA_ES_SBE_MASK 0x2u
2541 #define DMA_ES_SBE_SHIFT 1
2542 #define DMA_ES_SGE_MASK 0x4u
2543 #define DMA_ES_SGE_SHIFT 2
2544 #define DMA_ES_NCE_MASK 0x8u
2545 #define DMA_ES_NCE_SHIFT 3
2546 #define DMA_ES_DOE_MASK 0x10u
2547 #define DMA_ES_DOE_SHIFT 4
2548 #define DMA_ES_DAE_MASK 0x20u
2549 #define DMA_ES_DAE_SHIFT 5
2550 #define DMA_ES_SOE_MASK 0x40u
2551 #define DMA_ES_SOE_SHIFT 6
2552 #define DMA_ES_SAE_MASK 0x80u
2553 #define DMA_ES_SAE_SHIFT 7
2554 #define DMA_ES_ERRCHN_MASK 0xF00u
2555 #define DMA_ES_ERRCHN_SHIFT 8
2556 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
2557 #define DMA_ES_CPE_MASK 0x4000u
2558 #define DMA_ES_CPE_SHIFT 14
2559 #define DMA_ES_ECX_MASK 0x10000u
2560 #define DMA_ES_ECX_SHIFT 16
2561 #define DMA_ES_VLD_MASK 0x80000000u
2562 #define DMA_ES_VLD_SHIFT 31
2563 /* ERQ Bit Fields */
2564 #define DMA_ERQ_ERQ0_MASK 0x1u
2565 #define DMA_ERQ_ERQ0_SHIFT 0
2566 #define DMA_ERQ_ERQ1_MASK 0x2u
2567 #define DMA_ERQ_ERQ1_SHIFT 1
2568 #define DMA_ERQ_ERQ2_MASK 0x4u
2569 #define DMA_ERQ_ERQ2_SHIFT 2
2570 #define DMA_ERQ_ERQ3_MASK 0x8u
2571 #define DMA_ERQ_ERQ3_SHIFT 3
2572 #define DMA_ERQ_ERQ4_MASK 0x10u
2573 #define DMA_ERQ_ERQ4_SHIFT 4
2574 #define DMA_ERQ_ERQ5_MASK 0x20u
2575 #define DMA_ERQ_ERQ5_SHIFT 5
2576 #define DMA_ERQ_ERQ6_MASK 0x40u
2577 #define DMA_ERQ_ERQ6_SHIFT 6
2578 #define DMA_ERQ_ERQ7_MASK 0x80u
2579 #define DMA_ERQ_ERQ7_SHIFT 7
2580 #define DMA_ERQ_ERQ8_MASK 0x100u
2581 #define DMA_ERQ_ERQ8_SHIFT 8
2582 #define DMA_ERQ_ERQ9_MASK 0x200u
2583 #define DMA_ERQ_ERQ9_SHIFT 9
2584 #define DMA_ERQ_ERQ10_MASK 0x400u
2585 #define DMA_ERQ_ERQ10_SHIFT 10
2586 #define DMA_ERQ_ERQ11_MASK 0x800u
2587 #define DMA_ERQ_ERQ11_SHIFT 11
2588 #define DMA_ERQ_ERQ12_MASK 0x1000u
2589 #define DMA_ERQ_ERQ12_SHIFT 12
2590 #define DMA_ERQ_ERQ13_MASK 0x2000u
2591 #define DMA_ERQ_ERQ13_SHIFT 13
2592 #define DMA_ERQ_ERQ14_MASK 0x4000u
2593 #define DMA_ERQ_ERQ14_SHIFT 14
2594 #define DMA_ERQ_ERQ15_MASK 0x8000u
2595 #define DMA_ERQ_ERQ15_SHIFT 15
2596 /* EEI Bit Fields */
2597 #define DMA_EEI_EEI0_MASK 0x1u
2598 #define DMA_EEI_EEI0_SHIFT 0
2599 #define DMA_EEI_EEI1_MASK 0x2u
2600 #define DMA_EEI_EEI1_SHIFT 1
2601 #define DMA_EEI_EEI2_MASK 0x4u
2602 #define DMA_EEI_EEI2_SHIFT 2
2603 #define DMA_EEI_EEI3_MASK 0x8u
2604 #define DMA_EEI_EEI3_SHIFT 3
2605 #define DMA_EEI_EEI4_MASK 0x10u
2606 #define DMA_EEI_EEI4_SHIFT 4
2607 #define DMA_EEI_EEI5_MASK 0x20u
2608 #define DMA_EEI_EEI5_SHIFT 5
2609 #define DMA_EEI_EEI6_MASK 0x40u
2610 #define DMA_EEI_EEI6_SHIFT 6
2611 #define DMA_EEI_EEI7_MASK 0x80u
2612 #define DMA_EEI_EEI7_SHIFT 7
2613 #define DMA_EEI_EEI8_MASK 0x100u
2614 #define DMA_EEI_EEI8_SHIFT 8
2615 #define DMA_EEI_EEI9_MASK 0x200u
2616 #define DMA_EEI_EEI9_SHIFT 9
2617 #define DMA_EEI_EEI10_MASK 0x400u
2618 #define DMA_EEI_EEI10_SHIFT 10
2619 #define DMA_EEI_EEI11_MASK 0x800u
2620 #define DMA_EEI_EEI11_SHIFT 11
2621 #define DMA_EEI_EEI12_MASK 0x1000u
2622 #define DMA_EEI_EEI12_SHIFT 12
2623 #define DMA_EEI_EEI13_MASK 0x2000u
2624 #define DMA_EEI_EEI13_SHIFT 13
2625 #define DMA_EEI_EEI14_MASK 0x4000u
2626 #define DMA_EEI_EEI14_SHIFT 14
2627 #define DMA_EEI_EEI15_MASK 0x8000u
2628 #define DMA_EEI_EEI15_SHIFT 15
2629 /* CEEI Bit Fields */
2630 #define DMA_CEEI_CEEI_MASK 0xFu
2631 #define DMA_CEEI_CEEI_SHIFT 0
2632 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
2633 #define DMA_CEEI_CAEE_MASK 0x40u
2634 #define DMA_CEEI_CAEE_SHIFT 6
2635 #define DMA_CEEI_NOP_MASK 0x80u
2636 #define DMA_CEEI_NOP_SHIFT 7
2637 /* SEEI Bit Fields */
2638 #define DMA_SEEI_SEEI_MASK 0xFu
2639 #define DMA_SEEI_SEEI_SHIFT 0
2640 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
2641 #define DMA_SEEI_SAEE_MASK 0x40u
2642 #define DMA_SEEI_SAEE_SHIFT 6
2643 #define DMA_SEEI_NOP_MASK 0x80u
2644 #define DMA_SEEI_NOP_SHIFT 7
2645 /* CERQ Bit Fields */
2646 #define DMA_CERQ_CERQ_MASK 0xFu
2647 #define DMA_CERQ_CERQ_SHIFT 0
2648 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
2649 #define DMA_CERQ_CAER_MASK 0x40u
2650 #define DMA_CERQ_CAER_SHIFT 6
2651 #define DMA_CERQ_NOP_MASK 0x80u
2652 #define DMA_CERQ_NOP_SHIFT 7
2653 /* SERQ Bit Fields */
2654 #define DMA_SERQ_SERQ_MASK 0xFu
2655 #define DMA_SERQ_SERQ_SHIFT 0
2656 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
2657 #define DMA_SERQ_SAER_MASK 0x40u
2658 #define DMA_SERQ_SAER_SHIFT 6
2659 #define DMA_SERQ_NOP_MASK 0x80u
2660 #define DMA_SERQ_NOP_SHIFT 7
2661 /* CDNE Bit Fields */
2662 #define DMA_CDNE_CDNE_MASK 0xFu
2663 #define DMA_CDNE_CDNE_SHIFT 0
2664 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
2665 #define DMA_CDNE_CADN_MASK 0x40u
2666 #define DMA_CDNE_CADN_SHIFT 6
2667 #define DMA_CDNE_NOP_MASK 0x80u
2668 #define DMA_CDNE_NOP_SHIFT 7
2669 /* SSRT Bit Fields */
2670 #define DMA_SSRT_SSRT_MASK 0xFu
2671 #define DMA_SSRT_SSRT_SHIFT 0
2672 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
2673 #define DMA_SSRT_SAST_MASK 0x40u
2674 #define DMA_SSRT_SAST_SHIFT 6
2675 #define DMA_SSRT_NOP_MASK 0x80u
2676 #define DMA_SSRT_NOP_SHIFT 7
2677 /* CERR Bit Fields */
2678 #define DMA_CERR_CERR_MASK 0xFu
2679 #define DMA_CERR_CERR_SHIFT 0
2680 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
2681 #define DMA_CERR_CAEI_MASK 0x40u
2682 #define DMA_CERR_CAEI_SHIFT 6
2683 #define DMA_CERR_NOP_MASK 0x80u
2684 #define DMA_CERR_NOP_SHIFT 7
2685 /* CINT Bit Fields */
2686 #define DMA_CINT_CINT_MASK 0xFu
2687 #define DMA_CINT_CINT_SHIFT 0
2688 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
2689 #define DMA_CINT_CAIR_MASK 0x40u
2690 #define DMA_CINT_CAIR_SHIFT 6
2691 #define DMA_CINT_NOP_MASK 0x80u
2692 #define DMA_CINT_NOP_SHIFT 7
2693 /* INT Bit Fields */
2694 #define DMA_INT_INT0_MASK 0x1u
2695 #define DMA_INT_INT0_SHIFT 0
2696 #define DMA_INT_INT1_MASK 0x2u
2697 #define DMA_INT_INT1_SHIFT 1
2698 #define DMA_INT_INT2_MASK 0x4u
2699 #define DMA_INT_INT2_SHIFT 2
2700 #define DMA_INT_INT3_MASK 0x8u
2701 #define DMA_INT_INT3_SHIFT 3
2702 #define DMA_INT_INT4_MASK 0x10u
2703 #define DMA_INT_INT4_SHIFT 4
2704 #define DMA_INT_INT5_MASK 0x20u
2705 #define DMA_INT_INT5_SHIFT 5
2706 #define DMA_INT_INT6_MASK 0x40u
2707 #define DMA_INT_INT6_SHIFT 6
2708 #define DMA_INT_INT7_MASK 0x80u
2709 #define DMA_INT_INT7_SHIFT 7
2710 #define DMA_INT_INT8_MASK 0x100u
2711 #define DMA_INT_INT8_SHIFT 8
2712 #define DMA_INT_INT9_MASK 0x200u
2713 #define DMA_INT_INT9_SHIFT 9
2714 #define DMA_INT_INT10_MASK 0x400u
2715 #define DMA_INT_INT10_SHIFT 10
2716 #define DMA_INT_INT11_MASK 0x800u
2717 #define DMA_INT_INT11_SHIFT 11
2718 #define DMA_INT_INT12_MASK 0x1000u
2719 #define DMA_INT_INT12_SHIFT 12
2720 #define DMA_INT_INT13_MASK 0x2000u
2721 #define DMA_INT_INT13_SHIFT 13
2722 #define DMA_INT_INT14_MASK 0x4000u
2723 #define DMA_INT_INT14_SHIFT 14
2724 #define DMA_INT_INT15_MASK 0x8000u
2725 #define DMA_INT_INT15_SHIFT 15
2726 /* ERR Bit Fields */
2727 #define DMA_ERR_ERR0_MASK 0x1u
2728 #define DMA_ERR_ERR0_SHIFT 0
2729 #define DMA_ERR_ERR1_MASK 0x2u
2730 #define DMA_ERR_ERR1_SHIFT 1
2731 #define DMA_ERR_ERR2_MASK 0x4u
2732 #define DMA_ERR_ERR2_SHIFT 2
2733 #define DMA_ERR_ERR3_MASK 0x8u
2734 #define DMA_ERR_ERR3_SHIFT 3
2735 #define DMA_ERR_ERR4_MASK 0x10u
2736 #define DMA_ERR_ERR4_SHIFT 4
2737 #define DMA_ERR_ERR5_MASK 0x20u
2738 #define DMA_ERR_ERR5_SHIFT 5
2739 #define DMA_ERR_ERR6_MASK 0x40u
2740 #define DMA_ERR_ERR6_SHIFT 6
2741 #define DMA_ERR_ERR7_MASK 0x80u
2742 #define DMA_ERR_ERR7_SHIFT 7
2743 #define DMA_ERR_ERR8_MASK 0x100u
2744 #define DMA_ERR_ERR8_SHIFT 8
2745 #define DMA_ERR_ERR9_MASK 0x200u
2746 #define DMA_ERR_ERR9_SHIFT 9
2747 #define DMA_ERR_ERR10_MASK 0x400u
2748 #define DMA_ERR_ERR10_SHIFT 10
2749 #define DMA_ERR_ERR11_MASK 0x800u
2750 #define DMA_ERR_ERR11_SHIFT 11
2751 #define DMA_ERR_ERR12_MASK 0x1000u
2752 #define DMA_ERR_ERR12_SHIFT 12
2753 #define DMA_ERR_ERR13_MASK 0x2000u
2754 #define DMA_ERR_ERR13_SHIFT 13
2755 #define DMA_ERR_ERR14_MASK 0x4000u
2756 #define DMA_ERR_ERR14_SHIFT 14
2757 #define DMA_ERR_ERR15_MASK 0x8000u
2758 #define DMA_ERR_ERR15_SHIFT 15
2759 /* HRS Bit Fields */
2760 #define DMA_HRS_HRS0_MASK 0x1u
2761 #define DMA_HRS_HRS0_SHIFT 0
2762 #define DMA_HRS_HRS1_MASK 0x2u
2763 #define DMA_HRS_HRS1_SHIFT 1
2764 #define DMA_HRS_HRS2_MASK 0x4u
2765 #define DMA_HRS_HRS2_SHIFT 2
2766 #define DMA_HRS_HRS3_MASK 0x8u
2767 #define DMA_HRS_HRS3_SHIFT 3
2768 #define DMA_HRS_HRS4_MASK 0x10u
2769 #define DMA_HRS_HRS4_SHIFT 4
2770 #define DMA_HRS_HRS5_MASK 0x20u
2771 #define DMA_HRS_HRS5_SHIFT 5
2772 #define DMA_HRS_HRS6_MASK 0x40u
2773 #define DMA_HRS_HRS6_SHIFT 6
2774 #define DMA_HRS_HRS7_MASK 0x80u
2775 #define DMA_HRS_HRS7_SHIFT 7
2776 #define DMA_HRS_HRS8_MASK 0x100u
2777 #define DMA_HRS_HRS8_SHIFT 8
2778 #define DMA_HRS_HRS9_MASK 0x200u
2779 #define DMA_HRS_HRS9_SHIFT 9
2780 #define DMA_HRS_HRS10_MASK 0x400u
2781 #define DMA_HRS_HRS10_SHIFT 10
2782 #define DMA_HRS_HRS11_MASK 0x800u
2783 #define DMA_HRS_HRS11_SHIFT 11
2784 #define DMA_HRS_HRS12_MASK 0x1000u
2785 #define DMA_HRS_HRS12_SHIFT 12
2786 #define DMA_HRS_HRS13_MASK 0x2000u
2787 #define DMA_HRS_HRS13_SHIFT 13
2788 #define DMA_HRS_HRS14_MASK 0x4000u
2789 #define DMA_HRS_HRS14_SHIFT 14
2790 #define DMA_HRS_HRS15_MASK 0x8000u
2791 #define DMA_HRS_HRS15_SHIFT 15
2792 /* DCHPRI3 Bit Fields */
2793 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
2794 #define DMA_DCHPRI3_CHPRI_SHIFT 0
2795 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
2796 #define DMA_DCHPRI3_DPA_MASK 0x40u
2797 #define DMA_DCHPRI3_DPA_SHIFT 6
2798 #define DMA_DCHPRI3_ECP_MASK 0x80u
2799 #define DMA_DCHPRI3_ECP_SHIFT 7
2800 /* DCHPRI2 Bit Fields */
2801 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
2802 #define DMA_DCHPRI2_CHPRI_SHIFT 0
2803 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
2804 #define DMA_DCHPRI2_DPA_MASK 0x40u
2805 #define DMA_DCHPRI2_DPA_SHIFT 6
2806 #define DMA_DCHPRI2_ECP_MASK 0x80u
2807 #define DMA_DCHPRI2_ECP_SHIFT 7
2808 /* DCHPRI1 Bit Fields */
2809 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
2810 #define DMA_DCHPRI1_CHPRI_SHIFT 0
2811 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
2812 #define DMA_DCHPRI1_DPA_MASK 0x40u
2813 #define DMA_DCHPRI1_DPA_SHIFT 6
2814 #define DMA_DCHPRI1_ECP_MASK 0x80u
2815 #define DMA_DCHPRI1_ECP_SHIFT 7
2816 /* DCHPRI0 Bit Fields */
2817 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
2818 #define DMA_DCHPRI0_CHPRI_SHIFT 0
2819 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
2820 #define DMA_DCHPRI0_DPA_MASK 0x40u
2821 #define DMA_DCHPRI0_DPA_SHIFT 6
2822 #define DMA_DCHPRI0_ECP_MASK 0x80u
2823 #define DMA_DCHPRI0_ECP_SHIFT 7
2824 /* DCHPRI7 Bit Fields */
2825 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
2826 #define DMA_DCHPRI7_CHPRI_SHIFT 0
2827 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
2828 #define DMA_DCHPRI7_DPA_MASK 0x40u
2829 #define DMA_DCHPRI7_DPA_SHIFT 6
2830 #define DMA_DCHPRI7_ECP_MASK 0x80u
2831 #define DMA_DCHPRI7_ECP_SHIFT 7
2832 /* DCHPRI6 Bit Fields */
2833 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
2834 #define DMA_DCHPRI6_CHPRI_SHIFT 0
2835 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
2836 #define DMA_DCHPRI6_DPA_MASK 0x40u
2837 #define DMA_DCHPRI6_DPA_SHIFT 6
2838 #define DMA_DCHPRI6_ECP_MASK 0x80u
2839 #define DMA_DCHPRI6_ECP_SHIFT 7
2840 /* DCHPRI5 Bit Fields */
2841 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
2842 #define DMA_DCHPRI5_CHPRI_SHIFT 0
2843 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
2844 #define DMA_DCHPRI5_DPA_MASK 0x40u
2845 #define DMA_DCHPRI5_DPA_SHIFT 6
2846 #define DMA_DCHPRI5_ECP_MASK 0x80u
2847 #define DMA_DCHPRI5_ECP_SHIFT 7
2848 /* DCHPRI4 Bit Fields */
2849 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
2850 #define DMA_DCHPRI4_CHPRI_SHIFT 0
2851 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
2852 #define DMA_DCHPRI4_DPA_MASK 0x40u
2853 #define DMA_DCHPRI4_DPA_SHIFT 6
2854 #define DMA_DCHPRI4_ECP_MASK 0x80u
2855 #define DMA_DCHPRI4_ECP_SHIFT 7
2856 /* DCHPRI11 Bit Fields */
2857 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
2858 #define DMA_DCHPRI11_CHPRI_SHIFT 0
2859 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
2860 #define DMA_DCHPRI11_DPA_MASK 0x40u
2861 #define DMA_DCHPRI11_DPA_SHIFT 6
2862 #define DMA_DCHPRI11_ECP_MASK 0x80u
2863 #define DMA_DCHPRI11_ECP_SHIFT 7
2864 /* DCHPRI10 Bit Fields */
2865 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
2866 #define DMA_DCHPRI10_CHPRI_SHIFT 0
2867 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
2868 #define DMA_DCHPRI10_DPA_MASK 0x40u
2869 #define DMA_DCHPRI10_DPA_SHIFT 6
2870 #define DMA_DCHPRI10_ECP_MASK 0x80u
2871 #define DMA_DCHPRI10_ECP_SHIFT 7
2872 /* DCHPRI9 Bit Fields */
2873 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
2874 #define DMA_DCHPRI9_CHPRI_SHIFT 0
2875 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
2876 #define DMA_DCHPRI9_DPA_MASK 0x40u
2877 #define DMA_DCHPRI9_DPA_SHIFT 6
2878 #define DMA_DCHPRI9_ECP_MASK 0x80u
2879 #define DMA_DCHPRI9_ECP_SHIFT 7
2880 /* DCHPRI8 Bit Fields */
2881 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
2882 #define DMA_DCHPRI8_CHPRI_SHIFT 0
2883 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
2884 #define DMA_DCHPRI8_DPA_MASK 0x40u
2885 #define DMA_DCHPRI8_DPA_SHIFT 6
2886 #define DMA_DCHPRI8_ECP_MASK 0x80u
2887 #define DMA_DCHPRI8_ECP_SHIFT 7
2888 /* DCHPRI15 Bit Fields */
2889 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
2890 #define DMA_DCHPRI15_CHPRI_SHIFT 0
2891 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
2892 #define DMA_DCHPRI15_DPA_MASK 0x40u
2893 #define DMA_DCHPRI15_DPA_SHIFT 6
2894 #define DMA_DCHPRI15_ECP_MASK 0x80u
2895 #define DMA_DCHPRI15_ECP_SHIFT 7
2896 /* DCHPRI14 Bit Fields */
2897 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
2898 #define DMA_DCHPRI14_CHPRI_SHIFT 0
2899 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
2900 #define DMA_DCHPRI14_DPA_MASK 0x40u
2901 #define DMA_DCHPRI14_DPA_SHIFT 6
2902 #define DMA_DCHPRI14_ECP_MASK 0x80u
2903 #define DMA_DCHPRI14_ECP_SHIFT 7
2904 /* DCHPRI13 Bit Fields */
2905 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
2906 #define DMA_DCHPRI13_CHPRI_SHIFT 0
2907 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
2908 #define DMA_DCHPRI13_DPA_MASK 0x40u
2909 #define DMA_DCHPRI13_DPA_SHIFT 6
2910 #define DMA_DCHPRI13_ECP_MASK 0x80u
2911 #define DMA_DCHPRI13_ECP_SHIFT 7
2912 /* DCHPRI12 Bit Fields */
2913 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
2914 #define DMA_DCHPRI12_CHPRI_SHIFT 0
2915 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
2916 #define DMA_DCHPRI12_DPA_MASK 0x40u
2917 #define DMA_DCHPRI12_DPA_SHIFT 6
2918 #define DMA_DCHPRI12_ECP_MASK 0x80u
2919 #define DMA_DCHPRI12_ECP_SHIFT 7
2920 /* SADDR Bit Fields */
2921 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
2922 #define DMA_SADDR_SADDR_SHIFT 0
2923 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
2924 /* SOFF Bit Fields */
2925 #define DMA_SOFF_SOFF_MASK 0xFFFFu
2926 #define DMA_SOFF_SOFF_SHIFT 0
2927 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
2928 /* ATTR Bit Fields */
2929 #define DMA_ATTR_DSIZE_MASK 0x7u
2930 #define DMA_ATTR_DSIZE_SHIFT 0
2931 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
2932 #define DMA_ATTR_DMOD_MASK 0xF8u
2933 #define DMA_ATTR_DMOD_SHIFT 3
2934 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
2935 #define DMA_ATTR_SSIZE_MASK 0x700u
2936 #define DMA_ATTR_SSIZE_SHIFT 8
2937 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
2938 #define DMA_ATTR_SMOD_MASK 0xF800u
2939 #define DMA_ATTR_SMOD_SHIFT 11
2940 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
2941 /* NBYTES_MLNO Bit Fields */
2942 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
2943 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
2944 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
2945 /* NBYTES_MLOFFNO Bit Fields */
2946 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
2947 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
2948 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
2949 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
2950 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
2951 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
2952 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
2953 /* NBYTES_MLOFFYES Bit Fields */
2954 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
2955 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
2956 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
2957 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
2958 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
2959 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
2960 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
2961 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
2962 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
2963 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
2964 /* SLAST Bit Fields */
2965 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
2966 #define DMA_SLAST_SLAST_SHIFT 0
2967 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
2968 /* DADDR Bit Fields */
2969 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
2970 #define DMA_DADDR_DADDR_SHIFT 0
2971 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
2972 /* DOFF Bit Fields */
2973 #define DMA_DOFF_DOFF_MASK 0xFFFFu
2974 #define DMA_DOFF_DOFF_SHIFT 0
2975 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
2976 /* CITER_ELINKNO Bit Fields */
2977 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
2978 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
2979 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
2980 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
2981 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
2982 /* CITER_ELINKYES Bit Fields */
2983 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
2984 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
2985 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
2986 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
2987 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
2988 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
2989 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
2990 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
2991 /* DLAST_SGA Bit Fields */
2992 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
2993 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
2994 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
2995 /* CSR Bit Fields */
2996 #define DMA_CSR_START_MASK 0x1u
2997 #define DMA_CSR_START_SHIFT 0
2998 #define DMA_CSR_INTMAJOR_MASK 0x2u
2999 #define DMA_CSR_INTMAJOR_SHIFT 1
3000 #define DMA_CSR_INTHALF_MASK 0x4u
3001 #define DMA_CSR_INTHALF_SHIFT 2
3002 #define DMA_CSR_DREQ_MASK 0x8u
3003 #define DMA_CSR_DREQ_SHIFT 3
3004 #define DMA_CSR_ESG_MASK 0x10u
3005 #define DMA_CSR_ESG_SHIFT 4
3006 #define DMA_CSR_MAJORELINK_MASK 0x20u
3007 #define DMA_CSR_MAJORELINK_SHIFT 5
3008 #define DMA_CSR_ACTIVE_MASK 0x40u
3009 #define DMA_CSR_ACTIVE_SHIFT 6
3010 #define DMA_CSR_DONE_MASK 0x80u
3011 #define DMA_CSR_DONE_SHIFT 7
3012 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
3013 #define DMA_CSR_MAJORLINKCH_SHIFT 8
3014 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
3015 #define DMA_CSR_BWC_MASK 0xC000u
3016 #define DMA_CSR_BWC_SHIFT 14
3017 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
3018 /* BITER_ELINKNO Bit Fields */
3019 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
3020 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
3021 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
3022 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
3023 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
3024 /* BITER_ELINKYES Bit Fields */
3025 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
3026 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
3027 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
3028 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
3029 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
3030 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
3031 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
3032 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
3033 
3034 /**
3035  * @}
3036  */ /* end of group DMA_Register_Masks */
3037 
3038 
3039 /* DMA - Peripheral instance base addresses */
3040 /** Peripheral DMA base address */
3041 #define DMA_BASE (0x40008000u)
3042 /** Peripheral DMA base pointer */
3043 #define DMA0 ((DMA_Type *)DMA_BASE)
3044 /** Array initializer of DMA peripheral base pointers */
3045 #define DMA_BASES { DMA0 }
3046 
3047 /**
3048  * @}
3049  */ /* end of group DMA_Peripheral_Access_Layer */
3050 
3051 
3052 /* ----------------------------------------------------------------------------
3053  -- DMAMUX Peripheral Access Layer
3054  ---------------------------------------------------------------------------- */
3055 
3056 /**
3057  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
3058  * @{
3059  */
3060 
3061 /** DMAMUX - Register Layout Typedef */
3062 typedef struct {
3063  __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
3064 } DMAMUX_Type;
3065 
3066 /* ----------------------------------------------------------------------------
3067  -- DMAMUX Register Masks
3068  ---------------------------------------------------------------------------- */
3069 
3070 /**
3071  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
3072  * @{
3073  */
3074 
3075 /* CHCFG Bit Fields */
3076 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
3077 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
3078 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
3079 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
3080 #define DMAMUX_CHCFG_TRIG_SHIFT 6
3081 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
3082 #define DMAMUX_CHCFG_ENBL_SHIFT 7
3083 
3084 /**
3085  * @}
3086  */ /* end of group DMAMUX_Register_Masks */
3087 
3088 
3089 /* DMAMUX - Peripheral instance base addresses */
3090 /** Peripheral DMAMUX base address */
3091 #define DMAMUX_BASE (0x40021000u)
3092 /** Peripheral DMAMUX base pointer */
3093 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3094 /** Array initializer of DMAMUX peripheral base pointers */
3095 #define DMAMUX_BASES { DMAMUX }
3096 
3097 /**
3098  * @}
3099  */ /* end of group DMAMUX_Peripheral_Access_Layer */
3100 
3101 
3102 /* ----------------------------------------------------------------------------
3103  -- ENET Peripheral Access Layer
3104  ---------------------------------------------------------------------------- */
3105 
3106 /**
3107  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
3108  * @{
3109  */
3110 
3111 /** ENET - Register Layout Typedef */
3112 typedef struct {
3113  uint8_t RESERVED_0[4];
3114  __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
3115  __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
3116  uint8_t RESERVED_1[4];
3117  __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
3118  __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
3119  uint8_t RESERVED_2[12];
3120  __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
3121  uint8_t RESERVED_3[24];
3122  __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
3123  __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
3124  uint8_t RESERVED_4[28];
3125  __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
3126  uint8_t RESERVED_5[28];
3127  __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
3128  uint8_t RESERVED_6[60];
3129  __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
3130  uint8_t RESERVED_7[28];
3131  __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
3132  __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
3133  __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
3134  uint8_t RESERVED_8[40];
3135  __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
3136  __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
3137  __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
3138  __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
3139  uint8_t RESERVED_9[28];
3140  __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
3141  uint8_t RESERVED_10[56];
3142  __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
3143  __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
3144  __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
3145  uint8_t RESERVED_11[4];
3146  __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
3147  __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
3148  __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
3149  __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
3150  __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
3151  __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
3152  __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
3153  __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
3154  __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
3155  uint8_t RESERVED_12[12];
3156  __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
3157  __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
3158  uint8_t RESERVED_13[56];
3159  __IO uint32_t RMON_T_DROP; /**< Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200 */
3160  __IO uint32_t RMON_T_PACKETS; /**< RMON Tx packet count (RMON_T_PACKETS), offset: 0x204 */
3161  __IO uint32_t RMON_T_BC_PKT; /**< RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208 */
3162  __IO uint32_t RMON_T_MC_PKT; /**< RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C */
3163  __IO uint32_t RMON_T_CRC_ALIGN; /**< RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210 */
3164  __IO uint32_t RMON_T_UNDERSIZE; /**< RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214 */
3165  __IO uint32_t RMON_T_OVERSIZE; /**< RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */
3166  __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */
3167  __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */
3168  __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */
3169  __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */
3170  __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */
3171  __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */
3172  __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */
3173  __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */
3174  __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */
3175  __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */
3176  __IO uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */
3177  __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */
3178  __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */
3179  __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */
3180  __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */
3181  __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */
3182  __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */
3183  __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */
3184  __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */
3185  __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */
3186  __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */
3187  __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */
3188  __IO uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */
3189  uint8_t RESERVED_14[12];
3190  __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */
3191  __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */
3192  __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */
3193  __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */
3194  __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */
3195  __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */
3196  __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */
3197  __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */
3198  __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */
3199  __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */
3200  __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */
3201  __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */
3202  __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */
3203  __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */
3204  __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */
3205  __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */
3206  __IO uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */
3207  __IO uint32_t RMON_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */
3208  __IO uint32_t RMON_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */
3209  __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */
3210  __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */
3211  __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */
3212  __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */
3213  __IO uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */
3214  uint8_t RESERVED_15[284];
3215  __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */
3216  __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
3217  __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
3218  __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
3219  __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
3220  __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
3221  __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
3222  uint8_t RESERVED_16[488];
3223  __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
3224  struct { /* offset: 0x608, array step: 0x8 */
3225  __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
3226  __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
3227  } CHANNEL[4];
3228 } ENET_Type;
3229 
3230 /* ----------------------------------------------------------------------------
3231  -- ENET Register Masks
3232  ---------------------------------------------------------------------------- */
3233 
3234 /**
3235  * @addtogroup ENET_Register_Masks ENET Register Masks
3236  * @{
3237  */
3238 
3239 /* EIR Bit Fields */
3240 #define ENET_EIR_TS_TIMER_MASK 0x8000u
3241 #define ENET_EIR_TS_TIMER_SHIFT 15
3242 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
3243 #define ENET_EIR_TS_AVAIL_SHIFT 16
3244 #define ENET_EIR_WAKEUP_MASK 0x20000u
3245 #define ENET_EIR_WAKEUP_SHIFT 17
3246 #define ENET_EIR_PLR_MASK 0x40000u
3247 #define ENET_EIR_PLR_SHIFT 18
3248 #define ENET_EIR_UN_MASK 0x80000u
3249 #define ENET_EIR_UN_SHIFT 19
3250 #define ENET_EIR_RL_MASK 0x100000u
3251 #define ENET_EIR_RL_SHIFT 20
3252 #define ENET_EIR_LC_MASK 0x200000u
3253 #define ENET_EIR_LC_SHIFT 21
3254 #define ENET_EIR_EBERR_MASK 0x400000u
3255 #define ENET_EIR_EBERR_SHIFT 22
3256 #define ENET_EIR_MII_MASK 0x800000u
3257 #define ENET_EIR_MII_SHIFT 23
3258 #define ENET_EIR_RXB_MASK 0x1000000u
3259 #define ENET_EIR_RXB_SHIFT 24
3260 #define ENET_EIR_RXF_MASK 0x2000000u
3261 #define ENET_EIR_RXF_SHIFT 25
3262 #define ENET_EIR_TXB_MASK 0x4000000u
3263 #define ENET_EIR_TXB_SHIFT 26
3264 #define ENET_EIR_TXF_MASK 0x8000000u
3265 #define ENET_EIR_TXF_SHIFT 27
3266 #define ENET_EIR_GRA_MASK 0x10000000u
3267 #define ENET_EIR_GRA_SHIFT 28
3268 #define ENET_EIR_BABT_MASK 0x20000000u
3269 #define ENET_EIR_BABT_SHIFT 29
3270 #define ENET_EIR_BABR_MASK 0x40000000u
3271 #define ENET_EIR_BABR_SHIFT 30
3272 /* EIMR Bit Fields */
3273 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
3274 #define ENET_EIMR_TS_TIMER_SHIFT 15
3275 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
3276 #define ENET_EIMR_TS_AVAIL_SHIFT 16
3277 #define ENET_EIMR_WAKEUP_MASK 0x20000u
3278 #define ENET_EIMR_WAKEUP_SHIFT 17
3279 #define ENET_EIMR_PLR_MASK 0x40000u
3280 #define ENET_EIMR_PLR_SHIFT 18
3281 #define ENET_EIMR_UN_MASK 0x80000u
3282 #define ENET_EIMR_UN_SHIFT 19
3283 #define ENET_EIMR_RL_MASK 0x100000u
3284 #define ENET_EIMR_RL_SHIFT 20
3285 #define ENET_EIMR_LC_MASK 0x200000u
3286 #define ENET_EIMR_LC_SHIFT 21
3287 #define ENET_EIMR_EBERR_MASK 0x400000u
3288 #define ENET_EIMR_EBERR_SHIFT 22
3289 #define ENET_EIMR_MII_MASK 0x800000u
3290 #define ENET_EIMR_MII_SHIFT 23
3291 #define ENET_EIMR_RXB_MASK 0x1000000u
3292 #define ENET_EIMR_RXB_SHIFT 24
3293 #define ENET_EIMR_RXF_MASK 0x2000000u
3294 #define ENET_EIMR_RXF_SHIFT 25
3295 #define ENET_EIMR_TXB_MASK 0x4000000u
3296 #define ENET_EIMR_TXB_SHIFT 26
3297 #define ENET_EIMR_TXF_MASK 0x8000000u
3298 #define ENET_EIMR_TXF_SHIFT 27
3299 #define ENET_EIMR_GRA_MASK 0x10000000u
3300 #define ENET_EIMR_GRA_SHIFT 28
3301 #define ENET_EIMR_BABT_MASK 0x20000000u
3302 #define ENET_EIMR_BABT_SHIFT 29
3303 #define ENET_EIMR_BABR_MASK 0x40000000u
3304 #define ENET_EIMR_BABR_SHIFT 30
3305 /* RDAR Bit Fields */
3306 #define ENET_RDAR_RDAR_MASK 0x1000000u
3307 #define ENET_RDAR_RDAR_SHIFT 24
3308 /* TDAR Bit Fields */
3309 #define ENET_TDAR_TDAR_MASK 0x1000000u
3310 #define ENET_TDAR_TDAR_SHIFT 24
3311 /* ECR Bit Fields */
3312 #define ENET_ECR_RESET_MASK 0x1u
3313 #define ENET_ECR_RESET_SHIFT 0
3314 #define ENET_ECR_ETHEREN_MASK 0x2u
3315 #define ENET_ECR_ETHEREN_SHIFT 1
3316 #define ENET_ECR_MAGICEN_MASK 0x4u
3317 #define ENET_ECR_MAGICEN_SHIFT 2
3318 #define ENET_ECR_SLEEP_MASK 0x8u
3319 #define ENET_ECR_SLEEP_SHIFT 3
3320 #define ENET_ECR_EN1588_MASK 0x10u
3321 #define ENET_ECR_EN1588_SHIFT 4
3322 #define ENET_ECR_DBGEN_MASK 0x40u
3323 #define ENET_ECR_DBGEN_SHIFT 6
3324 #define ENET_ECR_STOPEN_MASK 0x80u
3325 #define ENET_ECR_STOPEN_SHIFT 7
3326 #define ENET_ECR_DBSWP_MASK 0x100u
3327 #define ENET_ECR_DBSWP_SHIFT 8
3328 /* MMFR Bit Fields */
3329 #define ENET_MMFR_DATA_MASK 0xFFFFu
3330 #define ENET_MMFR_DATA_SHIFT 0
3331 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
3332 #define ENET_MMFR_TA_MASK 0x30000u
3333 #define ENET_MMFR_TA_SHIFT 16
3334 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
3335 #define ENET_MMFR_RA_MASK 0x7C0000u
3336 #define ENET_MMFR_RA_SHIFT 18
3337 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
3338 #define ENET_MMFR_PA_MASK 0xF800000u
3339 #define ENET_MMFR_PA_SHIFT 23
3340 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
3341 #define ENET_MMFR_OP_MASK 0x30000000u
3342 #define ENET_MMFR_OP_SHIFT 28
3343 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
3344 #define ENET_MMFR_ST_MASK 0xC0000000u
3345 #define ENET_MMFR_ST_SHIFT 30
3346 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
3347 /* MSCR Bit Fields */
3348 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
3349 #define ENET_MSCR_MII_SPEED_SHIFT 1
3350 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
3351 #define ENET_MSCR_DIS_PRE_MASK 0x80u
3352 #define ENET_MSCR_DIS_PRE_SHIFT 7
3353 #define ENET_MSCR_HOLDTIME_MASK 0x700u
3354 #define ENET_MSCR_HOLDTIME_SHIFT 8
3355 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
3356 /* MIBC Bit Fields */
3357 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
3358 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
3359 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
3360 #define ENET_MIBC_MIB_IDLE_SHIFT 30
3361 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
3362 #define ENET_MIBC_MIB_DIS_SHIFT 31
3363 /* RCR Bit Fields */
3364 #define ENET_RCR_LOOP_MASK 0x1u
3365 #define ENET_RCR_LOOP_SHIFT 0
3366 #define ENET_RCR_DRT_MASK 0x2u
3367 #define ENET_RCR_DRT_SHIFT 1
3368 #define ENET_RCR_MII_MODE_MASK 0x4u
3369 #define ENET_RCR_MII_MODE_SHIFT 2
3370 #define ENET_RCR_PROM_MASK 0x8u
3371 #define ENET_RCR_PROM_SHIFT 3
3372 #define ENET_RCR_BC_REJ_MASK 0x10u
3373 #define ENET_RCR_BC_REJ_SHIFT 4
3374 #define ENET_RCR_FCE_MASK 0x20u
3375 #define ENET_RCR_FCE_SHIFT 5
3376 #define ENET_RCR_RMII_MODE_MASK 0x100u
3377 #define ENET_RCR_RMII_MODE_SHIFT 8
3378 #define ENET_RCR_RMII_10T_MASK 0x200u
3379 #define ENET_RCR_RMII_10T_SHIFT 9
3380 #define ENET_RCR_PADEN_MASK 0x1000u
3381 #define ENET_RCR_PADEN_SHIFT 12
3382 #define ENET_RCR_PAUFWD_MASK 0x2000u
3383 #define ENET_RCR_PAUFWD_SHIFT 13
3384 #define ENET_RCR_CRCFWD_MASK 0x4000u
3385 #define ENET_RCR_CRCFWD_SHIFT 14
3386 #define ENET_RCR_CFEN_MASK 0x8000u
3387 #define ENET_RCR_CFEN_SHIFT 15
3388 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
3389 #define ENET_RCR_MAX_FL_SHIFT 16
3390 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
3391 #define ENET_RCR_NLC_MASK 0x40000000u
3392 #define ENET_RCR_NLC_SHIFT 30
3393 #define ENET_RCR_GRS_MASK 0x80000000u
3394 #define ENET_RCR_GRS_SHIFT 31
3395 /* TCR Bit Fields */
3396 #define ENET_TCR_GTS_MASK 0x1u
3397 #define ENET_TCR_GTS_SHIFT 0
3398 #define ENET_TCR_FDEN_MASK 0x4u
3399 #define ENET_TCR_FDEN_SHIFT 2
3400 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
3401 #define ENET_TCR_TFC_PAUSE_SHIFT 3
3402 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
3403 #define ENET_TCR_RFC_PAUSE_SHIFT 4
3404 #define ENET_TCR_ADDSEL_MASK 0xE0u
3405 #define ENET_TCR_ADDSEL_SHIFT 5
3406 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
3407 #define ENET_TCR_ADDINS_MASK 0x100u
3408 #define ENET_TCR_ADDINS_SHIFT 8
3409 #define ENET_TCR_CRCFWD_MASK 0x200u
3410 #define ENET_TCR_CRCFWD_SHIFT 9
3411 /* PALR Bit Fields */
3412 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
3413 #define ENET_PALR_PADDR1_SHIFT 0
3414 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
3415 /* PAUR Bit Fields */
3416 #define ENET_PAUR_TYPE_MASK 0xFFFFu
3417 #define ENET_PAUR_TYPE_SHIFT 0
3418 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
3419 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
3420 #define ENET_PAUR_PADDR2_SHIFT 16
3421 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
3422 /* OPD Bit Fields */
3423 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
3424 #define ENET_OPD_PAUSE_DUR_SHIFT 0
3425 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
3426 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
3427 #define ENET_OPD_OPCODE_SHIFT 16
3428 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
3429 /* IAUR Bit Fields */
3430 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
3431 #define ENET_IAUR_IADDR1_SHIFT 0
3432 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
3433 /* IALR Bit Fields */
3434 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
3435 #define ENET_IALR_IADDR2_SHIFT 0
3436 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
3437 /* GAUR Bit Fields */
3438 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
3439 #define ENET_GAUR_GADDR1_SHIFT 0
3440 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
3441 /* GALR Bit Fields */
3442 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
3443 #define ENET_GALR_GADDR2_SHIFT 0
3444 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
3445 /* TFWR Bit Fields */
3446 #define ENET_TFWR_TFWR_MASK 0x3Fu
3447 #define ENET_TFWR_TFWR_SHIFT 0
3448 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
3449 #define ENET_TFWR_STRFWD_MASK 0x100u
3450 #define ENET_TFWR_STRFWD_SHIFT 8
3451 /* RDSR Bit Fields */
3452 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
3453 #define ENET_RDSR_R_DES_START_SHIFT 3
3454 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
3455 /* TDSR Bit Fields */
3456 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
3457 #define ENET_TDSR_X_DES_START_SHIFT 3
3458 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
3459 /* MRBR Bit Fields */
3460 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
3461 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
3462 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
3463 /* RSFL Bit Fields */
3464 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
3465 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
3466 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
3467 /* RSEM Bit Fields */
3468 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
3469 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
3470 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
3471 /* RAEM Bit Fields */
3472 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
3473 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
3474 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
3475 /* RAFL Bit Fields */
3476 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
3477 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
3478 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
3479 /* TSEM Bit Fields */
3480 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
3481 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
3482 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
3483 /* TAEM Bit Fields */
3484 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
3485 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
3486 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
3487 /* TAFL Bit Fields */
3488 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
3489 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
3490 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
3491 /* TIPG Bit Fields */
3492 #define ENET_TIPG_IPG_MASK 0x1Fu
3493 #define ENET_TIPG_IPG_SHIFT 0
3494 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
3495 /* FTRL Bit Fields */
3496 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
3497 #define ENET_FTRL_TRUNC_FL_SHIFT 0
3498 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
3499 /* TACC Bit Fields */
3500 #define ENET_TACC_SHIFT16_MASK 0x1u
3501 #define ENET_TACC_SHIFT16_SHIFT 0
3502 #define ENET_TACC_IPCHK_MASK 0x8u
3503 #define ENET_TACC_IPCHK_SHIFT 3
3504 #define ENET_TACC_PROCHK_MASK 0x10u
3505 #define ENET_TACC_PROCHK_SHIFT 4
3506 /* RACC Bit Fields */
3507 #define ENET_RACC_PADREM_MASK 0x1u
3508 #define ENET_RACC_PADREM_SHIFT 0
3509 #define ENET_RACC_IPDIS_MASK 0x2u
3510 #define ENET_RACC_IPDIS_SHIFT 1
3511 #define ENET_RACC_PRODIS_MASK 0x4u
3512 #define ENET_RACC_PRODIS_SHIFT 2
3513 #define ENET_RACC_LINEDIS_MASK 0x40u
3514 #define ENET_RACC_LINEDIS_SHIFT 6
3515 #define ENET_RACC_SHIFT16_MASK 0x80u
3516 #define ENET_RACC_SHIFT16_SHIFT 7
3517 /* ATCR Bit Fields */
3518 #define ENET_ATCR_EN_MASK 0x1u
3519 #define ENET_ATCR_EN_SHIFT 0
3520 #define ENET_ATCR_OFFEN_MASK 0x4u
3521 #define ENET_ATCR_OFFEN_SHIFT 2
3522 #define ENET_ATCR_OFFRST_MASK 0x8u
3523 #define ENET_ATCR_OFFRST_SHIFT 3
3524 #define ENET_ATCR_PEREN_MASK 0x10u
3525 #define ENET_ATCR_PEREN_SHIFT 4
3526 #define ENET_ATCR_PINPER_MASK 0x80u
3527 #define ENET_ATCR_PINPER_SHIFT 7
3528 #define ENET_ATCR_RESTART_MASK 0x200u
3529 #define ENET_ATCR_RESTART_SHIFT 9
3530 #define ENET_ATCR_CAPTURE_MASK 0x800u
3531 #define ENET_ATCR_CAPTURE_SHIFT 11
3532 #define ENET_ATCR_SLAVE_MASK 0x2000u
3533 #define ENET_ATCR_SLAVE_SHIFT 13
3534 /* ATVR Bit Fields */
3535 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
3536 #define ENET_ATVR_ATIME_SHIFT 0
3537 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
3538 /* ATOFF Bit Fields */
3539 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
3540 #define ENET_ATOFF_OFFSET_SHIFT 0
3541 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
3542 /* ATPER Bit Fields */
3543 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
3544 #define ENET_ATPER_PERIOD_SHIFT 0
3545 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
3546 /* ATCOR Bit Fields */
3547 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
3548 #define ENET_ATCOR_COR_SHIFT 0
3549 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
3550 /* ATINC Bit Fields */
3551 #define ENET_ATINC_INC_MASK 0x7Fu
3552 #define ENET_ATINC_INC_SHIFT 0
3553 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
3554 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
3555 #define ENET_ATINC_INC_CORR_SHIFT 8
3556 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
3557 /* ATSTMP Bit Fields */
3558 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
3559 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
3560 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
3561 /* TGSR Bit Fields */
3562 #define ENET_TGSR_TF0_MASK 0x1u
3563 #define ENET_TGSR_TF0_SHIFT 0
3564 #define ENET_TGSR_TF1_MASK 0x2u
3565 #define ENET_TGSR_TF1_SHIFT 1
3566 #define ENET_TGSR_TF2_MASK 0x4u
3567 #define ENET_TGSR_TF2_SHIFT 2
3568 #define ENET_TGSR_TF3_MASK 0x8u
3569 #define ENET_TGSR_TF3_SHIFT 3
3570 /* TCSR Bit Fields */
3571 #define ENET_TCSR_TDRE_MASK 0x1u
3572 #define ENET_TCSR_TDRE_SHIFT 0
3573 #define ENET_TCSR_TMODE_MASK 0x3Cu
3574 #define ENET_TCSR_TMODE_SHIFT 2
3575 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
3576 #define ENET_TCSR_TIE_MASK 0x40u
3577 #define ENET_TCSR_TIE_SHIFT 6
3578 #define ENET_TCSR_TF_MASK 0x80u
3579 #define ENET_TCSR_TF_SHIFT 7
3580 /* TCCR Bit Fields */
3581 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
3582 #define ENET_TCCR_TCC_SHIFT 0
3583 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
3584 
3585 /**
3586  * @}
3587  */ /* end of group ENET_Register_Masks */
3588 
3589 
3590 /* ENET - Peripheral instance base addresses */
3591 /** Peripheral ENET base address */
3592 #define ENET_BASE (0x400C0000u)
3593 /** Peripheral ENET base pointer */
3594 #define ENET ((ENET_Type *)ENET_BASE)
3595 /** Array initializer of ENET peripheral base pointers */
3596 #define ENET_BASES { ENET }
3597 
3598 /**
3599  * @}
3600  */ /* end of group ENET_Peripheral_Access_Layer */
3601 
3602 
3603 /* ----------------------------------------------------------------------------
3604  -- EWM Peripheral Access Layer
3605  ---------------------------------------------------------------------------- */
3606 
3607 /**
3608  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
3609  * @{
3610  */
3611 
3612 /** EWM - Register Layout Typedef */
3613 typedef struct {
3614  __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
3615  __O uint8_t SERV; /**< Service Register, offset: 0x1 */
3616  __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
3617  __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
3618  uint8_t RESERVED_0[1];
3619  __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
3620 } EWM_Type;
3621 
3622 /* ----------------------------------------------------------------------------
3623  -- EWM Register Masks
3624  ---------------------------------------------------------------------------- */
3625 
3626 /**
3627  * @addtogroup EWM_Register_Masks EWM Register Masks
3628  * @{
3629  */
3630 
3631 /* CTRL Bit Fields */
3632 #define EWM_CTRL_EWMEN_MASK 0x1u
3633 #define EWM_CTRL_EWMEN_SHIFT 0
3634 #define EWM_CTRL_ASSIN_MASK 0x2u
3635 #define EWM_CTRL_ASSIN_SHIFT 1
3636 #define EWM_CTRL_INEN_MASK 0x4u
3637 #define EWM_CTRL_INEN_SHIFT 2
3638 #define EWM_CTRL_INTEN_MASK 0x8u
3639 #define EWM_CTRL_INTEN_SHIFT 3
3640 /* SERV Bit Fields */
3641 #define EWM_SERV_SERVICE_MASK 0xFFu
3642 #define EWM_SERV_SERVICE_SHIFT 0
3643 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
3644 /* CMPL Bit Fields */
3645 #define EWM_CMPL_COMPAREL_MASK 0xFFu
3646 #define EWM_CMPL_COMPAREL_SHIFT 0
3647 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
3648 /* CMPH Bit Fields */
3649 #define EWM_CMPH_COMPAREH_MASK 0xFFu
3650 #define EWM_CMPH_COMPAREH_SHIFT 0
3651 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
3652 /* CLKPRESCALER Bit Fields */
3653 #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
3654 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
3655 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
3656 
3657 /**
3658  * @}
3659  */ /* end of group EWM_Register_Masks */
3660 
3661 
3662 /* EWM - Peripheral instance base addresses */
3663 /** Peripheral EWM base address */
3664 #define EWM_BASE (0x40061000u)
3665 /** Peripheral EWM base pointer */
3666 #define EWM ((EWM_Type *)EWM_BASE)
3667 /** Array initializer of EWM peripheral base pointers */
3668 #define EWM_BASES { EWM }
3669 
3670 /**
3671  * @}
3672  */ /* end of group EWM_Peripheral_Access_Layer */
3673 
3674 
3675 /* ----------------------------------------------------------------------------
3676  -- FB Peripheral Access Layer
3677  ---------------------------------------------------------------------------- */
3678 
3679 /**
3680  * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
3681  * @{
3682  */
3683 
3684 /** FB - Register Layout Typedef */
3685 typedef struct {
3686  struct { /* offset: 0x0, array step: 0xC */
3687  __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
3688  __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
3689  __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
3690  } CS[6];
3691  uint8_t RESERVED_0[24];
3692  __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
3693 } FB_Type;
3694 
3695 /* ----------------------------------------------------------------------------
3696  -- FB Register Masks
3697  ---------------------------------------------------------------------------- */
3698 
3699 /**
3700  * @addtogroup FB_Register_Masks FB Register Masks
3701  * @{
3702  */
3703 
3704 /* CSAR Bit Fields */
3705 #define FB_CSAR_BA_MASK 0xFFFF0000u
3706 #define FB_CSAR_BA_SHIFT 16
3707 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
3708 /* CSMR Bit Fields */
3709 #define FB_CSMR_V_MASK 0x1u
3710 #define FB_CSMR_V_SHIFT 0
3711 #define FB_CSMR_WP_MASK 0x100u
3712 #define FB_CSMR_WP_SHIFT 8
3713 #define FB_CSMR_BAM_MASK 0xFFFF0000u
3714 #define FB_CSMR_BAM_SHIFT 16
3715 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
3716 /* CSCR Bit Fields */
3717 #define FB_CSCR_BSTW_MASK 0x8u
3718 #define FB_CSCR_BSTW_SHIFT 3
3719 #define FB_CSCR_BSTR_MASK 0x10u
3720 #define FB_CSCR_BSTR_SHIFT 4
3721 #define FB_CSCR_BEM_MASK 0x20u
3722 #define FB_CSCR_BEM_SHIFT 5
3723 #define FB_CSCR_PS_MASK 0xC0u
3724 #define FB_CSCR_PS_SHIFT 6
3725 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
3726 #define FB_CSCR_AA_MASK 0x100u
3727 #define FB_CSCR_AA_SHIFT 8
3728 #define FB_CSCR_BLS_MASK 0x200u
3729 #define FB_CSCR_BLS_SHIFT 9
3730 #define FB_CSCR_WS_MASK 0xFC00u
3731 #define FB_CSCR_WS_SHIFT 10
3732 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
3733 #define FB_CSCR_WRAH_MASK 0x30000u
3734 #define FB_CSCR_WRAH_SHIFT 16
3735 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
3736 #define FB_CSCR_RDAH_MASK 0xC0000u
3737 #define FB_CSCR_RDAH_SHIFT 18
3738 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
3739 #define FB_CSCR_ASET_MASK 0x300000u
3740 #define FB_CSCR_ASET_SHIFT 20
3741 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
3742 #define FB_CSCR_EXTS_MASK 0x400000u
3743 #define FB_CSCR_EXTS_SHIFT 22
3744 #define FB_CSCR_SWSEN_MASK 0x800000u
3745 #define FB_CSCR_SWSEN_SHIFT 23
3746 #define FB_CSCR_SWS_MASK 0xFC000000u
3747 #define FB_CSCR_SWS_SHIFT 26
3748 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
3749 /* CSPMCR Bit Fields */
3750 #define FB_CSPMCR_GROUP5_MASK 0xF000u
3751 #define FB_CSPMCR_GROUP5_SHIFT 12
3752 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
3753 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
3754 #define FB_CSPMCR_GROUP4_SHIFT 16
3755 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
3756 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
3757 #define FB_CSPMCR_GROUP3_SHIFT 20
3758 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
3759 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
3760 #define FB_CSPMCR_GROUP2_SHIFT 24
3761 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
3762 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
3763 #define FB_CSPMCR_GROUP1_SHIFT 28
3764 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
3765 
3766 /**
3767  * @}
3768  */ /* end of group FB_Register_Masks */
3769 
3770 
3771 /* FB - Peripheral instance base addresses */
3772 /** Peripheral FB base address */
3773 #define FB_BASE (0x4000C000u)
3774 /** Peripheral FB base pointer */
3775 #define FB ((FB_Type *)FB_BASE)
3776 /** Array initializer of FB peripheral base pointers */
3777 #define FB_BASES { FB }
3778 
3779 /**
3780  * @}
3781  */ /* end of group FB_Peripheral_Access_Layer */
3782 
3783 
3784 /* ----------------------------------------------------------------------------
3785  -- FMC Peripheral Access Layer
3786  ---------------------------------------------------------------------------- */
3787 
3788 /**
3789  * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
3790  * @{
3791  */
3792 
3793 /** FMC - Register Layout Typedef */
3794 typedef struct {
3795  __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
3796  __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
3797  __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
3798  uint8_t RESERVED_0[244];
3799  __IO uint32_t TAGVD[4][8]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
3800  uint8_t RESERVED_1[128];
3801  struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
3802  __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
3803  __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
3804  } SET[4][8];
3805 } FMC_Type;
3806 
3807 /* ----------------------------------------------------------------------------
3808  -- FMC Register Masks
3809  ---------------------------------------------------------------------------- */
3810 
3811 /**
3812  * @addtogroup FMC_Register_Masks FMC Register Masks
3813  * @{
3814  */
3815 
3816 /* PFAPR Bit Fields */
3817 #define FMC_PFAPR_M0AP_MASK 0x3u
3818 #define FMC_PFAPR_M0AP_SHIFT 0
3819 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
3820 #define FMC_PFAPR_M1AP_MASK 0xCu
3821 #define FMC_PFAPR_M1AP_SHIFT 2
3822 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
3823 #define FMC_PFAPR_M2AP_MASK 0x30u
3824 #define FMC_PFAPR_M2AP_SHIFT 4
3825 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
3826 #define FMC_PFAPR_M3AP_MASK 0xC0u
3827 #define FMC_PFAPR_M3AP_SHIFT 6
3828 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
3829 #define FMC_PFAPR_M4AP_MASK 0x300u
3830 #define FMC_PFAPR_M4AP_SHIFT 8
3831 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
3832 #define FMC_PFAPR_M5AP_MASK 0xC00u
3833 #define FMC_PFAPR_M5AP_SHIFT 10
3834 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
3835 #define FMC_PFAPR_M6AP_MASK 0x3000u
3836 #define FMC_PFAPR_M6AP_SHIFT 12
3837 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
3838 #define FMC_PFAPR_M7AP_MASK 0xC000u
3839 #define FMC_PFAPR_M7AP_SHIFT 14
3840 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
3841 #define FMC_PFAPR_M0PFD_MASK 0x10000u
3842 #define FMC_PFAPR_M0PFD_SHIFT 16
3843 #define FMC_PFAPR_M1PFD_MASK 0x20000u
3844 #define FMC_PFAPR_M1PFD_SHIFT 17
3845 #define FMC_PFAPR_M2PFD_MASK 0x40000u
3846 #define FMC_PFAPR_M2PFD_SHIFT 18
3847 #define FMC_PFAPR_M3PFD_MASK 0x80000u
3848 #define FMC_PFAPR_M3PFD_SHIFT 19
3849 #define FMC_PFAPR_M4PFD_MASK 0x100000u
3850 #define FMC_PFAPR_M4PFD_SHIFT 20
3851 #define FMC_PFAPR_M5PFD_MASK 0x200000u
3852 #define FMC_PFAPR_M5PFD_SHIFT 21
3853 #define FMC_PFAPR_M6PFD_MASK 0x400000u
3854 #define FMC_PFAPR_M6PFD_SHIFT 22
3855 #define FMC_PFAPR_M7PFD_MASK 0x800000u
3856 #define FMC_PFAPR_M7PFD_SHIFT 23
3857 /* PFB0CR Bit Fields */
3858 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
3859 #define FMC_PFB0CR_B0SEBE_SHIFT 0
3860 #define FMC_PFB0CR_B0IPE_MASK 0x2u
3861 #define FMC_PFB0CR_B0IPE_SHIFT 1
3862 #define FMC_PFB0CR_B0DPE_MASK 0x4u
3863 #define FMC_PFB0CR_B0DPE_SHIFT 2
3864 #define FMC_PFB0CR_B0ICE_MASK 0x8u
3865 #define FMC_PFB0CR_B0ICE_SHIFT 3
3866 #define FMC_PFB0CR_B0DCE_MASK 0x10u
3867 #define FMC_PFB0CR_B0DCE_SHIFT 4
3868 #define FMC_PFB0CR_CRC_MASK 0xE0u
3869 #define FMC_PFB0CR_CRC_SHIFT 5
3870 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
3871 #define FMC_PFB0CR_B0MW_MASK 0x60000u
3872 #define FMC_PFB0CR_B0MW_SHIFT 17
3873 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
3874 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
3875 #define FMC_PFB0CR_S_B_INV_SHIFT 19
3876 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
3877 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
3878 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
3879 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
3880 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
3881 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
3882 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
3883 #define FMC_PFB0CR_B0RWSC_SHIFT 28
3884 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
3885 /* PFB1CR Bit Fields */
3886 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
3887 #define FMC_PFB1CR_B1SEBE_SHIFT 0
3888 #define FMC_PFB1CR_B1IPE_MASK 0x2u
3889 #define FMC_PFB1CR_B1IPE_SHIFT 1
3890 #define FMC_PFB1CR_B1DPE_MASK 0x4u
3891 #define FMC_PFB1CR_B1DPE_SHIFT 2
3892 #define FMC_PFB1CR_B1ICE_MASK 0x8u
3893 #define FMC_PFB1CR_B1ICE_SHIFT 3
3894 #define FMC_PFB1CR_B1DCE_MASK 0x10u
3895 #define FMC_PFB1CR_B1DCE_SHIFT 4
3896 #define FMC_PFB1CR_B1MW_MASK 0x60000u
3897 #define FMC_PFB1CR_B1MW_SHIFT 17
3898 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
3899 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
3900 #define FMC_PFB1CR_B1RWSC_SHIFT 28
3901 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
3902 /* TAGVD Bit Fields */
3903 #define FMC_TAGVD_valid_MASK 0x1u
3904 #define FMC_TAGVD_valid_SHIFT 0
3905 #define FMC_TAGVD_tag_MASK 0x7FFC0u
3906 #define FMC_TAGVD_tag_SHIFT 6
3907 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
3908 /* DATA_U Bit Fields */
3909 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
3910 #define FMC_DATA_U_data_SHIFT 0
3911 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
3912 /* DATA_L Bit Fields */
3913 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
3914 #define FMC_DATA_L_data_SHIFT 0
3915 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
3916 
3917 /**
3918  * @}
3919  */ /* end of group FMC_Register_Masks */
3920 
3921 
3922 /* FMC - Peripheral instance base addresses */
3923 /** Peripheral FMC base address */
3924 #define FMC_BASE (0x4001F000u)
3925 /** Peripheral FMC base pointer */
3926 #define FMC ((FMC_Type *)FMC_BASE)
3927 /** Array initializer of FMC peripheral base pointers */
3928 #define FMC_BASES { FMC }
3929 
3930 /**
3931  * @}
3932  */ /* end of group FMC_Peripheral_Access_Layer */
3933 
3934 
3935 /* ----------------------------------------------------------------------------
3936  -- FTFL Peripheral Access Layer
3937  ---------------------------------------------------------------------------- */
3938 
3939 /**
3940  * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
3941  * @{
3942  */
3943 
3944 /** FTFL - Register Layout Typedef */
3945 typedef struct {
3946  __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3947  __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3948  __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3949  __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3950  __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3951  __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3952  __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3953  __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3954  __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3955  __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3956  __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3957  __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3958  __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3959  __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3960  __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3961  __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3962  __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3963  __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3964  __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3965  __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3966  uint8_t RESERVED_0[2];
3967  __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
3968  __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
3969 } FTFL_Type;
3970 
3971 /* ----------------------------------------------------------------------------
3972  -- FTFL Register Masks
3973  ---------------------------------------------------------------------------- */
3974 
3975 /**
3976  * @addtogroup FTFL_Register_Masks FTFL Register Masks
3977  * @{
3978  */
3979 
3980 /* FSTAT Bit Fields */
3981 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
3982 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
3983 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
3984 #define FTFL_FSTAT_FPVIOL_SHIFT 4
3985 #define FTFL_FSTAT_ACCERR_MASK 0x20u
3986 #define FTFL_FSTAT_ACCERR_SHIFT 5
3987 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
3988 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
3989 #define FTFL_FSTAT_CCIF_MASK 0x80u
3990 #define FTFL_FSTAT_CCIF_SHIFT 7
3991 /* FCNFG Bit Fields */
3992 #define FTFL_FCNFG_EEERDY_MASK 0x1u
3993 #define FTFL_FCNFG_EEERDY_SHIFT 0
3994 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
3995 #define FTFL_FCNFG_RAMRDY_SHIFT 1
3996 #define FTFL_FCNFG_PFLSH_MASK 0x4u
3997 #define FTFL_FCNFG_PFLSH_SHIFT 2
3998 #define FTFL_FCNFG_SWAP_MASK 0x8u
3999 #define FTFL_FCNFG_SWAP_SHIFT 3
4000 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
4001 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
4002 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
4003 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
4004 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
4005 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
4006 #define FTFL_FCNFG_CCIE_MASK 0x80u
4007 #define FTFL_FCNFG_CCIE_SHIFT 7
4008 /* FSEC Bit Fields */
4009 #define FTFL_FSEC_SEC_MASK 0x3u
4010 #define FTFL_FSEC_SEC_SHIFT 0
4011 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
4012 #define FTFL_FSEC_FSLACC_MASK 0xCu
4013 #define FTFL_FSEC_FSLACC_SHIFT 2
4014 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
4015 #define FTFL_FSEC_MEEN_MASK 0x30u
4016 #define FTFL_FSEC_MEEN_SHIFT 4
4017 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
4018 #define FTFL_FSEC_KEYEN_MASK 0xC0u
4019 #define FTFL_FSEC_KEYEN_SHIFT 6
4020 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
4021 /* FOPT Bit Fields */
4022 #define FTFL_FOPT_OPT_MASK 0xFFu
4023 #define FTFL_FOPT_OPT_SHIFT 0
4024 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
4025 /* FCCOB3 Bit Fields */
4026 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
4027 #define FTFL_FCCOB3_CCOBn_SHIFT 0
4028 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
4029 /* FCCOB2 Bit Fields */
4030 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
4031 #define FTFL_FCCOB2_CCOBn_SHIFT 0
4032 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
4033 /* FCCOB1 Bit Fields */
4034 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
4035 #define FTFL_FCCOB1_CCOBn_SHIFT 0
4036 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
4037 /* FCCOB0 Bit Fields */
4038 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
4039 #define FTFL_FCCOB0_CCOBn_SHIFT 0
4040 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
4041 /* FCCOB7 Bit Fields */
4042 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
4043 #define FTFL_FCCOB7_CCOBn_SHIFT 0
4044 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
4045 /* FCCOB6 Bit Fields */
4046 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
4047 #define FTFL_FCCOB6_CCOBn_SHIFT 0
4048 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
4049 /* FCCOB5 Bit Fields */
4050 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
4051 #define FTFL_FCCOB5_CCOBn_SHIFT 0
4052 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
4053 /* FCCOB4 Bit Fields */
4054 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
4055 #define FTFL_FCCOB4_CCOBn_SHIFT 0
4056 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
4057 /* FCCOBB Bit Fields */
4058 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
4059 #define FTFL_FCCOBB_CCOBn_SHIFT 0
4060 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
4061 /* FCCOBA Bit Fields */
4062 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
4063 #define FTFL_FCCOBA_CCOBn_SHIFT 0
4064 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
4065 /* FCCOB9 Bit Fields */
4066 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
4067 #define FTFL_FCCOB9_CCOBn_SHIFT 0
4068 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
4069 /* FCCOB8 Bit Fields */
4070 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
4071 #define FTFL_FCCOB8_CCOBn_SHIFT 0
4072 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
4073 /* FPROT3 Bit Fields */
4074 #define FTFL_FPROT3_PROT_MASK 0xFFu
4075 #define FTFL_FPROT3_PROT_SHIFT 0
4076 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
4077 /* FPROT2 Bit Fields */
4078 #define FTFL_FPROT2_PROT_MASK 0xFFu
4079 #define FTFL_FPROT2_PROT_SHIFT 0
4080 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
4081 /* FPROT1 Bit Fields */
4082 #define FTFL_FPROT1_PROT_MASK 0xFFu
4083 #define FTFL_FPROT1_PROT_SHIFT 0
4084 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
4085 /* FPROT0 Bit Fields */
4086 #define FTFL_FPROT0_PROT_MASK 0xFFu
4087 #define FTFL_FPROT0_PROT_SHIFT 0
4088 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
4089 /* FEPROT Bit Fields */
4090 #define FTFL_FEPROT_EPROT_MASK 0xFFu
4091 #define FTFL_FEPROT_EPROT_SHIFT 0
4092 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
4093 /* FDPROT Bit Fields */
4094 #define FTFL_FDPROT_DPROT_MASK 0xFFu
4095 #define FTFL_FDPROT_DPROT_SHIFT 0
4096 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
4097 
4098 /**
4099  * @}
4100  */ /* end of group FTFL_Register_Masks */
4101 
4102 
4103 /* FTFL - Peripheral instance base addresses */
4104 /** Peripheral FTFL base address */
4105 #define FTFL_BASE (0x40020000u)
4106 /** Peripheral FTFL base pointer */
4107 #define FTFL ((FTFL_Type *)FTFL_BASE)
4108 /** Array initializer of FTFL peripheral base pointers */
4109 #define FTFL_BASES { FTFL }
4110 
4111 /**
4112  * @}
4113  */ /* end of group FTFL_Peripheral_Access_Layer */
4114 
4115 
4116 /* ----------------------------------------------------------------------------
4117  -- FTM Peripheral Access Layer
4118  ---------------------------------------------------------------------------- */
4119 
4120 /**
4121  * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
4122  * @{
4123  */
4124 
4125 /** FTM - Register Layout Typedef */
4126 typedef struct {
4127  __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
4128  __IO uint32_t CNT; /**< Counter, offset: 0x4 */
4129  __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
4130  struct { /* offset: 0xC, array step: 0x8 */
4131  __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
4132  __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
4133  } CONTROLS[8];
4134  __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
4135  __I uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
4136  __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
4137  __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
4138  __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
4139  __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
4140  __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
4141  __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
4142  __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
4143  __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
4144  __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
4145  __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
4146  __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
4147  __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
4148  __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
4149  __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
4150  __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
4151  __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
4152  __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
4153  __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
4154 } FTM_Type;
4155 
4156 /* ----------------------------------------------------------------------------
4157  -- FTM Register Masks
4158  ---------------------------------------------------------------------------- */
4159 
4160 /**
4161  * @addtogroup FTM_Register_Masks FTM Register Masks
4162  * @{
4163  */
4164 
4165 /* SC Bit Fields */
4166 #define FTM_SC_PS_MASK 0x7u
4167 #define FTM_SC_PS_SHIFT 0
4168 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
4169 #define FTM_SC_CLKS_MASK 0x18u
4170 #define FTM_SC_CLKS_SHIFT 3
4171 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
4172 #define FTM_SC_CPWMS_MASK 0x20u
4173 #define FTM_SC_CPWMS_SHIFT 5
4174 #define FTM_SC_TOIE_MASK 0x40u
4175 #define FTM_SC_TOIE_SHIFT 6
4176 #define FTM_SC_TOF_MASK 0x80u
4177 #define FTM_SC_TOF_SHIFT 7
4178 /* CNT Bit Fields */
4179 #define FTM_CNT_COUNT_MASK 0xFFFFu
4180 #define FTM_CNT_COUNT_SHIFT 0
4181 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
4182 /* MOD Bit Fields */
4183 #define FTM_MOD_MOD_MASK 0xFFFFu
4184 #define FTM_MOD_MOD_SHIFT 0
4185 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
4186 /* CnSC Bit Fields */
4187 #define FTM_CnSC_DMA_MASK 0x1u
4188 #define FTM_CnSC_DMA_SHIFT 0
4189 #define FTM_CnSC_ELSA_MASK 0x4u
4190 #define FTM_CnSC_ELSA_SHIFT 2
4191 #define FTM_CnSC_ELSB_MASK 0x8u
4192 #define FTM_CnSC_ELSB_SHIFT 3
4193 #define FTM_CnSC_MSA_MASK 0x10u
4194 #define FTM_CnSC_MSA_SHIFT 4
4195 #define FTM_CnSC_MSB_MASK 0x20u
4196 #define FTM_CnSC_MSB_SHIFT 5
4197 #define FTM_CnSC_CHIE_MASK 0x40u
4198 #define FTM_CnSC_CHIE_SHIFT 6
4199 #define FTM_CnSC_CHF_MASK 0x80u
4200 #define FTM_CnSC_CHF_SHIFT 7
4201 /* CnV Bit Fields */
4202 #define FTM_CnV_VAL_MASK 0xFFFFu
4203 #define FTM_CnV_VAL_SHIFT 0
4204 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
4205 /* CNTIN Bit Fields */
4206 #define FTM_CNTIN_INIT_MASK 0xFFFFu
4207 #define FTM_CNTIN_INIT_SHIFT 0
4208 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
4209 /* STATUS Bit Fields */
4210 #define FTM_STATUS_CH0F_MASK 0x1u
4211 #define FTM_STATUS_CH0F_SHIFT 0
4212 #define FTM_STATUS_CH1F_MASK 0x2u
4213 #define FTM_STATUS_CH1F_SHIFT 1
4214 #define FTM_STATUS_CH2F_MASK 0x4u
4215 #define FTM_STATUS_CH2F_SHIFT 2
4216 #define FTM_STATUS_CH3F_MASK 0x8u
4217 #define FTM_STATUS_CH3F_SHIFT 3
4218 #define FTM_STATUS_CH4F_MASK 0x10u
4219 #define FTM_STATUS_CH4F_SHIFT 4
4220 #define FTM_STATUS_CH5F_MASK 0x20u
4221 #define FTM_STATUS_CH5F_SHIFT 5
4222 #define FTM_STATUS_CH6F_MASK 0x40u
4223 #define FTM_STATUS_CH6F_SHIFT 6
4224 #define FTM_STATUS_CH7F_MASK 0x80u
4225 #define FTM_STATUS_CH7F_SHIFT 7
4226 /* MODE Bit Fields */
4227 #define FTM_MODE_FTMEN_MASK 0x1u
4228 #define FTM_MODE_FTMEN_SHIFT 0
4229 #define FTM_MODE_INIT_MASK 0x2u
4230 #define FTM_MODE_INIT_SHIFT 1
4231 #define FTM_MODE_WPDIS_MASK 0x4u
4232 #define FTM_MODE_WPDIS_SHIFT 2
4233 #define FTM_MODE_PWMSYNC_MASK 0x8u
4234 #define FTM_MODE_PWMSYNC_SHIFT 3
4235 #define FTM_MODE_CAPTEST_MASK 0x10u
4236 #define FTM_MODE_CAPTEST_SHIFT 4
4237 #define FTM_MODE_FAULTM_MASK 0x60u
4238 #define FTM_MODE_FAULTM_SHIFT 5
4239 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
4240 #define FTM_MODE_FAULTIE_MASK 0x80u
4241 #define FTM_MODE_FAULTIE_SHIFT 7
4242 /* SYNC Bit Fields */
4243 #define FTM_SYNC_CNTMIN_MASK 0x1u
4244 #define FTM_SYNC_CNTMIN_SHIFT 0
4245 #define FTM_SYNC_CNTMAX_MASK 0x2u
4246 #define FTM_SYNC_CNTMAX_SHIFT 1
4247 #define FTM_SYNC_REINIT_MASK 0x4u
4248 #define FTM_SYNC_REINIT_SHIFT 2
4249 #define FTM_SYNC_SYNCHOM_MASK 0x8u
4250 #define FTM_SYNC_SYNCHOM_SHIFT 3
4251 #define FTM_SYNC_TRIG0_MASK 0x10u
4252 #define FTM_SYNC_TRIG0_SHIFT 4
4253 #define FTM_SYNC_TRIG1_MASK 0x20u
4254 #define FTM_SYNC_TRIG1_SHIFT 5
4255 #define FTM_SYNC_TRIG2_MASK 0x40u
4256 #define FTM_SYNC_TRIG2_SHIFT 6
4257 #define FTM_SYNC_SWSYNC_MASK 0x80u
4258 #define FTM_SYNC_SWSYNC_SHIFT 7
4259 /* OUTINIT Bit Fields */
4260 #define FTM_OUTINIT_CH0OI_MASK 0x1u
4261 #define FTM_OUTINIT_CH0OI_SHIFT 0
4262 #define FTM_OUTINIT_CH1OI_MASK 0x2u
4263 #define FTM_OUTINIT_CH1OI_SHIFT 1
4264 #define FTM_OUTINIT_CH2OI_MASK 0x4u
4265 #define FTM_OUTINIT_CH2OI_SHIFT 2
4266 #define FTM_OUTINIT_CH3OI_MASK 0x8u
4267 #define FTM_OUTINIT_CH3OI_SHIFT 3
4268 #define FTM_OUTINIT_CH4OI_MASK 0x10u
4269 #define FTM_OUTINIT_CH4OI_SHIFT 4
4270 #define FTM_OUTINIT_CH5OI_MASK 0x20u
4271 #define FTM_OUTINIT_CH5OI_SHIFT 5
4272 #define FTM_OUTINIT_CH6OI_MASK 0x40u
4273 #define FTM_OUTINIT_CH6OI_SHIFT 6
4274 #define FTM_OUTINIT_CH7OI_MASK 0x80u
4275 #define FTM_OUTINIT_CH7OI_SHIFT 7
4276 /* OUTMASK Bit Fields */
4277 #define FTM_OUTMASK_CH0OM_MASK 0x1u
4278 #define FTM_OUTMASK_CH0OM_SHIFT 0
4279 #define FTM_OUTMASK_CH1OM_MASK 0x2u
4280 #define FTM_OUTMASK_CH1OM_SHIFT 1
4281 #define FTM_OUTMASK_CH2OM_MASK 0x4u
4282 #define FTM_OUTMASK_CH2OM_SHIFT 2
4283 #define FTM_OUTMASK_CH3OM_MASK 0x8u
4284 #define FTM_OUTMASK_CH3OM_SHIFT 3
4285 #define FTM_OUTMASK_CH4OM_MASK 0x10u
4286 #define FTM_OUTMASK_CH4OM_SHIFT 4
4287 #define FTM_OUTMASK_CH5OM_MASK 0x20u
4288 #define FTM_OUTMASK_CH5OM_SHIFT 5
4289 #define FTM_OUTMASK_CH6OM_MASK 0x40u
4290 #define FTM_OUTMASK_CH6OM_SHIFT 6
4291 #define FTM_OUTMASK_CH7OM_MASK 0x80u
4292 #define FTM_OUTMASK_CH7OM_SHIFT 7
4293 /* COMBINE Bit Fields */
4294 #define FTM_COMBINE_COMBINE0_MASK 0x1u
4295 #define FTM_COMBINE_COMBINE0_SHIFT 0
4296 #define FTM_COMBINE_COMP0_MASK 0x2u
4297 #define FTM_COMBINE_COMP0_SHIFT 1
4298 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
4299 #define FTM_COMBINE_DECAPEN0_SHIFT 2
4300 #define FTM_COMBINE_DECAP0_MASK 0x8u
4301 #define FTM_COMBINE_DECAP0_SHIFT 3
4302 #define FTM_COMBINE_DTEN0_MASK 0x10u
4303 #define FTM_COMBINE_DTEN0_SHIFT 4
4304 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
4305 #define FTM_COMBINE_SYNCEN0_SHIFT 5
4306 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
4307 #define FTM_COMBINE_FAULTEN0_SHIFT 6
4308 #define FTM_COMBINE_COMBINE1_MASK 0x100u
4309 #define FTM_COMBINE_COMBINE1_SHIFT 8
4310 #define FTM_COMBINE_COMP1_MASK 0x200u
4311 #define FTM_COMBINE_COMP1_SHIFT 9
4312 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
4313 #define FTM_COMBINE_DECAPEN1_SHIFT 10
4314 #define FTM_COMBINE_DECAP1_MASK 0x800u
4315 #define FTM_COMBINE_DECAP1_SHIFT 11
4316 #define FTM_COMBINE_DTEN1_MASK 0x1000u
4317 #define FTM_COMBINE_DTEN1_SHIFT 12
4318 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
4319 #define FTM_COMBINE_SYNCEN1_SHIFT 13
4320 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
4321 #define FTM_COMBINE_FAULTEN1_SHIFT 14
4322 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
4323 #define FTM_COMBINE_COMBINE2_SHIFT 16
4324 #define FTM_COMBINE_COMP2_MASK 0x20000u
4325 #define FTM_COMBINE_COMP2_SHIFT 17
4326 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
4327 #define FTM_COMBINE_DECAPEN2_SHIFT 18
4328 #define FTM_COMBINE_DECAP2_MASK 0x80000u
4329 #define FTM_COMBINE_DECAP2_SHIFT 19
4330 #define FTM_COMBINE_DTEN2_MASK 0x100000u
4331 #define FTM_COMBINE_DTEN2_SHIFT 20
4332 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
4333 #define FTM_COMBINE_SYNCEN2_SHIFT 21
4334 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
4335 #define FTM_COMBINE_FAULTEN2_SHIFT 22
4336 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
4337 #define FTM_COMBINE_COMBINE3_SHIFT 24
4338 #define FTM_COMBINE_COMP3_MASK 0x2000000u
4339 #define FTM_COMBINE_COMP3_SHIFT 25
4340 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
4341 #define FTM_COMBINE_DECAPEN3_SHIFT 26
4342 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
4343 #define FTM_COMBINE_DECAP3_SHIFT 27
4344 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
4345 #define FTM_COMBINE_DTEN3_SHIFT 28
4346 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
4347 #define FTM_COMBINE_SYNCEN3_SHIFT 29
4348 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
4349 #define FTM_COMBINE_FAULTEN3_SHIFT 30
4350 /* DEADTIME Bit Fields */
4351 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
4352 #define FTM_DEADTIME_DTVAL_SHIFT 0
4353 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
4354 #define FTM_DEADTIME_DTPS_MASK 0xC0u
4355 #define FTM_DEADTIME_DTPS_SHIFT 6
4356 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
4357 /* EXTTRIG Bit Fields */
4358 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
4359 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
4360 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
4361 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
4362 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
4363 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
4364 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
4365 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
4366 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
4367 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
4368 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
4369 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
4370 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
4371 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
4372 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
4373 #define FTM_EXTTRIG_TRIGF_SHIFT 7
4374 /* POL Bit Fields */
4375 #define FTM_POL_POL0_MASK 0x1u
4376 #define FTM_POL_POL0_SHIFT 0
4377 #define FTM_POL_POL1_MASK 0x2u
4378 #define FTM_POL_POL1_SHIFT 1
4379 #define FTM_POL_POL2_MASK 0x4u
4380 #define FTM_POL_POL2_SHIFT 2
4381 #define FTM_POL_POL3_MASK 0x8u
4382 #define FTM_POL_POL3_SHIFT 3
4383 #define FTM_POL_POL4_MASK 0x10u
4384 #define FTM_POL_POL4_SHIFT 4
4385 #define FTM_POL_POL5_MASK 0x20u
4386 #define FTM_POL_POL5_SHIFT 5
4387 #define FTM_POL_POL6_MASK 0x40u
4388 #define FTM_POL_POL6_SHIFT 6
4389 #define FTM_POL_POL7_MASK 0x80u
4390 #define FTM_POL_POL7_SHIFT 7
4391 /* FMS Bit Fields */
4392 #define FTM_FMS_FAULTF0_MASK 0x1u
4393 #define FTM_FMS_FAULTF0_SHIFT 0
4394 #define FTM_FMS_FAULTF1_MASK 0x2u
4395 #define FTM_FMS_FAULTF1_SHIFT 1
4396 #define FTM_FMS_FAULTF2_MASK 0x4u
4397 #define FTM_FMS_FAULTF2_SHIFT 2
4398 #define FTM_FMS_FAULTF3_MASK 0x8u
4399 #define FTM_FMS_FAULTF3_SHIFT 3
4400 #define FTM_FMS_FAULTIN_MASK 0x20u
4401 #define FTM_FMS_FAULTIN_SHIFT 5
4402 #define FTM_FMS_WPEN_MASK 0x40u
4403 #define FTM_FMS_WPEN_SHIFT 6
4404 #define FTM_FMS_FAULTF_MASK 0x80u
4405 #define FTM_FMS_FAULTF_SHIFT 7
4406 /* FILTER Bit Fields */
4407 #define FTM_FILTER_CH0FVAL_MASK 0xFu
4408 #define FTM_FILTER_CH0FVAL_SHIFT 0
4409 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
4410 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
4411 #define FTM_FILTER_CH1FVAL_SHIFT 4
4412 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
4413 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
4414 #define FTM_FILTER_CH2FVAL_SHIFT 8
4415 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
4416 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
4417 #define FTM_FILTER_CH3FVAL_SHIFT 12
4418 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
4419 /* FLTCTRL Bit Fields */
4420 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
4421 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
4422 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
4423 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
4424 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
4425 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
4426 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
4427 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
4428 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
4429 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
4430 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
4431 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
4432 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
4433 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
4434 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
4435 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
4436 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
4437 #define FTM_FLTCTRL_FFVAL_SHIFT 8
4438 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
4439 /* QDCTRL Bit Fields */
4440 #define FTM_QDCTRL_QUADEN_MASK 0x1u
4441 #define FTM_QDCTRL_QUADEN_SHIFT 0
4442 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
4443 #define FTM_QDCTRL_TOFDIR_SHIFT 1
4444 #define FTM_QDCTRL_QUADIR_MASK 0x4u
4445 #define FTM_QDCTRL_QUADIR_SHIFT 2
4446 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
4447 #define FTM_QDCTRL_QUADMODE_SHIFT 3
4448 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
4449 #define FTM_QDCTRL_PHBPOL_SHIFT 4
4450 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
4451 #define FTM_QDCTRL_PHAPOL_SHIFT 5
4452 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
4453 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
4454 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
4455 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
4456 /* CONF Bit Fields */
4457 #define FTM_CONF_NUMTOF_MASK 0x1Fu
4458 #define FTM_CONF_NUMTOF_SHIFT 0
4459 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
4460 #define FTM_CONF_BDMMODE_MASK 0xC0u
4461 #define FTM_CONF_BDMMODE_SHIFT 6
4462 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
4463 #define FTM_CONF_GTBEEN_MASK 0x200u
4464 #define FTM_CONF_GTBEEN_SHIFT 9
4465 #define FTM_CONF_GTBEOUT_MASK 0x400u
4466 #define FTM_CONF_GTBEOUT_SHIFT 10
4467 /* FLTPOL Bit Fields */
4468 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
4469 #define FTM_FLTPOL_FLT0POL_SHIFT 0
4470 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
4471 #define FTM_FLTPOL_FLT1POL_SHIFT 1
4472 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
4473 #define FTM_FLTPOL_FLT2POL_SHIFT 2
4474 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
4475 #define FTM_FLTPOL_FLT3POL_SHIFT 3
4476 /* SYNCONF Bit Fields */
4477 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
4478 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
4479 #define FTM_SYNCONF_CNTINC_MASK 0x4u
4480 #define FTM_SYNCONF_CNTINC_SHIFT 2
4481 #define FTM_SYNCONF_INVC_MASK 0x10u
4482 #define FTM_SYNCONF_INVC_SHIFT 4
4483 #define FTM_SYNCONF_SWOC_MASK 0x20u
4484 #define FTM_SYNCONF_SWOC_SHIFT 5
4485 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
4486 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
4487 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
4488 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
4489 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
4490 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
4491 #define FTM_SYNCONF_SWOM_MASK 0x400u
4492 #define FTM_SYNCONF_SWOM_SHIFT 10
4493 #define FTM_SYNCONF_SWINVC_MASK 0x800u
4494 #define FTM_SYNCONF_SWINVC_SHIFT 11
4495 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
4496 #define FTM_SYNCONF_SWSOC_SHIFT 12
4497 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
4498 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
4499 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
4500 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
4501 #define FTM_SYNCONF_HWOM_MASK 0x40000u
4502 #define FTM_SYNCONF_HWOM_SHIFT 18
4503 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
4504 #define FTM_SYNCONF_HWINVC_SHIFT 19
4505 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
4506 #define FTM_SYNCONF_HWSOC_SHIFT 20
4507 /* INVCTRL Bit Fields */
4508 #define FTM_INVCTRL_INV0EN_MASK 0x1u
4509 #define FTM_INVCTRL_INV0EN_SHIFT 0
4510 #define FTM_INVCTRL_INV1EN_MASK 0x2u
4511 #define FTM_INVCTRL_INV1EN_SHIFT 1
4512 #define FTM_INVCTRL_INV2EN_MASK 0x4u
4513 #define FTM_INVCTRL_INV2EN_SHIFT 2
4514 #define FTM_INVCTRL_INV3EN_MASK 0x8u
4515 #define FTM_INVCTRL_INV3EN_SHIFT 3
4516 /* SWOCTRL Bit Fields */
4517 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
4518 #define FTM_SWOCTRL_CH0OC_SHIFT 0
4519 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
4520 #define FTM_SWOCTRL_CH1OC_SHIFT 1
4521 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
4522 #define FTM_SWOCTRL_CH2OC_SHIFT 2
4523 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
4524 #define FTM_SWOCTRL_CH3OC_SHIFT 3
4525 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
4526 #define FTM_SWOCTRL_CH4OC_SHIFT 4
4527 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
4528 #define FTM_SWOCTRL_CH5OC_SHIFT 5
4529 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
4530 #define FTM_SWOCTRL_CH6OC_SHIFT 6
4531 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
4532 #define FTM_SWOCTRL_CH7OC_SHIFT 7
4533 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
4534 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
4535 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
4536 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
4537 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
4538 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
4539 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
4540 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
4541 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
4542 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
4543 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
4544 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
4545 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
4546 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
4547 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
4548 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
4549 /* PWMLOAD Bit Fields */
4550 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
4551 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
4552 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
4553 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
4554 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
4555 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
4556 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
4557 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
4558 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
4559 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
4560 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
4561 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
4562 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
4563 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
4564 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
4565 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
4566 #define FTM_PWMLOAD_LDOK_MASK 0x200u
4567 #define FTM_PWMLOAD_LDOK_SHIFT 9
4568 
4569 /**
4570  * @}
4571  */ /* end of group FTM_Register_Masks */
4572 
4573 
4574 /* FTM - Peripheral instance base addresses */
4575 /** Peripheral FTM0 base address */
4576 #define FTM0_BASE (0x40038000u)
4577 /** Peripheral FTM0 base pointer */
4578 #define FTM0 ((FTM_Type *)FTM0_BASE)
4579 /** Peripheral FTM1 base address */
4580 #define FTM1_BASE (0x40039000u)
4581 /** Peripheral FTM1 base pointer */
4582 #define FTM1 ((FTM_Type *)FTM1_BASE)
4583 /** Peripheral FTM2 base address */
4584 #define FTM2_BASE (0x400B8000u)
4585 /** Peripheral FTM2 base pointer */
4586 #define FTM2 ((FTM_Type *)FTM2_BASE)
4587 /** Array initializer of FTM peripheral base pointers */
4588 #define FTM_BASES { FTM0, FTM1, FTM2 }
4589 
4590 /**
4591  * @}
4592  */ /* end of group FTM_Peripheral_Access_Layer */
4593 
4594 
4595 /* ----------------------------------------------------------------------------
4596  -- GPIO Peripheral Access Layer
4597  ---------------------------------------------------------------------------- */
4598 
4599 /**
4600  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
4601  * @{
4602  */
4603 
4604 /** GPIO - Register Layout Typedef */
4605 typedef struct {
4606  __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
4607  __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
4608  __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
4609  __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
4610  __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
4611  __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
4612 } GPIO_Type;
4613 
4614 /* ----------------------------------------------------------------------------
4615  -- GPIO Register Masks
4616  ---------------------------------------------------------------------------- */
4617 
4618 /**
4619  * @addtogroup GPIO_Register_Masks GPIO Register Masks
4620  * @{
4621  */
4622 
4623 /* PDOR Bit Fields */
4624 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
4625 #define GPIO_PDOR_PDO_SHIFT 0
4626 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
4627 /* PSOR Bit Fields */
4628 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
4629 #define GPIO_PSOR_PTSO_SHIFT 0
4630 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
4631 /* PCOR Bit Fields */
4632 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
4633 #define GPIO_PCOR_PTCO_SHIFT 0
4634 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
4635 /* PTOR Bit Fields */
4636 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
4637 #define GPIO_PTOR_PTTO_SHIFT 0
4638 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
4639 /* PDIR Bit Fields */
4640 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
4641 #define GPIO_PDIR_PDI_SHIFT 0
4642 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
4643 /* PDDR Bit Fields */
4644 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
4645 #define GPIO_PDDR_PDD_SHIFT 0
4646 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
4647 
4648 /**
4649  * @}
4650  */ /* end of group GPIO_Register_Masks */
4651 
4652 
4653 /* GPIO - Peripheral instance base addresses */
4654 /** Peripheral PTA base address */
4655 #define PTA_BASE (0x400FF000u)
4656 /** Peripheral PTA base pointer */
4657 #define PTA ((GPIO_Type *)PTA_BASE)
4658 /** Peripheral PTB base address */
4659 #define PTB_BASE (0x400FF040u)
4660 /** Peripheral PTB base pointer */
4661 #define PTB ((GPIO_Type *)PTB_BASE)
4662 /** Peripheral PTC base address */
4663 #define PTC_BASE (0x400FF080u)
4664 /** Peripheral PTC base pointer */
4665 #define PTC ((GPIO_Type *)PTC_BASE)
4666 /** Peripheral PTD base address */
4667 #define PTD_BASE (0x400FF0C0u)
4668 /** Peripheral PTD base pointer */
4669 #define PTD ((GPIO_Type *)PTD_BASE)
4670 /** Peripheral PTE base address */
4671 #define PTE_BASE (0x400FF100u)
4672 /** Peripheral PTE base pointer */
4673 #define PTE ((GPIO_Type *)PTE_BASE)
4674 /** Array initializer of GPIO peripheral base pointers */
4675 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
4676 
4677 /**
4678  * @}
4679  */ /* end of group GPIO_Peripheral_Access_Layer */
4680 
4681 
4682 /* ----------------------------------------------------------------------------
4683  -- I2C Peripheral Access Layer
4684  ---------------------------------------------------------------------------- */
4685 
4686 /**
4687  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
4688  * @{
4689  */
4690 
4691 /** I2C - Register Layout Typedef */
4692 typedef struct {
4693  __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
4694  __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
4695  __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
4696  __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
4697  __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
4698  __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
4699  __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
4700  __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
4701  __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
4702  __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
4703  __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
4704  __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
4705 } I2C_Type;
4706 
4707 /* ----------------------------------------------------------------------------
4708  -- I2C Register Masks
4709  ---------------------------------------------------------------------------- */
4710 
4711 /**
4712  * @addtogroup I2C_Register_Masks I2C Register Masks
4713  * @{
4714  */
4715 
4716 /* A1 Bit Fields */
4717 #define I2C_A1_AD_MASK 0xFEu
4718 #define I2C_A1_AD_SHIFT 1
4719 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
4720 /* F Bit Fields */
4721 #define I2C_F_ICR_MASK 0x3Fu
4722 #define I2C_F_ICR_SHIFT 0
4723 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
4724 #define I2C_F_MULT_MASK 0xC0u
4725 #define I2C_F_MULT_SHIFT 6
4726 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
4727 /* C1 Bit Fields */
4728 #define I2C_C1_DMAEN_MASK 0x1u
4729 #define I2C_C1_DMAEN_SHIFT 0
4730 #define I2C_C1_WUEN_MASK 0x2u
4731 #define I2C_C1_WUEN_SHIFT 1
4732 #define I2C_C1_RSTA_MASK 0x4u
4733 #define I2C_C1_RSTA_SHIFT 2
4734 #define I2C_C1_TXAK_MASK 0x8u
4735 #define I2C_C1_TXAK_SHIFT 3
4736 #define I2C_C1_TX_MASK 0x10u
4737 #define I2C_C1_TX_SHIFT 4
4738 #define I2C_C1_MST_MASK 0x20u
4739 #define I2C_C1_MST_SHIFT 5
4740 #define I2C_C1_IICIE_MASK 0x40u
4741 #define I2C_C1_IICIE_SHIFT 6
4742 #define I2C_C1_IICEN_MASK 0x80u
4743 #define I2C_C1_IICEN_SHIFT 7
4744 /* S Bit Fields */
4745 #define I2C_S_RXAK_MASK 0x1u
4746 #define I2C_S_RXAK_SHIFT 0
4747 #define I2C_S_IICIF_MASK 0x2u
4748 #define I2C_S_IICIF_SHIFT 1
4749 #define I2C_S_SRW_MASK 0x4u
4750 #define I2C_S_SRW_SHIFT 2
4751 #define I2C_S_RAM_MASK 0x8u
4752 #define I2C_S_RAM_SHIFT 3
4753 #define I2C_S_ARBL_MASK 0x10u
4754 #define I2C_S_ARBL_SHIFT 4
4755 #define I2C_S_BUSY_MASK 0x20u
4756 #define I2C_S_BUSY_SHIFT 5
4757 #define I2C_S_IAAS_MASK 0x40u
4758 #define I2C_S_IAAS_SHIFT 6
4759 #define I2C_S_TCF_MASK 0x80u
4760 #define I2C_S_TCF_SHIFT 7
4761 /* D Bit Fields */
4762 #define I2C_D_DATA_MASK 0xFFu
4763 #define I2C_D_DATA_SHIFT 0
4764 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
4765 /* C2 Bit Fields */
4766 #define I2C_C2_AD_MASK 0x7u
4767 #define I2C_C2_AD_SHIFT 0
4768 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
4769 #define I2C_C2_RMEN_MASK 0x8u
4770 #define I2C_C2_RMEN_SHIFT 3
4771 #define I2C_C2_SBRC_MASK 0x10u
4772 #define I2C_C2_SBRC_SHIFT 4
4773 #define I2C_C2_HDRS_MASK 0x20u
4774 #define I2C_C2_HDRS_SHIFT 5
4775 #define I2C_C2_ADEXT_MASK 0x40u
4776 #define I2C_C2_ADEXT_SHIFT 6
4777 #define I2C_C2_GCAEN_MASK 0x80u
4778 #define I2C_C2_GCAEN_SHIFT 7
4779 /* FLT Bit Fields */
4780 #define I2C_FLT_FLT_MASK 0x1Fu
4781 #define I2C_FLT_FLT_SHIFT 0
4782 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
4783 /* RA Bit Fields */
4784 #define I2C_RA_RAD_MASK 0xFEu
4785 #define I2C_RA_RAD_SHIFT 1
4786 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
4787 /* SMB Bit Fields */
4788 #define I2C_SMB_SHTF2IE_MASK 0x1u
4789 #define I2C_SMB_SHTF2IE_SHIFT 0
4790 #define I2C_SMB_SHTF2_MASK 0x2u
4791 #define I2C_SMB_SHTF2_SHIFT 1
4792 #define I2C_SMB_SHTF1_MASK 0x4u
4793 #define I2C_SMB_SHTF1_SHIFT 2
4794 #define I2C_SMB_SLTF_MASK 0x8u
4795 #define I2C_SMB_SLTF_SHIFT 3
4796 #define I2C_SMB_TCKSEL_MASK 0x10u
4797 #define I2C_SMB_TCKSEL_SHIFT 4
4798 #define I2C_SMB_SIICAEN_MASK 0x20u
4799 #define I2C_SMB_SIICAEN_SHIFT 5
4800 #define I2C_SMB_ALERTEN_MASK 0x40u
4801 #define I2C_SMB_ALERTEN_SHIFT 6
4802 #define I2C_SMB_FACK_MASK 0x80u
4803 #define I2C_SMB_FACK_SHIFT 7
4804 /* A2 Bit Fields */
4805 #define I2C_A2_SAD_MASK 0xFEu
4806 #define I2C_A2_SAD_SHIFT 1
4807 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
4808 /* SLTH Bit Fields */
4809 #define I2C_SLTH_SSLT_MASK 0xFFu
4810 #define I2C_SLTH_SSLT_SHIFT 0
4811 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
4812 /* SLTL Bit Fields */
4813 #define I2C_SLTL_SSLT_MASK 0xFFu
4814 #define I2C_SLTL_SSLT_SHIFT 0
4815 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
4816 
4817 /**
4818  * @}
4819  */ /* end of group I2C_Register_Masks */
4820 
4821 
4822 /* I2C - Peripheral instance base addresses */
4823 /** Peripheral I2C0 base address */
4824 #define I2C0_BASE (0x40066000u)
4825 /** Peripheral I2C0 base pointer */
4826 #define I2C0 ((I2C_Type *)I2C0_BASE)
4827 /** Peripheral I2C1 base address */
4828 #define I2C1_BASE (0x40067000u)
4829 /** Peripheral I2C1 base pointer */
4830 #define I2C1 ((I2C_Type *)I2C1_BASE)
4831 /** Array initializer of I2C peripheral base pointers */
4832 #define I2C_BASES { I2C0, I2C1 }
4833 
4834 /**
4835  * @}
4836  */ /* end of group I2C_Peripheral_Access_Layer */
4837 
4838 
4839 /* ----------------------------------------------------------------------------
4840  -- I2S Peripheral Access Layer
4841  ---------------------------------------------------------------------------- */
4842 
4843 /**
4844  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
4845  * @{
4846  */
4847 
4848 /** I2S - Register Layout Typedef */
4849 typedef struct {
4850  __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
4851  __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
4852  __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
4853  __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
4854  __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
4855  __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
4856  uint8_t RESERVED_0[8];
4857  __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
4858  uint8_t RESERVED_1[24];
4859  __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
4860  uint8_t RESERVED_2[24];
4861  __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
4862  uint8_t RESERVED_3[28];
4863  __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
4864  __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
4865  __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
4866  __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
4867  __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
4868  __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
4869  uint8_t RESERVED_4[8];
4870  __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
4871  uint8_t RESERVED_5[24];
4872  __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
4873  uint8_t RESERVED_6[24];
4874  __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
4875  uint8_t RESERVED_7[28];
4876  __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
4877  __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
4878 } I2S_Type;
4879 
4880 /* ----------------------------------------------------------------------------
4881  -- I2S Register Masks
4882  ---------------------------------------------------------------------------- */
4883 
4884 /**
4885  * @addtogroup I2S_Register_Masks I2S Register Masks
4886  * @{
4887  */
4888 
4889 /* TCSR Bit Fields */
4890 #define I2S_TCSR_FRDE_MASK 0x1u
4891 #define I2S_TCSR_FRDE_SHIFT 0
4892 #define I2S_TCSR_FWDE_MASK 0x2u
4893 #define I2S_TCSR_FWDE_SHIFT 1
4894 #define I2S_TCSR_FRIE_MASK 0x100u
4895 #define I2S_TCSR_FRIE_SHIFT 8
4896 #define I2S_TCSR_FWIE_MASK 0x200u
4897 #define I2S_TCSR_FWIE_SHIFT 9
4898 #define I2S_TCSR_FEIE_MASK 0x400u
4899 #define I2S_TCSR_FEIE_SHIFT 10
4900 #define I2S_TCSR_SEIE_MASK 0x800u
4901 #define I2S_TCSR_SEIE_SHIFT 11
4902 #define I2S_TCSR_WSIE_MASK 0x1000u
4903 #define I2S_TCSR_WSIE_SHIFT 12
4904 #define I2S_TCSR_FRF_MASK 0x10000u
4905 #define I2S_TCSR_FRF_SHIFT 16
4906 #define I2S_TCSR_FWF_MASK 0x20000u
4907 #define I2S_TCSR_FWF_SHIFT 17
4908 #define I2S_TCSR_FEF_MASK 0x40000u
4909 #define I2S_TCSR_FEF_SHIFT 18
4910 #define I2S_TCSR_SEF_MASK 0x80000u
4911 #define I2S_TCSR_SEF_SHIFT 19
4912 #define I2S_TCSR_WSF_MASK 0x100000u
4913 #define I2S_TCSR_WSF_SHIFT 20
4914 #define I2S_TCSR_SR_MASK 0x1000000u
4915 #define I2S_TCSR_SR_SHIFT 24
4916 #define I2S_TCSR_FR_MASK 0x2000000u
4917 #define I2S_TCSR_FR_SHIFT 25
4918 #define I2S_TCSR_BCE_MASK 0x10000000u
4919 #define I2S_TCSR_BCE_SHIFT 28
4920 #define I2S_TCSR_DBGE_MASK 0x20000000u
4921 #define I2S_TCSR_DBGE_SHIFT 29
4922 #define I2S_TCSR_STOPE_MASK 0x40000000u
4923 #define I2S_TCSR_STOPE_SHIFT 30
4924 #define I2S_TCSR_TE_MASK 0x80000000u
4925 #define I2S_TCSR_TE_SHIFT 31
4926 /* TCR1 Bit Fields */
4927 #define I2S_TCR1_TFW_MASK 0x7u
4928 #define I2S_TCR1_TFW_SHIFT 0
4929 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
4930 /* TCR2 Bit Fields */
4931 #define I2S_TCR2_DIV_MASK 0xFFu
4932 #define I2S_TCR2_DIV_SHIFT 0
4933 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
4934 #define I2S_TCR2_BCD_MASK 0x1000000u
4935 #define I2S_TCR2_BCD_SHIFT 24
4936 #define I2S_TCR2_BCP_MASK 0x2000000u
4937 #define I2S_TCR2_BCP_SHIFT 25
4938 #define I2S_TCR2_MSEL_MASK 0xC000000u
4939 #define I2S_TCR2_MSEL_SHIFT 26
4940 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
4941 #define I2S_TCR2_BCI_MASK 0x10000000u
4942 #define I2S_TCR2_BCI_SHIFT 28
4943 #define I2S_TCR2_BCS_MASK 0x20000000u
4944 #define I2S_TCR2_BCS_SHIFT 29
4945 #define I2S_TCR2_SYNC_MASK 0xC0000000u
4946 #define I2S_TCR2_SYNC_SHIFT 30
4947 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
4948 /* TCR3 Bit Fields */
4949 #define I2S_TCR3_WDFL_MASK 0x1Fu
4950 #define I2S_TCR3_WDFL_SHIFT 0
4951 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
4952 #define I2S_TCR3_TCE_MASK 0x30000u
4953 #define I2S_TCR3_TCE_SHIFT 16
4954 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
4955 /* TCR4 Bit Fields */
4956 #define I2S_TCR4_FSD_MASK 0x1u
4957 #define I2S_TCR4_FSD_SHIFT 0
4958 #define I2S_TCR4_FSP_MASK 0x2u
4959 #define I2S_TCR4_FSP_SHIFT 1
4960 #define I2S_TCR4_FSE_MASK 0x8u
4961 #define I2S_TCR4_FSE_SHIFT 3
4962 #define I2S_TCR4_MF_MASK 0x10u
4963 #define I2S_TCR4_MF_SHIFT 4
4964 #define I2S_TCR4_SYWD_MASK 0x1F00u
4965 #define I2S_TCR4_SYWD_SHIFT 8
4966 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
4967 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
4968 #define I2S_TCR4_FRSZ_SHIFT 16
4969 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
4970 /* TCR5 Bit Fields */
4971 #define I2S_TCR5_FBT_MASK 0x1F00u
4972 #define I2S_TCR5_FBT_SHIFT 8
4973 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
4974 #define I2S_TCR5_W0W_MASK 0x1F0000u
4975 #define I2S_TCR5_W0W_SHIFT 16
4976 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
4977 #define I2S_TCR5_WNW_MASK 0x1F000000u
4978 #define I2S_TCR5_WNW_SHIFT 24
4979 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
4980 /* TDR Bit Fields */
4981 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
4982 #define I2S_TDR_TDR_SHIFT 0
4983 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
4984 /* TFR Bit Fields */
4985 #define I2S_TFR_RFP_MASK 0xFu
4986 #define I2S_TFR_RFP_SHIFT 0
4987 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
4988 #define I2S_TFR_WFP_MASK 0xF0000u
4989 #define I2S_TFR_WFP_SHIFT 16
4990 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
4991 /* TMR Bit Fields */
4992 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
4993 #define I2S_TMR_TWM_SHIFT 0
4994 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
4995 /* RCSR Bit Fields */
4996 #define I2S_RCSR_FRDE_MASK 0x1u
4997 #define I2S_RCSR_FRDE_SHIFT 0
4998 #define I2S_RCSR_FWDE_MASK 0x2u
4999 #define I2S_RCSR_FWDE_SHIFT 1
5000 #define I2S_RCSR_FRIE_MASK 0x100u
5001 #define I2S_RCSR_FRIE_SHIFT 8
5002 #define I2S_RCSR_FWIE_MASK 0x200u
5003 #define I2S_RCSR_FWIE_SHIFT 9
5004 #define I2S_RCSR_FEIE_MASK 0x400u
5005 #define I2S_RCSR_FEIE_SHIFT 10
5006 #define I2S_RCSR_SEIE_MASK 0x800u
5007 #define I2S_RCSR_SEIE_SHIFT 11
5008 #define I2S_RCSR_WSIE_MASK 0x1000u
5009 #define I2S_RCSR_WSIE_SHIFT 12
5010 #define I2S_RCSR_FRF_MASK 0x10000u
5011 #define I2S_RCSR_FRF_SHIFT 16
5012 #define I2S_RCSR_FWF_MASK 0x20000u
5013 #define I2S_RCSR_FWF_SHIFT 17
5014 #define I2S_RCSR_FEF_MASK 0x40000u
5015 #define I2S_RCSR_FEF_SHIFT 18
5016 #define I2S_RCSR_SEF_MASK 0x80000u
5017 #define I2S_RCSR_SEF_SHIFT 19
5018 #define I2S_RCSR_WSF_MASK 0x100000u
5019 #define I2S_RCSR_WSF_SHIFT 20
5020 #define I2S_RCSR_SR_MASK 0x1000000u
5021 #define I2S_RCSR_SR_SHIFT 24
5022 #define I2S_RCSR_FR_MASK 0x2000000u
5023 #define I2S_RCSR_FR_SHIFT 25
5024 #define I2S_RCSR_BCE_MASK 0x10000000u
5025 #define I2S_RCSR_BCE_SHIFT 28
5026 #define I2S_RCSR_DBGE_MASK 0x20000000u
5027 #define I2S_RCSR_DBGE_SHIFT 29
5028 #define I2S_RCSR_STOPE_MASK 0x40000000u
5029 #define I2S_RCSR_STOPE_SHIFT 30
5030 #define I2S_RCSR_RE_MASK 0x80000000u
5031 #define I2S_RCSR_RE_SHIFT 31
5032 /* RCR1 Bit Fields */
5033 #define I2S_RCR1_RFW_MASK 0x7u
5034 #define I2S_RCR1_RFW_SHIFT 0
5035 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
5036 /* RCR2 Bit Fields */
5037 #define I2S_RCR2_DIV_MASK 0xFFu
5038 #define I2S_RCR2_DIV_SHIFT 0
5039 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
5040 #define I2S_RCR2_BCD_MASK 0x1000000u
5041 #define I2S_RCR2_BCD_SHIFT 24
5042 #define I2S_RCR2_BCP_MASK 0x2000000u
5043 #define I2S_RCR2_BCP_SHIFT 25
5044 #define I2S_RCR2_MSEL_MASK 0xC000000u
5045 #define I2S_RCR2_MSEL_SHIFT 26
5046 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
5047 #define I2S_RCR2_BCI_MASK 0x10000000u
5048 #define I2S_RCR2_BCI_SHIFT 28
5049 #define I2S_RCR2_BCS_MASK 0x20000000u
5050 #define I2S_RCR2_BCS_SHIFT 29
5051 #define I2S_RCR2_SYNC_MASK 0xC0000000u
5052 #define I2S_RCR2_SYNC_SHIFT 30
5053 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
5054 /* RCR3 Bit Fields */
5055 #define I2S_RCR3_WDFL_MASK 0x1Fu
5056 #define I2S_RCR3_WDFL_SHIFT 0
5057 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
5058 #define I2S_RCR3_RCE_MASK 0x30000u
5059 #define I2S_RCR3_RCE_SHIFT 16
5060 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
5061 /* RCR4 Bit Fields */
5062 #define I2S_RCR4_FSD_MASK 0x1u
5063 #define I2S_RCR4_FSD_SHIFT 0
5064 #define I2S_RCR4_FSP_MASK 0x2u
5065 #define I2S_RCR4_FSP_SHIFT 1
5066 #define I2S_RCR4_FSE_MASK 0x8u
5067 #define I2S_RCR4_FSE_SHIFT 3
5068 #define I2S_RCR4_MF_MASK 0x10u
5069 #define I2S_RCR4_MF_SHIFT 4
5070 #define I2S_RCR4_SYWD_MASK 0x1F00u
5071 #define I2S_RCR4_SYWD_SHIFT 8
5072 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
5073 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
5074 #define I2S_RCR4_FRSZ_SHIFT 16
5075 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
5076 /* RCR5 Bit Fields */
5077 #define I2S_RCR5_FBT_MASK 0x1F00u
5078 #define I2S_RCR5_FBT_SHIFT 8
5079 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
5080 #define I2S_RCR5_W0W_MASK 0x1F0000u
5081 #define I2S_RCR5_W0W_SHIFT 16
5082 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
5083 #define I2S_RCR5_WNW_MASK 0x1F000000u
5084 #define I2S_RCR5_WNW_SHIFT 24
5085 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
5086 /* RDR Bit Fields */
5087 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
5088 #define I2S_RDR_RDR_SHIFT 0
5089 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
5090 /* RFR Bit Fields */
5091 #define I2S_RFR_RFP_MASK 0xFu
5092 #define I2S_RFR_RFP_SHIFT 0
5093 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
5094 #define I2S_RFR_WFP_MASK 0xF0000u
5095 #define I2S_RFR_WFP_SHIFT 16
5096 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
5097 /* RMR Bit Fields */
5098 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
5099 #define I2S_RMR_RWM_SHIFT 0
5100 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
5101 /* MCR Bit Fields */
5102 #define I2S_MCR_MICS_MASK 0x3000000u
5103 #define I2S_MCR_MICS_SHIFT 24
5104 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
5105 #define I2S_MCR_MOE_MASK 0x40000000u
5106 #define I2S_MCR_MOE_SHIFT 30
5107 #define I2S_MCR_DUF_MASK 0x80000000u
5108 #define I2S_MCR_DUF_SHIFT 31
5109 /* MDR Bit Fields */
5110 #define I2S_MDR_DIVIDE_MASK 0xFFFu
5111 #define I2S_MDR_DIVIDE_SHIFT 0
5112 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
5113 #define I2S_MDR_FRACT_MASK 0xFF000u
5114 #define I2S_MDR_FRACT_SHIFT 12
5115 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
5116 
5117 /**
5118  * @}
5119  */ /* end of group I2S_Register_Masks */
5120 
5121 
5122 /* I2S - Peripheral instance base addresses */
5123 /** Peripheral I2S0 base address */
5124 #define I2S0_BASE (0x4002F000u)
5125 /** Peripheral I2S0 base pointer */
5126 #define I2S0 ((I2S_Type *)I2S0_BASE)
5127 /** Array initializer of I2S peripheral base pointers */
5128 #define I2S_BASES { I2S0 }
5129 
5130 /**
5131  * @}
5132  */ /* end of group I2S_Peripheral_Access_Layer */
5133 
5134 
5135 /* ----------------------------------------------------------------------------
5136  -- LLWU Peripheral Access Layer
5137  ---------------------------------------------------------------------------- */
5138 
5139 /**
5140  * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
5141  * @{
5142  */
5143 
5144 /** LLWU - Register Layout Typedef */
5145 typedef struct {
5146  __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
5147  __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
5148  __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
5149  __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
5150  __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
5151  __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
5152  __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
5153  __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
5154  __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
5155  __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
5156  __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
5157 } LLWU_Type;
5158 
5159 /* ----------------------------------------------------------------------------
5160  -- LLWU Register Masks
5161  ---------------------------------------------------------------------------- */
5162 
5163 /**
5164  * @addtogroup LLWU_Register_Masks LLWU Register Masks
5165  * @{
5166  */
5167 
5168 /* PE1 Bit Fields */
5169 #define LLWU_PE1_WUPE0_MASK 0x3u
5170 #define LLWU_PE1_WUPE0_SHIFT 0
5171 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
5172 #define LLWU_PE1_WUPE1_MASK 0xCu
5173 #define LLWU_PE1_WUPE1_SHIFT 2
5174 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
5175 #define LLWU_PE1_WUPE2_MASK 0x30u
5176 #define LLWU_PE1_WUPE2_SHIFT 4
5177 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
5178 #define LLWU_PE1_WUPE3_MASK 0xC0u
5179 #define LLWU_PE1_WUPE3_SHIFT 6
5180 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
5181 /* PE2 Bit Fields */
5182 #define LLWU_PE2_WUPE4_MASK 0x3u
5183 #define LLWU_PE2_WUPE4_SHIFT 0
5184 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
5185 #define LLWU_PE2_WUPE5_MASK 0xCu
5186 #define LLWU_PE2_WUPE5_SHIFT 2
5187 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
5188 #define LLWU_PE2_WUPE6_MASK 0x30u
5189 #define LLWU_PE2_WUPE6_SHIFT 4
5190 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
5191 #define LLWU_PE2_WUPE7_MASK 0xC0u
5192 #define LLWU_PE2_WUPE7_SHIFT 6
5193 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
5194 /* PE3 Bit Fields */
5195 #define LLWU_PE3_WUPE8_MASK 0x3u
5196 #define LLWU_PE3_WUPE8_SHIFT 0
5197 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
5198 #define LLWU_PE3_WUPE9_MASK 0xCu
5199 #define LLWU_PE3_WUPE9_SHIFT 2
5200 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
5201 #define LLWU_PE3_WUPE10_MASK 0x30u
5202 #define LLWU_PE3_WUPE10_SHIFT 4
5203 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
5204 #define LLWU_PE3_WUPE11_MASK 0xC0u
5205 #define LLWU_PE3_WUPE11_SHIFT 6
5206 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
5207 /* PE4 Bit Fields */
5208 #define LLWU_PE4_WUPE12_MASK 0x3u
5209 #define LLWU_PE4_WUPE12_SHIFT 0
5210 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
5211 #define LLWU_PE4_WUPE13_MASK 0xCu
5212 #define LLWU_PE4_WUPE13_SHIFT 2
5213 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
5214 #define LLWU_PE4_WUPE14_MASK 0x30u
5215 #define LLWU_PE4_WUPE14_SHIFT 4
5216 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
5217 #define LLWU_PE4_WUPE15_MASK 0xC0u
5218 #define LLWU_PE4_WUPE15_SHIFT 6
5219 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
5220 /* ME Bit Fields */
5221 #define LLWU_ME_WUME0_MASK 0x1u
5222 #define LLWU_ME_WUME0_SHIFT 0
5223 #define LLWU_ME_WUME1_MASK 0x2u
5224 #define LLWU_ME_WUME1_SHIFT 1
5225 #define LLWU_ME_WUME2_MASK 0x4u
5226 #define LLWU_ME_WUME2_SHIFT 2
5227 #define LLWU_ME_WUME3_MASK 0x8u
5228 #define LLWU_ME_WUME3_SHIFT 3
5229 #define LLWU_ME_WUME4_MASK 0x10u
5230 #define LLWU_ME_WUME4_SHIFT 4
5231 #define LLWU_ME_WUME5_MASK 0x20u
5232 #define LLWU_ME_WUME5_SHIFT 5
5233 #define LLWU_ME_WUME6_MASK 0x40u
5234 #define LLWU_ME_WUME6_SHIFT 6
5235 #define LLWU_ME_WUME7_MASK 0x80u
5236 #define LLWU_ME_WUME7_SHIFT 7
5237 /* F1 Bit Fields */
5238 #define LLWU_F1_WUF0_MASK 0x1u
5239 #define LLWU_F1_WUF0_SHIFT 0
5240 #define LLWU_F1_WUF1_MASK 0x2u
5241 #define LLWU_F1_WUF1_SHIFT 1
5242 #define LLWU_F1_WUF2_MASK 0x4u
5243 #define LLWU_F1_WUF2_SHIFT 2
5244 #define LLWU_F1_WUF3_MASK 0x8u
5245 #define LLWU_F1_WUF3_SHIFT 3
5246 #define LLWU_F1_WUF4_MASK 0x10u
5247 #define LLWU_F1_WUF4_SHIFT 4
5248 #define LLWU_F1_WUF5_MASK 0x20u
5249 #define LLWU_F1_WUF5_SHIFT 5
5250 #define LLWU_F1_WUF6_MASK 0x40u
5251 #define LLWU_F1_WUF6_SHIFT 6
5252 #define LLWU_F1_WUF7_MASK 0x80u
5253 #define LLWU_F1_WUF7_SHIFT 7
5254 /* F2 Bit Fields */
5255 #define LLWU_F2_WUF8_MASK 0x1u
5256 #define LLWU_F2_WUF8_SHIFT 0
5257 #define LLWU_F2_WUF9_MASK 0x2u
5258 #define LLWU_F2_WUF9_SHIFT 1
5259 #define LLWU_F2_WUF10_MASK 0x4u
5260 #define LLWU_F2_WUF10_SHIFT 2
5261 #define LLWU_F2_WUF11_MASK 0x8u
5262 #define LLWU_F2_WUF11_SHIFT 3
5263 #define LLWU_F2_WUF12_MASK 0x10u
5264 #define LLWU_F2_WUF12_SHIFT 4
5265 #define LLWU_F2_WUF13_MASK 0x20u
5266 #define LLWU_F2_WUF13_SHIFT 5
5267 #define LLWU_F2_WUF14_MASK 0x40u
5268 #define LLWU_F2_WUF14_SHIFT 6
5269 #define LLWU_F2_WUF15_MASK 0x80u
5270 #define LLWU_F2_WUF15_SHIFT 7
5271 /* F3 Bit Fields */
5272 #define LLWU_F3_MWUF0_MASK 0x1u
5273 #define LLWU_F3_MWUF0_SHIFT 0
5274 #define LLWU_F3_MWUF1_MASK 0x2u
5275 #define LLWU_F3_MWUF1_SHIFT 1
5276 #define LLWU_F3_MWUF2_MASK 0x4u
5277 #define LLWU_F3_MWUF2_SHIFT 2
5278 #define LLWU_F3_MWUF3_MASK 0x8u
5279 #define LLWU_F3_MWUF3_SHIFT 3
5280 #define LLWU_F3_MWUF4_MASK 0x10u
5281 #define LLWU_F3_MWUF4_SHIFT 4
5282 #define LLWU_F3_MWUF5_MASK 0x20u
5283 #define LLWU_F3_MWUF5_SHIFT 5
5284 #define LLWU_F3_MWUF6_MASK 0x40u
5285 #define LLWU_F3_MWUF6_SHIFT 6
5286 #define LLWU_F3_MWUF7_MASK 0x80u
5287 #define LLWU_F3_MWUF7_SHIFT 7
5288 /* FILT1 Bit Fields */
5289 #define LLWU_FILT1_FILTSEL_MASK 0xFu
5290 #define LLWU_FILT1_FILTSEL_SHIFT 0
5291 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
5292 #define LLWU_FILT1_FILTE_MASK 0x60u
5293 #define LLWU_FILT1_FILTE_SHIFT 5
5294 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
5295 #define LLWU_FILT1_FILTF_MASK 0x80u
5296 #define LLWU_FILT1_FILTF_SHIFT 7
5297 /* FILT2 Bit Fields */
5298 #define LLWU_FILT2_FILTSEL_MASK 0xFu
5299 #define LLWU_FILT2_FILTSEL_SHIFT 0
5300 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
5301 #define LLWU_FILT2_FILTE_MASK 0x60u
5302 #define LLWU_FILT2_FILTE_SHIFT 5
5303 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
5304 #define LLWU_FILT2_FILTF_MASK 0x80u
5305 #define LLWU_FILT2_FILTF_SHIFT 7
5306 /* RST Bit Fields */
5307 #define LLWU_RST_RSTFILT_MASK 0x1u
5308 #define LLWU_RST_RSTFILT_SHIFT 0
5309 #define LLWU_RST_LLRSTE_MASK 0x2u
5310 #define LLWU_RST_LLRSTE_SHIFT 1
5311 
5312 /**
5313  * @}
5314  */ /* end of group LLWU_Register_Masks */
5315 
5316 
5317 /* LLWU - Peripheral instance base addresses */
5318 /** Peripheral LLWU base address */
5319 #define LLWU_BASE (0x4007C000u)
5320 /** Peripheral LLWU base pointer */
5321 #define LLWU ((LLWU_Type *)LLWU_BASE)
5322 /** Array initializer of LLWU peripheral base pointers */
5323 #define LLWU_BASES { LLWU }
5324 
5325 /**
5326  * @}
5327  */ /* end of group LLWU_Peripheral_Access_Layer */
5328 
5329 
5330 /* ----------------------------------------------------------------------------
5331  -- LPTMR Peripheral Access Layer
5332  ---------------------------------------------------------------------------- */
5333 
5334 /**
5335  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
5336  * @{
5337  */
5338 
5339 /** LPTMR - Register Layout Typedef */
5340 typedef struct {
5341  __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
5342  __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
5343  __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
5344  __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
5345 } LPTMR_Type;
5346 
5347 /* ----------------------------------------------------------------------------
5348  -- LPTMR Register Masks
5349  ---------------------------------------------------------------------------- */
5350 
5351 /**
5352  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
5353  * @{
5354  */
5355 
5356 /* CSR Bit Fields */
5357 #define LPTMR_CSR_TEN_MASK 0x1u
5358 #define LPTMR_CSR_TEN_SHIFT 0
5359 #define LPTMR_CSR_TMS_MASK 0x2u
5360 #define LPTMR_CSR_TMS_SHIFT 1
5361 #define LPTMR_CSR_TFC_MASK 0x4u
5362 #define LPTMR_CSR_TFC_SHIFT 2
5363 #define LPTMR_CSR_TPP_MASK 0x8u
5364 #define LPTMR_CSR_TPP_SHIFT 3
5365 #define LPTMR_CSR_TPS_MASK 0x30u
5366 #define LPTMR_CSR_TPS_SHIFT 4
5367 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
5368 #define LPTMR_CSR_TIE_MASK 0x40u
5369 #define LPTMR_CSR_TIE_SHIFT 6
5370 #define LPTMR_CSR_TCF_MASK 0x80u
5371 #define LPTMR_CSR_TCF_SHIFT 7
5372 /* PSR Bit Fields */
5373 #define LPTMR_PSR_PCS_MASK 0x3u
5374 #define LPTMR_PSR_PCS_SHIFT 0
5375 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
5376 #define LPTMR_PSR_PBYP_MASK 0x4u
5377 #define LPTMR_PSR_PBYP_SHIFT 2
5378 #define LPTMR_PSR_PRESCALE_MASK 0x78u
5379 #define LPTMR_PSR_PRESCALE_SHIFT 3
5380 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
5381 /* CMR Bit Fields */
5382 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
5383 #define LPTMR_CMR_COMPARE_SHIFT 0
5384 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
5385 /* CNR Bit Fields */
5386 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
5387 #define LPTMR_CNR_COUNTER_SHIFT 0
5388 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
5389 
5390 /**
5391  * @}
5392  */ /* end of group LPTMR_Register_Masks */
5393 
5394 
5395 /* LPTMR - Peripheral instance base addresses */
5396 /** Peripheral LPTMR0 base address */
5397 #define LPTMR0_BASE (0x40040000u)
5398 /** Peripheral LPTMR0 base pointer */
5399 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
5400 /** Array initializer of LPTMR peripheral base pointers */
5401 #define LPTMR_BASES { LPTMR0 }
5402 
5403 /**
5404  * @}
5405  */ /* end of group LPTMR_Peripheral_Access_Layer */
5406 
5407 
5408 /* ----------------------------------------------------------------------------
5409  -- MCG Peripheral Access Layer
5410  ---------------------------------------------------------------------------- */
5411 
5412 /**
5413  * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
5414  * @{
5415  */
5416 
5417 /** MCG - Register Layout Typedef */
5418 typedef struct {
5419  __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
5420  __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
5421  __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
5422  __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
5423  __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
5424  __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
5425  __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
5426  uint8_t RESERVED_0[1];
5427  __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
5428  uint8_t RESERVED_1[1];
5429  __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
5430  __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
5431  __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
5432  __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
5433  __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
5434  __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
5435 } MCG_Type;
5436 
5437 /* ----------------------------------------------------------------------------
5438  -- MCG Register Masks
5439  ---------------------------------------------------------------------------- */
5440 
5441 /**
5442  * @addtogroup MCG_Register_Masks MCG Register Masks
5443  * @{
5444  */
5445 
5446 /* C1 Bit Fields */
5447 #define MCG_C1_IREFSTEN_MASK 0x1u
5448 #define MCG_C1_IREFSTEN_SHIFT 0
5449 #define MCG_C1_IRCLKEN_MASK 0x2u
5450 #define MCG_C1_IRCLKEN_SHIFT 1
5451 #define MCG_C1_IREFS_MASK 0x4u
5452 #define MCG_C1_IREFS_SHIFT 2
5453 #define MCG_C1_FRDIV_MASK 0x38u
5454 #define MCG_C1_FRDIV_SHIFT 3
5455 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
5456 #define MCG_C1_CLKS_MASK 0xC0u
5457 #define MCG_C1_CLKS_SHIFT 6
5458 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
5459 /* C2 Bit Fields */
5460 #define MCG_C2_IRCS_MASK 0x1u
5461 #define MCG_C2_IRCS_SHIFT 0
5462 #define MCG_C2_LP_MASK 0x2u
5463 #define MCG_C2_LP_SHIFT 1
5464 #define MCG_C2_EREFS0_MASK 0x4u
5465 #define MCG_C2_EREFS0_SHIFT 2
5466 #define MCG_C2_HGO0_MASK 0x8u
5467 #define MCG_C2_HGO0_SHIFT 3
5468 #define MCG_C2_RANGE0_MASK 0x30u
5469 #define MCG_C2_RANGE0_SHIFT 4
5470 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
5471 #define MCG_C2_LOCRE0_MASK 0x80u
5472 #define MCG_C2_LOCRE0_SHIFT 7
5473 /* C3 Bit Fields */
5474 #define MCG_C3_SCTRIM_MASK 0xFFu
5475 #define MCG_C3_SCTRIM_SHIFT 0
5476 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
5477 /* C4 Bit Fields */
5478 #define MCG_C4_SCFTRIM_MASK 0x1u
5479 #define MCG_C4_SCFTRIM_SHIFT 0
5480 #define MCG_C4_FCTRIM_MASK 0x1Eu
5481 #define MCG_C4_FCTRIM_SHIFT 1
5482 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
5483 #define MCG_C4_DRST_DRS_MASK 0x60u
5484 #define MCG_C4_DRST_DRS_SHIFT 5
5485 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
5486 #define MCG_C4_DMX32_MASK 0x80u
5487 #define MCG_C4_DMX32_SHIFT 7
5488 /* C5 Bit Fields */
5489 #define MCG_C5_PRDIV0_MASK 0x1Fu
5490 #define MCG_C5_PRDIV0_SHIFT 0
5491 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
5492 #define MCG_C5_PLLSTEN0_MASK 0x20u
5493 #define MCG_C5_PLLSTEN0_SHIFT 5
5494 #define MCG_C5_PLLCLKEN0_MASK 0x40u
5495 #define MCG_C5_PLLCLKEN0_SHIFT 6
5496 /* C6 Bit Fields */
5497 #define MCG_C6_VDIV0_MASK 0x1Fu
5498 #define MCG_C6_VDIV0_SHIFT 0
5499 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
5500 #define MCG_C6_CME0_MASK 0x20u
5501 #define MCG_C6_CME0_SHIFT 5
5502 #define MCG_C6_PLLS_MASK 0x40u
5503 #define MCG_C6_PLLS_SHIFT 6
5504 #define MCG_C6_LOLIE0_MASK 0x80u
5505 #define MCG_C6_LOLIE0_SHIFT 7
5506 /* S Bit Fields */
5507 #define MCG_S_IRCST_MASK 0x1u
5508 #define MCG_S_IRCST_SHIFT 0
5509 #define MCG_S_OSCINIT0_MASK 0x2u
5510 #define MCG_S_OSCINIT0_SHIFT 1
5511 #define MCG_S_CLKST_MASK 0xCu
5512 #define MCG_S_CLKST_SHIFT 2
5513 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
5514 #define MCG_S_IREFST_MASK 0x10u
5515 #define MCG_S_IREFST_SHIFT 4
5516 #define MCG_S_PLLST_MASK 0x20u
5517 #define MCG_S_PLLST_SHIFT 5
5518 #define MCG_S_LOCK0_MASK 0x40u
5519 #define MCG_S_LOCK0_SHIFT 6
5520 #define MCG_S_LOLS_MASK 0x80u
5521 #define MCG_S_LOLS_SHIFT 7
5522 /* SC Bit Fields */
5523 #define MCG_SC_LOCS0_MASK 0x1u
5524 #define MCG_SC_LOCS0_SHIFT 0
5525 #define MCG_SC_FCRDIV_MASK 0xEu
5526 #define MCG_SC_FCRDIV_SHIFT 1
5527 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
5528 #define MCG_SC_FLTPRSRV_MASK 0x10u
5529 #define MCG_SC_FLTPRSRV_SHIFT 4
5530 #define MCG_SC_ATMF_MASK 0x20u
5531 #define MCG_SC_ATMF_SHIFT 5
5532 #define MCG_SC_ATMS_MASK 0x40u
5533 #define MCG_SC_ATMS_SHIFT 6
5534 #define MCG_SC_ATME_MASK 0x80u
5535 #define MCG_SC_ATME_SHIFT 7
5536 /* ATCVH Bit Fields */
5537 #define MCG_ATCVH_ATCVH_MASK 0xFFu
5538 #define MCG_ATCVH_ATCVH_SHIFT 0
5539 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
5540 /* ATCVL Bit Fields */
5541 #define MCG_ATCVL_ATCVL_MASK 0xFFu
5542 #define MCG_ATCVL_ATCVL_SHIFT 0
5543 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
5544 /* C7 Bit Fields */
5545 #define MCG_C7_OSCSEL_MASK 0x1u
5546 #define MCG_C7_OSCSEL_SHIFT 0
5547 /* C8 Bit Fields */
5548 #define MCG_C8_LOCS1_MASK 0x1u
5549 #define MCG_C8_LOCS1_SHIFT 0
5550 #define MCG_C8_CME1_MASK 0x20u
5551 #define MCG_C8_CME1_SHIFT 5
5552 #define MCG_C8_LOLRE_MASK 0x40u
5553 #define MCG_C8_LOLRE_SHIFT 6
5554 #define MCG_C8_LOCRE1_MASK 0x80u
5555 #define MCG_C8_LOCRE1_SHIFT 7
5556 
5557 /**
5558  * @}
5559  */ /* end of group MCG_Register_Masks */
5560 
5561 
5562 /* MCG - Peripheral instance base addresses */
5563 /** Peripheral MCG base address */
5564 #define MCG_BASE (0x40064000u)
5565 /** Peripheral MCG base pointer */
5566 #define MCG ((MCG_Type *)MCG_BASE)
5567 /** Array initializer of MCG peripheral base pointers */
5568 #define MCG_BASES { MCG }
5569 
5570 /**
5571  * @}
5572  */ /* end of group MCG_Peripheral_Access_Layer */
5573 
5574 
5575 /* ----------------------------------------------------------------------------
5576  -- MCM Peripheral Access Layer
5577  ---------------------------------------------------------------------------- */
5578 
5579 /**
5580  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
5581  * @{
5582  */
5583 
5584 /** MCM - Register Layout Typedef */
5585 typedef struct {
5586  uint8_t RESERVED_0[8];
5587  __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
5588  __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
5589  __IO uint32_t CR; /**< Control Register, offset: 0xC */
5590  __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x10 */
5591  __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
5592  __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
5593  __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
5594  uint8_t RESERVED_1[16];
5595  __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
5596 } MCM_Type;
5597 
5598 /* ----------------------------------------------------------------------------
5599  -- MCM Register Masks
5600  ---------------------------------------------------------------------------- */
5601 
5602 /**
5603  * @addtogroup MCM_Register_Masks MCM Register Masks
5604  * @{
5605  */
5606 
5607 /* PLASC Bit Fields */
5608 #define MCM_PLASC_ASC_MASK 0xFFu
5609 #define MCM_PLASC_ASC_SHIFT 0
5610 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
5611 /* PLAMC Bit Fields */
5612 #define MCM_PLAMC_AMC_MASK 0xFFu
5613 #define MCM_PLAMC_AMC_SHIFT 0
5614 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
5615 /* CR Bit Fields */
5616 #define MCM_CR_SRAMUAP_MASK 0x3000000u
5617 #define MCM_CR_SRAMUAP_SHIFT 24
5618 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
5619 #define MCM_CR_SRAMUWP_MASK 0x4000000u
5620 #define MCM_CR_SRAMUWP_SHIFT 26
5621 #define MCM_CR_SRAMLAP_MASK 0x30000000u
5622 #define MCM_CR_SRAMLAP_SHIFT 28
5623 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
5624 #define MCM_CR_SRAMLWP_MASK 0x40000000u
5625 #define MCM_CR_SRAMLWP_SHIFT 30
5626 /* ISR Bit Fields */
5627 #define MCM_ISR_IRQ_MASK 0x2u
5628 #define MCM_ISR_IRQ_SHIFT 1
5629 #define MCM_ISR_NMI_MASK 0x4u
5630 #define MCM_ISR_NMI_SHIFT 2
5631 #define MCM_ISR_DHREQ_MASK 0x8u
5632 #define MCM_ISR_DHREQ_SHIFT 3
5633 /* ETBCC Bit Fields */
5634 #define MCM_ETBCC_CNTEN_MASK 0x1u
5635 #define MCM_ETBCC_CNTEN_SHIFT 0
5636 #define MCM_ETBCC_RSPT_MASK 0x6u
5637 #define MCM_ETBCC_RSPT_SHIFT 1
5638 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
5639 #define MCM_ETBCC_RLRQ_MASK 0x8u
5640 #define MCM_ETBCC_RLRQ_SHIFT 3
5641 #define MCM_ETBCC_ETDIS_MASK 0x10u
5642 #define MCM_ETBCC_ETDIS_SHIFT 4
5643 #define MCM_ETBCC_ITDIS_MASK 0x20u
5644 #define MCM_ETBCC_ITDIS_SHIFT 5
5645 /* ETBRL Bit Fields */
5646 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
5647 #define MCM_ETBRL_RELOAD_SHIFT 0
5648 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
5649 /* ETBCNT Bit Fields */
5650 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
5651 #define MCM_ETBCNT_COUNTER_SHIFT 0
5652 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
5653 /* PID Bit Fields */
5654 #define MCM_PID_PID_MASK 0xFFu
5655 #define MCM_PID_PID_SHIFT 0
5656 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
5657 
5658 /**
5659  * @}
5660  */ /* end of group MCM_Register_Masks */
5661 
5662 
5663 /* MCM - Peripheral instance base addresses */
5664 /** Peripheral MCM base address */
5665 #define MCM_BASE (0xE0080000u)
5666 /** Peripheral MCM base pointer */
5667 #define MCM ((MCM_Type *)MCM_BASE)
5668 /** Array initializer of MCM peripheral base pointers */
5669 #define MCM_BASES { MCM }
5670 
5671 /**
5672  * @}
5673  */ /* end of group MCM_Peripheral_Access_Layer */
5674 
5675 
5676 /* ----------------------------------------------------------------------------
5677  -- MPU Peripheral Access Layer
5678  ---------------------------------------------------------------------------- */
5679 
5680 /**
5681  * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
5682  * @{
5683  */
5684 
5685 /** MPU - Register Layout Typedef */
5686 typedef struct {
5687  __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
5688  uint8_t RESERVED_0[12];
5689  struct { /* offset: 0x10, array step: 0x8 */
5690  __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
5691  __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
5692  } SP[5];
5693  uint8_t RESERVED_1[968];
5694  __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
5695  uint8_t RESERVED_2[832];
5696  __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
5697 } MPU_Type;
5698 
5699 /* ----------------------------------------------------------------------------
5700  -- MPU Register Masks
5701  ---------------------------------------------------------------------------- */
5702 
5703 /**
5704  * @addtogroup MPU_Register_Masks MPU Register Masks
5705  * @{
5706  */
5707 
5708 /* CESR Bit Fields */
5709 #define MPU_CESR_VLD_MASK 0x1u
5710 #define MPU_CESR_VLD_SHIFT 0
5711 #define MPU_CESR_NRGD_MASK 0xF00u
5712 #define MPU_CESR_NRGD_SHIFT 8
5713 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
5714 #define MPU_CESR_NSP_MASK 0xF000u
5715 #define MPU_CESR_NSP_SHIFT 12
5716 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
5717 #define MPU_CESR_HRL_MASK 0xF0000u
5718 #define MPU_CESR_HRL_SHIFT 16
5719 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
5720 #define MPU_CESR_SPERR_MASK 0xF8000000u
5721 #define MPU_CESR_SPERR_SHIFT 27
5722 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
5723 /* EAR Bit Fields */
5724 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
5725 #define MPU_EAR_EADDR_SHIFT 0
5726 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
5727 /* EDR Bit Fields */
5728 #define MPU_EDR_ERW_MASK 0x1u
5729 #define MPU_EDR_ERW_SHIFT 0
5730 #define MPU_EDR_EATTR_MASK 0xEu
5731 #define MPU_EDR_EATTR_SHIFT 1
5732 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
5733 #define MPU_EDR_EMN_MASK 0xF0u
5734 #define MPU_EDR_EMN_SHIFT 4
5735 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
5736 #define MPU_EDR_EACD_MASK 0xFFFF0000u
5737 #define MPU_EDR_EACD_SHIFT 16
5738 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
5739 /* WORD Bit Fields */
5740 #define MPU_WORD_M0UM_MASK 0x7u
5741 #define MPU_WORD_M0UM_SHIFT 0
5742 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
5743 #define MPU_WORD_VLD_MASK 0x1u
5744 #define MPU_WORD_VLD_SHIFT 0
5745 #define MPU_WORD_M0SM_MASK 0x18u
5746 #define MPU_WORD_M0SM_SHIFT 3
5747 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
5748 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
5749 #define MPU_WORD_ENDADDR_SHIFT 5
5750 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
5751 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
5752 #define MPU_WORD_SRTADDR_SHIFT 5
5753 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
5754 #define MPU_WORD_M1UM_MASK 0x1C0u
5755 #define MPU_WORD_M1UM_SHIFT 6
5756 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
5757 #define MPU_WORD_M1SM_MASK 0x600u
5758 #define MPU_WORD_M1SM_SHIFT 9
5759 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
5760 #define MPU_WORD_M2UM_MASK 0x7000u
5761 #define MPU_WORD_M2UM_SHIFT 12
5762 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
5763 #define MPU_WORD_M2SM_MASK 0x18000u
5764 #define MPU_WORD_M2SM_SHIFT 15
5765 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
5766 #define MPU_WORD_M3UM_MASK 0x1C0000u
5767 #define MPU_WORD_M3UM_SHIFT 18
5768 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
5769 #define MPU_WORD_M3SM_MASK 0x600000u
5770 #define MPU_WORD_M3SM_SHIFT 21
5771 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
5772 #define MPU_WORD_M4WE_MASK 0x1000000u
5773 #define MPU_WORD_M4WE_SHIFT 24
5774 #define MPU_WORD_M4RE_MASK 0x2000000u
5775 #define MPU_WORD_M4RE_SHIFT 25
5776 #define MPU_WORD_M5WE_MASK 0x4000000u
5777 #define MPU_WORD_M5WE_SHIFT 26
5778 #define MPU_WORD_M5RE_MASK 0x8000000u
5779 #define MPU_WORD_M5RE_SHIFT 27
5780 #define MPU_WORD_M6WE_MASK 0x10000000u
5781 #define MPU_WORD_M6WE_SHIFT 28
5782 #define MPU_WORD_M6RE_MASK 0x20000000u
5783 #define MPU_WORD_M6RE_SHIFT 29
5784 #define MPU_WORD_M7WE_MASK 0x40000000u
5785 #define MPU_WORD_M7WE_SHIFT 30
5786 #define MPU_WORD_M7RE_MASK 0x80000000u
5787 #define MPU_WORD_M7RE_SHIFT 31
5788 /* RGDAAC Bit Fields */
5789 #define MPU_RGDAAC_M0UM_MASK 0x7u
5790 #define MPU_RGDAAC_M0UM_SHIFT 0
5791 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
5792 #define MPU_RGDAAC_M0SM_MASK 0x18u
5793 #define MPU_RGDAAC_M0SM_SHIFT 3
5794 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
5795 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
5796 #define MPU_RGDAAC_M1UM_SHIFT 6
5797 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
5798 #define MPU_RGDAAC_M1SM_MASK 0x600u
5799 #define MPU_RGDAAC_M1SM_SHIFT 9
5800 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
5801 #define MPU_RGDAAC_M2UM_MASK 0x7000u
5802 #define MPU_RGDAAC_M2UM_SHIFT 12
5803 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
5804 #define MPU_RGDAAC_M2SM_MASK 0x18000u
5805 #define MPU_RGDAAC_M2SM_SHIFT 15
5806 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
5807 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
5808 #define MPU_RGDAAC_M3UM_SHIFT 18
5809 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
5810 #define MPU_RGDAAC_M3SM_MASK 0x600000u
5811 #define MPU_RGDAAC_M3SM_SHIFT 21
5812 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
5813 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
5814 #define MPU_RGDAAC_M4WE_SHIFT 24
5815 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
5816 #define MPU_RGDAAC_M4RE_SHIFT 25
5817 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
5818 #define MPU_RGDAAC_M5WE_SHIFT 26
5819 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
5820 #define MPU_RGDAAC_M5RE_SHIFT 27
5821 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
5822 #define MPU_RGDAAC_M6WE_SHIFT 28
5823 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
5824 #define MPU_RGDAAC_M6RE_SHIFT 29
5825 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
5826 #define MPU_RGDAAC_M7WE_SHIFT 30
5827 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
5828 #define MPU_RGDAAC_M7RE_SHIFT 31
5829 
5830 /**
5831  * @}
5832  */ /* end of group MPU_Register_Masks */
5833 
5834 
5835 /* MPU - Peripheral instance base addresses */
5836 /** Peripheral MPU base address */
5837 #define MPU_BASE (0x4000D000u)
5838 /** Peripheral MPU base pointer */
5839 #define MPU ((MPU_Type *)MPU_BASE)
5840 /** Array initializer of MPU peripheral base pointers */
5841 #define MPU_BASES { MPU }
5842 
5843 /**
5844  * @}
5845  */ /* end of group MPU_Peripheral_Access_Layer */
5846 
5847 
5848 /* ----------------------------------------------------------------------------
5849  -- NV Peripheral Access Layer
5850  ---------------------------------------------------------------------------- */
5851 
5852 /**
5853  * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
5854  * @{
5855  */
5856 
5857 /** NV - Register Layout Typedef */
5858 typedef struct {
5859  __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
5860  __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
5861  __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
5862  __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
5863  __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
5864  __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
5865  __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
5866  __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
5867  __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
5868  __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
5869  __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
5870  __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
5871  __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
5872  __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
5873  __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
5874  __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
5875 } NV_Type;
5876 
5877 /* ----------------------------------------------------------------------------
5878  -- NV Register Masks
5879  ---------------------------------------------------------------------------- */
5880 
5881 /**
5882  * @addtogroup NV_Register_Masks NV Register Masks
5883  * @{
5884  */
5885 
5886 /* BACKKEY3 Bit Fields */
5887 #define NV_BACKKEY3_KEY_MASK 0xFFu
5888 #define NV_BACKKEY3_KEY_SHIFT 0
5889 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
5890 /* BACKKEY2 Bit Fields */
5891 #define NV_BACKKEY2_KEY_MASK 0xFFu
5892 #define NV_BACKKEY2_KEY_SHIFT 0
5893 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
5894 /* BACKKEY1 Bit Fields */
5895 #define NV_BACKKEY1_KEY_MASK 0xFFu
5896 #define NV_BACKKEY1_KEY_SHIFT 0
5897 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
5898 /* BACKKEY0 Bit Fields */
5899 #define NV_BACKKEY0_KEY_MASK 0xFFu
5900 #define NV_BACKKEY0_KEY_SHIFT 0
5901 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
5902 /* BACKKEY7 Bit Fields */
5903 #define NV_BACKKEY7_KEY_MASK 0xFFu
5904 #define NV_BACKKEY7_KEY_SHIFT 0
5905 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
5906 /* BACKKEY6 Bit Fields */
5907 #define NV_BACKKEY6_KEY_MASK 0xFFu
5908 #define NV_BACKKEY6_KEY_SHIFT 0
5909 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
5910 /* BACKKEY5 Bit Fields */
5911 #define NV_BACKKEY5_KEY_MASK 0xFFu
5912 #define NV_BACKKEY5_KEY_SHIFT 0
5913 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
5914 /* BACKKEY4 Bit Fields */
5915 #define NV_BACKKEY4_KEY_MASK 0xFFu
5916 #define NV_BACKKEY4_KEY_SHIFT 0
5917 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
5918 /* FPROT3 Bit Fields */
5919 #define NV_FPROT3_PROT_MASK 0xFFu
5920 #define NV_FPROT3_PROT_SHIFT 0
5921 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
5922 /* FPROT2 Bit Fields */
5923 #define NV_FPROT2_PROT_MASK 0xFFu
5924 #define NV_FPROT2_PROT_SHIFT 0
5925 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
5926 /* FPROT1 Bit Fields */
5927 #define NV_FPROT1_PROT_MASK 0xFFu
5928 #define NV_FPROT1_PROT_SHIFT 0
5929 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
5930 /* FPROT0 Bit Fields */
5931 #define NV_FPROT0_PROT_MASK 0xFFu
5932 #define NV_FPROT0_PROT_SHIFT 0
5933 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
5934 /* FSEC Bit Fields */
5935 #define NV_FSEC_SEC_MASK 0x3u
5936 #define NV_FSEC_SEC_SHIFT 0
5937 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
5938 #define NV_FSEC_FSLACC_MASK 0xCu
5939 #define NV_FSEC_FSLACC_SHIFT 2
5940 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
5941 #define NV_FSEC_MEEN_MASK 0x30u
5942 #define NV_FSEC_MEEN_SHIFT 4
5943 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
5944 #define NV_FSEC_KEYEN_MASK 0xC0u
5945 #define NV_FSEC_KEYEN_SHIFT 6
5946 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
5947 /* FOPT Bit Fields */
5948 #define NV_FOPT_LPBOOT_MASK 0x1u
5949 #define NV_FOPT_LPBOOT_SHIFT 0
5950 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
5951 #define NV_FOPT_EZPORT_DIS_SHIFT 1
5952 /* FEPROT Bit Fields */
5953 #define NV_FEPROT_EPROT_MASK 0xFFu
5954 #define NV_FEPROT_EPROT_SHIFT 0
5955 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
5956 /* FDPROT Bit Fields */
5957 #define NV_FDPROT_DPROT_MASK 0xFFu
5958 #define NV_FDPROT_DPROT_SHIFT 0
5959 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
5960 
5961 /**
5962  * @}
5963  */ /* end of group NV_Register_Masks */
5964 
5965 
5966 /* NV - Peripheral instance base addresses */
5967 /** Peripheral FTFL_FlashConfig base address */
5968 #define FTFL_FlashConfig_BASE (0x400u)
5969 /** Peripheral FTFL_FlashConfig base pointer */
5970 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
5971 /** Array initializer of NV peripheral base pointers */
5972 #define NV_BASES { FTFL_FlashConfig }
5973 
5974 /**
5975  * @}
5976  */ /* end of group NV_Peripheral_Access_Layer */
5977 
5978 
5979 /* ----------------------------------------------------------------------------
5980  -- OSC Peripheral Access Layer
5981  ---------------------------------------------------------------------------- */
5982 
5983 /**
5984  * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
5985  * @{
5986  */
5987 
5988 /** OSC - Register Layout Typedef */
5989 typedef struct {
5990  __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
5991 } OSC_Type;
5992 
5993 /* ----------------------------------------------------------------------------
5994  -- OSC Register Masks
5995  ---------------------------------------------------------------------------- */
5996 
5997 /**
5998  * @addtogroup OSC_Register_Masks OSC Register Masks
5999  * @{
6000  */
6001 
6002 /* CR Bit Fields */
6003 #define OSC_CR_SC16P_MASK 0x1u
6004 #define OSC_CR_SC16P_SHIFT 0
6005 #define OSC_CR_SC8P_MASK 0x2u
6006 #define OSC_CR_SC8P_SHIFT 1
6007 #define OSC_CR_SC4P_MASK 0x4u
6008 #define OSC_CR_SC4P_SHIFT 2
6009 #define OSC_CR_SC2P_MASK 0x8u
6010 #define OSC_CR_SC2P_SHIFT 3
6011 #define OSC_CR_EREFSTEN_MASK 0x20u
6012 #define OSC_CR_EREFSTEN_SHIFT 5
6013 #define OSC_CR_ERCLKEN_MASK 0x80u
6014 #define OSC_CR_ERCLKEN_SHIFT 7
6015 
6016 /**
6017  * @}
6018  */ /* end of group OSC_Register_Masks */
6019 
6020 
6021 /* OSC - Peripheral instance base addresses */
6022 /** Peripheral OSC base address */
6023 #define OSC_BASE (0x40065000u)
6024 /** Peripheral OSC base pointer */
6025 #define OSC ((OSC_Type *)OSC_BASE)
6026 /** Array initializer of OSC peripheral base pointers */
6027 #define OSC_BASES { OSC }
6028 
6029 /**
6030  * @}
6031  */ /* end of group OSC_Peripheral_Access_Layer */
6032 
6033 
6034 /* ----------------------------------------------------------------------------
6035  -- PDB Peripheral Access Layer
6036  ---------------------------------------------------------------------------- */
6037 
6038 /**
6039  * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
6040  * @{
6041  */
6042 
6043 /** PDB - Register Layout Typedef */
6044 typedef struct {
6045  __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
6046  __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
6047  __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
6048  __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
6049  struct { /* offset: 0x10, array step: 0x28 */
6050  __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
6051  __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */
6052  __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
6053  uint8_t RESERVED_0[24];
6054  } CH[2];
6055  uint8_t RESERVED_0[240];
6056  struct { /* offset: 0x150, array step: 0x8 */
6057  __IO uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */
6058  __IO uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */
6059  } DAC[2];
6060  uint8_t RESERVED_1[48];
6061  __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
6062  __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
6063 } PDB_Type;
6064 
6065 /* ----------------------------------------------------------------------------
6066  -- PDB Register Masks
6067  ---------------------------------------------------------------------------- */
6068 
6069 /**
6070  * @addtogroup PDB_Register_Masks PDB Register Masks
6071  * @{
6072  */
6073 
6074 /* SC Bit Fields */
6075 #define PDB_SC_LDOK_MASK 0x1u
6076 #define PDB_SC_LDOK_SHIFT 0
6077 #define PDB_SC_CONT_MASK 0x2u
6078 #define PDB_SC_CONT_SHIFT 1
6079 #define PDB_SC_MULT_MASK 0xCu
6080 #define PDB_SC_MULT_SHIFT 2
6081 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
6082 #define PDB_SC_PDBIE_MASK 0x20u
6083 #define PDB_SC_PDBIE_SHIFT 5
6084 #define PDB_SC_PDBIF_MASK 0x40u
6085 #define PDB_SC_PDBIF_SHIFT 6
6086 #define PDB_SC_PDBEN_MASK 0x80u
6087 #define PDB_SC_PDBEN_SHIFT 7
6088 #define PDB_SC_TRGSEL_MASK 0xF00u
6089 #define PDB_SC_TRGSEL_SHIFT 8
6090 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
6091 #define PDB_SC_PRESCALER_MASK 0x7000u
6092 #define PDB_SC_PRESCALER_SHIFT 12
6093 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
6094 #define PDB_SC_DMAEN_MASK 0x8000u
6095 #define PDB_SC_DMAEN_SHIFT 15
6096 #define PDB_SC_SWTRIG_MASK 0x10000u
6097 #define PDB_SC_SWTRIG_SHIFT 16
6098 #define PDB_SC_PDBEIE_MASK 0x20000u
6099 #define PDB_SC_PDBEIE_SHIFT 17
6100 #define PDB_SC_LDMOD_MASK 0xC0000u
6101 #define PDB_SC_LDMOD_SHIFT 18
6102 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
6103 /* MOD Bit Fields */
6104 #define PDB_MOD_MOD_MASK 0xFFFFu
6105 #define PDB_MOD_MOD_SHIFT 0
6106 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
6107 /* CNT Bit Fields */
6108 #define PDB_CNT_CNT_MASK 0xFFFFu
6109 #define PDB_CNT_CNT_SHIFT 0
6110 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
6111 /* IDLY Bit Fields */
6112 #define PDB_IDLY_IDLY_MASK 0xFFFFu
6113 #define PDB_IDLY_IDLY_SHIFT 0
6114 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
6115 /* C1 Bit Fields */
6116 #define PDB_C1_EN_MASK 0xFFu
6117 #define PDB_C1_EN_SHIFT 0
6118 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
6119 #define PDB_C1_TOS_MASK 0xFF00u
6120 #define PDB_C1_TOS_SHIFT 8
6121 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
6122 #define PDB_C1_BB_MASK 0xFF0000u
6123 #define PDB_C1_BB_SHIFT 16
6124 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
6125 /* S Bit Fields */
6126 #define PDB_S_ERR_MASK 0xFFu
6127 #define PDB_S_ERR_SHIFT 0
6128 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
6129 #define PDB_S_CF_MASK 0xFF0000u
6130 #define PDB_S_CF_SHIFT 16
6131 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
6132 /* DLY Bit Fields */
6133 #define PDB_DLY_DLY_MASK 0xFFFFu
6134 #define PDB_DLY_DLY_SHIFT 0
6135 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
6136 /* INTC Bit Fields */
6137 #define PDB_INTC_TOE_MASK 0x1u
6138 #define PDB_INTC_TOE_SHIFT 0
6139 #define PDB_INTC_EXT_MASK 0x2u
6140 #define PDB_INTC_EXT_SHIFT 1
6141 /* INT Bit Fields */
6142 #define PDB_INT_INT_MASK 0xFFFFu
6143 #define PDB_INT_INT_SHIFT 0
6144 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
6145 /* POEN Bit Fields */
6146 #define PDB_POEN_POEN_MASK 0xFFu
6147 #define PDB_POEN_POEN_SHIFT 0
6148 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
6149 /* PODLY Bit Fields */
6150 #define PDB_PODLY_DLY2_MASK 0xFFFFu
6151 #define PDB_PODLY_DLY2_SHIFT 0
6152 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
6153 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
6154 #define PDB_PODLY_DLY1_SHIFT 16
6155 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
6156 
6157 /**
6158  * @}
6159  */ /* end of group PDB_Register_Masks */
6160 
6161 
6162 /* PDB - Peripheral instance base addresses */
6163 /** Peripheral PDB0 base address */
6164 #define PDB0_BASE (0x40036000u)
6165 /** Peripheral PDB0 base pointer */
6166 #define PDB0 ((PDB_Type *)PDB0_BASE)
6167 /** Array initializer of PDB peripheral base pointers */
6168 #define PDB_BASES { PDB0 }
6169 
6170 /**
6171  * @}
6172  */ /* end of group PDB_Peripheral_Access_Layer */
6173 
6174 
6175 /* ----------------------------------------------------------------------------
6176  -- PIT Peripheral Access Layer
6177  ---------------------------------------------------------------------------- */
6178 
6179 /**
6180  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
6181  * @{
6182  */
6183 
6184 /** PIT - Register Layout Typedef */
6185 typedef struct {
6186  __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
6187  uint8_t RESERVED_0[252];
6188  struct { /* offset: 0x100, array step: 0x10 */
6189  __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
6190  __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
6191  __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
6192  __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
6193  } CHANNEL[4];
6194 } PIT_Type;
6195 
6196 /* ----------------------------------------------------------------------------
6197  -- PIT Register Masks
6198  ---------------------------------------------------------------------------- */
6199 
6200 /**
6201  * @addtogroup PIT_Register_Masks PIT Register Masks
6202  * @{
6203  */
6204 
6205 /* MCR Bit Fields */
6206 #define PIT_MCR_FRZ_MASK 0x1u
6207 #define PIT_MCR_FRZ_SHIFT 0
6208 #define PIT_MCR_MDIS_MASK 0x2u
6209 #define PIT_MCR_MDIS_SHIFT 1
6210 /* LDVAL Bit Fields */
6211 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
6212 #define PIT_LDVAL_TSV_SHIFT 0
6213 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
6214 /* CVAL Bit Fields */
6215 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
6216 #define PIT_CVAL_TVL_SHIFT 0
6217 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
6218 /* TCTRL Bit Fields */
6219 #define PIT_TCTRL_TEN_MASK 0x1u
6220 #define PIT_TCTRL_TEN_SHIFT 0
6221 #define PIT_TCTRL_TIE_MASK 0x2u
6222 #define PIT_TCTRL_TIE_SHIFT 1
6223 #define PIT_TCTRL_CHN_MASK 0x4u
6224 #define PIT_TCTRL_CHN_SHIFT 2
6225 /* TFLG Bit Fields */
6226 #define PIT_TFLG_TIF_MASK 0x1u
6227 #define PIT_TFLG_TIF_SHIFT 0
6228 
6229 /**
6230  * @}
6231  */ /* end of group PIT_Register_Masks */
6232 
6233 
6234 /* PIT - Peripheral instance base addresses */
6235 /** Peripheral PIT base address */
6236 #define PIT_BASE (0x40037000u)
6237 /** Peripheral PIT base pointer */
6238 #define PIT ((PIT_Type *)PIT_BASE)
6239 /** Array initializer of PIT peripheral base pointers */
6240 #define PIT_BASES { PIT }
6241 
6242 /**
6243  * @}
6244  */ /* end of group PIT_Peripheral_Access_Layer */
6245 
6246 
6247 /* ----------------------------------------------------------------------------
6248  -- PMC Peripheral Access Layer
6249  ---------------------------------------------------------------------------- */
6250 
6251 /**
6252  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
6253  * @{
6254  */
6255 
6256 /** PMC - Register Layout Typedef */
6257 typedef struct {
6258  __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
6259  __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
6260  __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
6261 } PMC_Type;
6262 
6263 /* ----------------------------------------------------------------------------
6264  -- PMC Register Masks
6265  ---------------------------------------------------------------------------- */
6266 
6267 /**
6268  * @addtogroup PMC_Register_Masks PMC Register Masks
6269  * @{
6270  */
6271 
6272 /* LVDSC1 Bit Fields */
6273 #define PMC_LVDSC1_LVDV_MASK 0x3u
6274 #define PMC_LVDSC1_LVDV_SHIFT 0
6275 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
6276 #define PMC_LVDSC1_LVDRE_MASK 0x10u
6277 #define PMC_LVDSC1_LVDRE_SHIFT 4
6278 #define PMC_LVDSC1_LVDIE_MASK 0x20u
6279 #define PMC_LVDSC1_LVDIE_SHIFT 5
6280 #define PMC_LVDSC1_LVDACK_MASK 0x40u
6281 #define PMC_LVDSC1_LVDACK_SHIFT 6
6282 #define PMC_LVDSC1_LVDF_MASK 0x80u
6283 #define PMC_LVDSC1_LVDF_SHIFT 7
6284 /* LVDSC2 Bit Fields */
6285 #define PMC_LVDSC2_LVWV_MASK 0x3u
6286 #define PMC_LVDSC2_LVWV_SHIFT 0
6287 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
6288 #define PMC_LVDSC2_LVWIE_MASK 0x20u
6289 #define PMC_LVDSC2_LVWIE_SHIFT 5
6290 #define PMC_LVDSC2_LVWACK_MASK 0x40u
6291 #define PMC_LVDSC2_LVWACK_SHIFT 6
6292 #define PMC_LVDSC2_LVWF_MASK 0x80u
6293 #define PMC_LVDSC2_LVWF_SHIFT 7
6294 /* REGSC Bit Fields */
6295 #define PMC_REGSC_BGBE_MASK 0x1u
6296 #define PMC_REGSC_BGBE_SHIFT 0
6297 #define PMC_REGSC_REGONS_MASK 0x4u
6298 #define PMC_REGSC_REGONS_SHIFT 2
6299 #define PMC_REGSC_ACKISO_MASK 0x8u
6300 #define PMC_REGSC_ACKISO_SHIFT 3
6301 #define PMC_REGSC_BGEN_MASK 0x10u
6302 #define PMC_REGSC_BGEN_SHIFT 4
6303 
6304 /**
6305  * @}
6306  */ /* end of group PMC_Register_Masks */
6307 
6308 
6309 /* PMC - Peripheral instance base addresses */
6310 /** Peripheral PMC base address */
6311 #define PMC_BASE (0x4007D000u)
6312 /** Peripheral PMC base pointer */
6313 #define PMC ((PMC_Type *)PMC_BASE)
6314 /** Array initializer of PMC peripheral base pointers */
6315 #define PMC_BASES { PMC }
6316 
6317 /**
6318  * @}
6319  */ /* end of group PMC_Peripheral_Access_Layer */
6320 
6321 
6322 /* ----------------------------------------------------------------------------
6323  -- PORT Peripheral Access Layer
6324  ---------------------------------------------------------------------------- */
6325 
6326 /**
6327  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
6328  * @{
6329  */
6330 
6331 /** PORT - Register Layout Typedef */
6332 typedef struct {
6333  __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
6334  __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
6335  __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
6336  uint8_t RESERVED_0[24];
6337  __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
6338  uint8_t RESERVED_1[28];
6339  __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
6340  __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
6341  __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
6342 } PORT_Type;
6343 
6344 /* ----------------------------------------------------------------------------
6345  -- PORT Register Masks
6346  ---------------------------------------------------------------------------- */
6347 
6348 /**
6349  * @addtogroup PORT_Register_Masks PORT Register Masks
6350  * @{
6351  */
6352 
6353 /* PCR Bit Fields */
6354 #define PORT_PCR_PS_MASK 0x1u
6355 #define PORT_PCR_PS_SHIFT 0
6356 #define PORT_PCR_PE_MASK 0x2u
6357 #define PORT_PCR_PE_SHIFT 1
6358 #define PORT_PCR_SRE_MASK 0x4u
6359 #define PORT_PCR_SRE_SHIFT 2
6360 #define PORT_PCR_PFE_MASK 0x10u
6361 #define PORT_PCR_PFE_SHIFT 4
6362 #define PORT_PCR_ODE_MASK 0x20u
6363 #define PORT_PCR_ODE_SHIFT 5
6364 #define PORT_PCR_DSE_MASK 0x40u
6365 #define PORT_PCR_DSE_SHIFT 6
6366 #define PORT_PCR_MUX_MASK 0x700u
6367 #define PORT_PCR_MUX_SHIFT 8
6368 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
6369 #define PORT_PCR_LK_MASK 0x8000u
6370 #define PORT_PCR_LK_SHIFT 15
6371 #define PORT_PCR_IRQC_MASK 0xF0000u
6372 #define PORT_PCR_IRQC_SHIFT 16
6373 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
6374 #define PORT_PCR_ISF_MASK 0x1000000u
6375 #define PORT_PCR_ISF_SHIFT 24
6376 /* GPCLR Bit Fields */
6377 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
6378 #define PORT_GPCLR_GPWD_SHIFT 0
6379 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
6380 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
6381 #define PORT_GPCLR_GPWE_SHIFT 16
6382 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
6383 /* GPCHR Bit Fields */
6384 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
6385 #define PORT_GPCHR_GPWD_SHIFT 0
6386 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
6387 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
6388 #define PORT_GPCHR_GPWE_SHIFT 16
6389 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
6390 /* ISFR Bit Fields */
6391 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
6392 #define PORT_ISFR_ISF_SHIFT 0
6393 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
6394 /* DFER Bit Fields */
6395 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
6396 #define PORT_DFER_DFE_SHIFT 0
6397 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
6398 /* DFCR Bit Fields */
6399 #define PORT_DFCR_CS_MASK 0x1u
6400 #define PORT_DFCR_CS_SHIFT 0
6401 /* DFWR Bit Fields */
6402 #define PORT_DFWR_FILT_MASK 0x1Fu
6403 #define PORT_DFWR_FILT_SHIFT 0
6404 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
6405 
6406 /**
6407  * @}
6408  */ /* end of group PORT_Register_Masks */
6409 
6410 
6411 /* PORT - Peripheral instance base addresses */
6412 /** Peripheral PORTA base address */
6413 #define PORTA_BASE (0x40049000u)
6414 /** Peripheral PORTA base pointer */
6415 #define PORTA ((PORT_Type *)PORTA_BASE)
6416 /** Peripheral PORTB base address */
6417 #define PORTB_BASE (0x4004A000u)
6418 /** Peripheral PORTB base pointer */
6419 #define PORTB ((PORT_Type *)PORTB_BASE)
6420 /** Peripheral PORTC base address */
6421 #define PORTC_BASE (0x4004B000u)
6422 /** Peripheral PORTC base pointer */
6423 #define PORTC ((PORT_Type *)PORTC_BASE)
6424 /** Peripheral PORTD base address */
6425 #define PORTD_BASE (0x4004C000u)
6426 /** Peripheral PORTD base pointer */
6427 #define PORTD ((PORT_Type *)PORTD_BASE)
6428 /** Peripheral PORTE base address */
6429 #define PORTE_BASE (0x4004D000u)
6430 /** Peripheral PORTE base pointer */
6431 #define PORTE ((PORT_Type *)PORTE_BASE)
6432 /** Array initializer of PORT peripheral base pointers */
6433 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
6434 
6435 /**
6436  * @}
6437  */ /* end of group PORT_Peripheral_Access_Layer */
6438 
6439 
6440 /* ----------------------------------------------------------------------------
6441  -- RCM Peripheral Access Layer
6442  ---------------------------------------------------------------------------- */
6443 
6444 /**
6445  * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
6446  * @{
6447  */
6448 
6449 /** RCM - Register Layout Typedef */
6450 typedef struct {
6451  __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
6452  __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
6453  uint8_t RESERVED_0[2];
6454  __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
6455  __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
6456  uint8_t RESERVED_1[1];
6457  __I uint8_t MR; /**< Mode Register, offset: 0x7 */
6458 } RCM_Type;
6459 
6460 /* ----------------------------------------------------------------------------
6461  -- RCM Register Masks
6462  ---------------------------------------------------------------------------- */
6463 
6464 /**
6465  * @addtogroup RCM_Register_Masks RCM Register Masks
6466  * @{
6467  */
6468 
6469 /* SRS0 Bit Fields */
6470 #define RCM_SRS0_WAKEUP_MASK 0x1u
6471 #define RCM_SRS0_WAKEUP_SHIFT 0
6472 #define RCM_SRS0_LVD_MASK 0x2u
6473 #define RCM_SRS0_LVD_SHIFT 1
6474 #define RCM_SRS0_LOC_MASK 0x4u
6475 #define RCM_SRS0_LOC_SHIFT 2
6476 #define RCM_SRS0_LOL_MASK 0x8u
6477 #define RCM_SRS0_LOL_SHIFT 3
6478 #define RCM_SRS0_WDOG_MASK 0x20u
6479 #define RCM_SRS0_WDOG_SHIFT 5
6480 #define RCM_SRS0_PIN_MASK 0x40u
6481 #define RCM_SRS0_PIN_SHIFT 6
6482 #define RCM_SRS0_POR_MASK 0x80u
6483 #define RCM_SRS0_POR_SHIFT 7
6484 /* SRS1 Bit Fields */
6485 #define RCM_SRS1_JTAG_MASK 0x1u
6486 #define RCM_SRS1_JTAG_SHIFT 0
6487 #define RCM_SRS1_LOCKUP_MASK 0x2u
6488 #define RCM_SRS1_LOCKUP_SHIFT 1
6489 #define RCM_SRS1_SW_MASK 0x4u
6490 #define RCM_SRS1_SW_SHIFT 2
6491 #define RCM_SRS1_MDM_AP_MASK 0x8u
6492 #define RCM_SRS1_MDM_AP_SHIFT 3
6493 #define RCM_SRS1_EZPT_MASK 0x10u
6494 #define RCM_SRS1_EZPT_SHIFT 4
6495 #define RCM_SRS1_SACKERR_MASK 0x20u
6496 #define RCM_SRS1_SACKERR_SHIFT 5
6497 /* RPFC Bit Fields */
6498 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
6499 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
6500 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
6501 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
6502 #define RCM_RPFC_RSTFLTSS_SHIFT 2
6503 /* RPFW Bit Fields */
6504 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
6505 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
6506 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
6507 /* MR Bit Fields */
6508 #define RCM_MR_EZP_MS_MASK 0x2u
6509 #define RCM_MR_EZP_MS_SHIFT 1
6510 
6511 /**
6512  * @}
6513  */ /* end of group RCM_Register_Masks */
6514 
6515 
6516 /* RCM - Peripheral instance base addresses */
6517 /** Peripheral RCM base address */
6518 #define RCM_BASE (0x4007F000u)
6519 /** Peripheral RCM base pointer */
6520 #define RCM ((RCM_Type *)RCM_BASE)
6521 /** Array initializer of RCM peripheral base pointers */
6522 #define RCM_BASES { RCM }
6523 
6524 /**
6525  * @}
6526  */ /* end of group RCM_Peripheral_Access_Layer */
6527 
6528 
6529 /* ----------------------------------------------------------------------------
6530  -- RFSYS Peripheral Access Layer
6531  ---------------------------------------------------------------------------- */
6532 
6533 /**
6534  * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
6535  * @{
6536  */
6537 
6538 /** RFSYS - Register Layout Typedef */
6539 typedef struct {
6540  __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
6541 } RFSYS_Type;
6542 
6543 /* ----------------------------------------------------------------------------
6544  -- RFSYS Register Masks
6545  ---------------------------------------------------------------------------- */
6546 
6547 /**
6548  * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
6549  * @{
6550  */
6551 
6552 /* REG Bit Fields */
6553 #define RFSYS_REG_LL_MASK 0xFFu
6554 #define RFSYS_REG_LL_SHIFT 0
6555 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
6556 #define RFSYS_REG_LH_MASK 0xFF00u
6557 #define RFSYS_REG_LH_SHIFT 8
6558 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
6559 #define RFSYS_REG_HL_MASK 0xFF0000u
6560 #define RFSYS_REG_HL_SHIFT 16
6561 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
6562 #define RFSYS_REG_HH_MASK 0xFF000000u
6563 #define RFSYS_REG_HH_SHIFT 24
6564 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
6565 
6566 /**
6567  * @}
6568  */ /* end of group RFSYS_Register_Masks */
6569 
6570 
6571 /* RFSYS - Peripheral instance base addresses */
6572 /** Peripheral RFSYS base address */
6573 #define RFSYS_BASE (0x40041000u)
6574 /** Peripheral RFSYS base pointer */
6575 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
6576 /** Array initializer of RFSYS peripheral base pointers */
6577 #define RFSYS_BASES { RFSYS }
6578 
6579 /**
6580  * @}
6581  */ /* end of group RFSYS_Peripheral_Access_Layer */
6582 
6583 
6584 /* ----------------------------------------------------------------------------
6585  -- RFVBAT Peripheral Access Layer
6586  ---------------------------------------------------------------------------- */
6587 
6588 /**
6589  * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
6590  * @{
6591  */
6592 
6593 /** RFVBAT - Register Layout Typedef */
6594 typedef struct {
6595  __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
6596 } RFVBAT_Type;
6597 
6598 /* ----------------------------------------------------------------------------
6599  -- RFVBAT Register Masks
6600  ---------------------------------------------------------------------------- */
6601 
6602 /**
6603  * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
6604  * @{
6605  */
6606 
6607 /* REG Bit Fields */
6608 #define RFVBAT_REG_LL_MASK 0xFFu
6609 #define RFVBAT_REG_LL_SHIFT 0
6610 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
6611 #define RFVBAT_REG_LH_MASK 0xFF00u
6612 #define RFVBAT_REG_LH_SHIFT 8
6613 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
6614 #define RFVBAT_REG_HL_MASK 0xFF0000u
6615 #define RFVBAT_REG_HL_SHIFT 16
6616 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
6617 #define RFVBAT_REG_HH_MASK 0xFF000000u
6618 #define RFVBAT_REG_HH_SHIFT 24
6619 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
6620 
6621 /**
6622  * @}
6623  */ /* end of group RFVBAT_Register_Masks */
6624 
6625 
6626 /* RFVBAT - Peripheral instance base addresses */
6627 /** Peripheral RFVBAT base address */
6628 #define RFVBAT_BASE (0x4003E000u)
6629 /** Peripheral RFVBAT base pointer */
6630 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
6631 /** Array initializer of RFVBAT peripheral base pointers */
6632 #define RFVBAT_BASES { RFVBAT }
6633 
6634 /**
6635  * @}
6636  */ /* end of group RFVBAT_Peripheral_Access_Layer */
6637 
6638 
6639 /* ----------------------------------------------------------------------------
6640  -- RNG Peripheral Access Layer
6641  ---------------------------------------------------------------------------- */
6642 
6643 /**
6644  * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
6645  * @{
6646  */
6647 
6648 /** RNG - Register Layout Typedef */
6649 typedef struct {
6650  __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
6651  __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
6652  __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
6653  __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
6654 } RNG_Type;
6655 
6656 /* ----------------------------------------------------------------------------
6657  -- RNG Register Masks
6658  ---------------------------------------------------------------------------- */
6659 
6660 /**
6661  * @addtogroup RNG_Register_Masks RNG Register Masks
6662  * @{
6663  */
6664 
6665 /* CR Bit Fields */
6666 #define RNG_CR_GO_MASK 0x1u
6667 #define RNG_CR_GO_SHIFT 0
6668 #define RNG_CR_HA_MASK 0x2u
6669 #define RNG_CR_HA_SHIFT 1
6670 #define RNG_CR_INTM_MASK 0x4u
6671 #define RNG_CR_INTM_SHIFT 2
6672 #define RNG_CR_CLRI_MASK 0x8u
6673 #define RNG_CR_CLRI_SHIFT 3
6674 #define RNG_CR_SLP_MASK 0x10u
6675 #define RNG_CR_SLP_SHIFT 4
6676 /* SR Bit Fields */
6677 #define RNG_SR_SECV_MASK 0x1u
6678 #define RNG_SR_SECV_SHIFT 0
6679 #define RNG_SR_LRS_MASK 0x2u
6680 #define RNG_SR_LRS_SHIFT 1
6681 #define RNG_SR_ORU_MASK 0x4u
6682 #define RNG_SR_ORU_SHIFT 2
6683 #define RNG_SR_ERRI_MASK 0x8u
6684 #define RNG_SR_ERRI_SHIFT 3
6685 #define RNG_SR_SLP_MASK 0x10u
6686 #define RNG_SR_SLP_SHIFT 4
6687 #define RNG_SR_OREG_LVL_MASK 0xFF00u
6688 #define RNG_SR_OREG_LVL_SHIFT 8
6689 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
6690 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
6691 #define RNG_SR_OREG_SIZE_SHIFT 16
6692 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
6693 /* ER Bit Fields */
6694 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
6695 #define RNG_ER_EXT_ENT_SHIFT 0
6696 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
6697 /* OR Bit Fields */
6698 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
6699 #define RNG_OR_RANDOUT_SHIFT 0
6700 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
6701 
6702 /**
6703  * @}
6704  */ /* end of group RNG_Register_Masks */
6705 
6706 
6707 /* RNG - Peripheral instance base addresses */
6708 /** Peripheral RNG base address */
6709 #define RNG_BASE (0x400A0000u)
6710 /** Peripheral RNG base pointer */
6711 #define RNG ((RNG_Type *)RNG_BASE)
6712 /** Array initializer of RNG peripheral base pointers */
6713 #define RNG_BASES { RNG }
6714 
6715 /**
6716  * @}
6717  */ /* end of group RNG_Peripheral_Access_Layer */
6718 
6719 
6720 /* ----------------------------------------------------------------------------
6721  -- RTC Peripheral Access Layer
6722  ---------------------------------------------------------------------------- */
6723 
6724 /**
6725  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
6726  * @{
6727  */
6728 
6729 /** RTC - Register Layout Typedef */
6730 typedef struct {
6731  __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
6732  __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
6733  __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
6734  __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
6735  __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
6736  __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
6737  __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
6738  __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
6739  uint8_t RESERVED_0[2016];
6740  __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
6741  __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
6742 } RTC_Type;
6743 
6744 /* ----------------------------------------------------------------------------
6745  -- RTC Register Masks
6746  ---------------------------------------------------------------------------- */
6747 
6748 /**
6749  * @addtogroup RTC_Register_Masks RTC Register Masks
6750  * @{
6751  */
6752 
6753 /* TSR Bit Fields */
6754 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
6755 #define RTC_TSR_TSR_SHIFT 0
6756 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
6757 /* TPR Bit Fields */
6758 #define RTC_TPR_TPR_MASK 0xFFFFu
6759 #define RTC_TPR_TPR_SHIFT 0
6760 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
6761 /* TAR Bit Fields */
6762 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
6763 #define RTC_TAR_TAR_SHIFT 0
6764 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
6765 /* TCR Bit Fields */
6766 #define RTC_TCR_TCR_MASK 0xFFu
6767 #define RTC_TCR_TCR_SHIFT 0
6768 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
6769 #define RTC_TCR_CIR_MASK 0xFF00u
6770 #define RTC_TCR_CIR_SHIFT 8
6771 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
6772 #define RTC_TCR_TCV_MASK 0xFF0000u
6773 #define RTC_TCR_TCV_SHIFT 16
6774 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
6775 #define RTC_TCR_CIC_MASK 0xFF000000u
6776 #define RTC_TCR_CIC_SHIFT 24
6777 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
6778 /* CR Bit Fields */
6779 #define RTC_CR_SWR_MASK 0x1u
6780 #define RTC_CR_SWR_SHIFT 0
6781 #define RTC_CR_WPE_MASK 0x2u
6782 #define RTC_CR_WPE_SHIFT 1
6783 #define RTC_CR_SUP_MASK 0x4u
6784 #define RTC_CR_SUP_SHIFT 2
6785 #define RTC_CR_UM_MASK 0x8u
6786 #define RTC_CR_UM_SHIFT 3
6787 #define RTC_CR_OSCE_MASK 0x100u
6788 #define RTC_CR_OSCE_SHIFT 8
6789 #define RTC_CR_CLKO_MASK 0x200u
6790 #define RTC_CR_CLKO_SHIFT 9
6791 #define RTC_CR_SC16P_MASK 0x400u
6792 #define RTC_CR_SC16P_SHIFT 10
6793 #define RTC_CR_SC8P_MASK 0x800u
6794 #define RTC_CR_SC8P_SHIFT 11
6795 #define RTC_CR_SC4P_MASK 0x1000u
6796 #define RTC_CR_SC4P_SHIFT 12
6797 #define RTC_CR_SC2P_MASK 0x2000u
6798 #define RTC_CR_SC2P_SHIFT 13
6799 /* SR Bit Fields */
6800 #define RTC_SR_TIF_MASK 0x1u
6801 #define RTC_SR_TIF_SHIFT 0
6802 #define RTC_SR_TOF_MASK 0x2u
6803 #define RTC_SR_TOF_SHIFT 1
6804 #define RTC_SR_TAF_MASK 0x4u
6805 #define RTC_SR_TAF_SHIFT 2
6806 #define RTC_SR_TCE_MASK 0x10u
6807 #define RTC_SR_TCE_SHIFT 4
6808 /* LR Bit Fields */
6809 #define RTC_LR_TCL_MASK 0x8u
6810 #define RTC_LR_TCL_SHIFT 3
6811 #define RTC_LR_CRL_MASK 0x10u
6812 #define RTC_LR_CRL_SHIFT 4
6813 #define RTC_LR_SRL_MASK 0x20u
6814 #define RTC_LR_SRL_SHIFT 5
6815 #define RTC_LR_LRL_MASK 0x40u
6816 #define RTC_LR_LRL_SHIFT 6
6817 /* IER Bit Fields */
6818 #define RTC_IER_TIIE_MASK 0x1u
6819 #define RTC_IER_TIIE_SHIFT 0
6820 #define RTC_IER_TOIE_MASK 0x2u
6821 #define RTC_IER_TOIE_SHIFT 1
6822 #define RTC_IER_TAIE_MASK 0x4u
6823 #define RTC_IER_TAIE_SHIFT 2
6824 #define RTC_IER_TSIE_MASK 0x10u
6825 #define RTC_IER_TSIE_SHIFT 4
6826 #define RTC_IER_WPON_MASK 0x80u
6827 #define RTC_IER_WPON_SHIFT 7
6828 /* WAR Bit Fields */
6829 #define RTC_WAR_TSRW_MASK 0x1u
6830 #define RTC_WAR_TSRW_SHIFT 0
6831 #define RTC_WAR_TPRW_MASK 0x2u
6832 #define RTC_WAR_TPRW_SHIFT 1
6833 #define RTC_WAR_TARW_MASK 0x4u
6834 #define RTC_WAR_TARW_SHIFT 2
6835 #define RTC_WAR_TCRW_MASK 0x8u
6836 #define RTC_WAR_TCRW_SHIFT 3
6837 #define RTC_WAR_CRW_MASK 0x10u
6838 #define RTC_WAR_CRW_SHIFT 4
6839 #define RTC_WAR_SRW_MASK 0x20u
6840 #define RTC_WAR_SRW_SHIFT 5
6841 #define RTC_WAR_LRW_MASK 0x40u
6842 #define RTC_WAR_LRW_SHIFT 6
6843 #define RTC_WAR_IERW_MASK 0x80u
6844 #define RTC_WAR_IERW_SHIFT 7
6845 /* RAR Bit Fields */
6846 #define RTC_RAR_TSRR_MASK 0x1u
6847 #define RTC_RAR_TSRR_SHIFT 0
6848 #define RTC_RAR_TPRR_MASK 0x2u
6849 #define RTC_RAR_TPRR_SHIFT 1
6850 #define RTC_RAR_TARR_MASK 0x4u
6851 #define RTC_RAR_TARR_SHIFT 2
6852 #define RTC_RAR_TCRR_MASK 0x8u
6853 #define RTC_RAR_TCRR_SHIFT 3
6854 #define RTC_RAR_CRR_MASK 0x10u
6855 #define RTC_RAR_CRR_SHIFT 4
6856 #define RTC_RAR_SRR_MASK 0x20u
6857 #define RTC_RAR_SRR_SHIFT 5
6858 #define RTC_RAR_LRR_MASK 0x40u
6859 #define RTC_RAR_LRR_SHIFT 6
6860 #define RTC_RAR_IERR_MASK 0x80u
6861 #define RTC_RAR_IERR_SHIFT 7
6862 
6863 /**
6864  * @}
6865  */ /* end of group RTC_Register_Masks */
6866 
6867 
6868 /* RTC - Peripheral instance base addresses */
6869 /** Peripheral RTC base address */
6870 #define RTC_BASE (0x4003D000u)
6871 /** Peripheral RTC base pointer */
6872 #define RTC ((RTC_Type *)RTC_BASE)
6873 /** Array initializer of RTC peripheral base pointers */
6874 #define RTC_BASES { RTC }
6875 
6876 /**
6877  * @}
6878  */ /* end of group RTC_Peripheral_Access_Layer */
6879 
6880 
6881 /* ----------------------------------------------------------------------------
6882  -- SDHC Peripheral Access Layer
6883  ---------------------------------------------------------------------------- */
6884 
6885 /**
6886  * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
6887  * @{
6888  */
6889 
6890 /** SDHC - Register Layout Typedef */
6891 typedef struct {
6892  __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
6893  __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
6894  __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
6895  __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
6896  __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
6897  __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
6898  __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
6899  __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
6900  __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
6901  __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
6902  __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
6903  __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
6904  __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
6905  __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
6906  __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
6907  uint8_t RESERVED_0[8];
6908  __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
6909  __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
6910  __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
6911  uint8_t RESERVED_1[100];
6912  __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
6913  __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
6914  uint8_t RESERVED_2[52];
6915  __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
6916 } SDHC_Type;
6917 
6918 /* ----------------------------------------------------------------------------
6919  -- SDHC Register Masks
6920  ---------------------------------------------------------------------------- */
6921 
6922 /**
6923  * @addtogroup SDHC_Register_Masks SDHC Register Masks
6924  * @{
6925  */
6926 
6927 /* DSADDR Bit Fields */
6928 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
6929 #define SDHC_DSADDR_DSADDR_SHIFT 2
6930 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
6931 /* BLKATTR Bit Fields */
6932 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
6933 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
6934 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
6935 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
6936 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
6937 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
6938 /* CMDARG Bit Fields */
6939 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
6940 #define SDHC_CMDARG_CMDARG_SHIFT 0
6941 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
6942 /* XFERTYP Bit Fields */
6943 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
6944 #define SDHC_XFERTYP_DMAEN_SHIFT 0
6945 #define SDHC_XFERTYP_BCEN_MASK 0x2u
6946 #define SDHC_XFERTYP_BCEN_SHIFT 1
6947 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
6948 #define SDHC_XFERTYP_AC12EN_SHIFT 2
6949 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
6950 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
6951 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
6952 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
6953 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
6954 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
6955 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
6956 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
6957 #define SDHC_XFERTYP_CCCEN_SHIFT 19
6958 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
6959 #define SDHC_XFERTYP_CICEN_SHIFT 20
6960 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
6961 #define SDHC_XFERTYP_DPSEL_SHIFT 21
6962 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
6963 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
6964 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
6965 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
6966 #define SDHC_XFERTYP_CMDINX_SHIFT 24
6967 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
6968 /* CMDRSP Bit Fields */
6969 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
6970 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
6971 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
6972 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
6973 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
6974 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
6975 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
6976 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
6977 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
6978 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
6979 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
6980 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
6981 /* DATPORT Bit Fields */
6982 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
6983 #define SDHC_DATPORT_DATCONT_SHIFT 0
6984 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
6985 /* PRSSTAT Bit Fields */
6986 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
6987 #define SDHC_PRSSTAT_CIHB_SHIFT 0
6988 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
6989 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
6990 #define SDHC_PRSSTAT_DLA_MASK 0x4u
6991 #define SDHC_PRSSTAT_DLA_SHIFT 2
6992 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
6993 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
6994 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
6995 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
6996 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
6997 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
6998 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
6999 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
7000 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
7001 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
7002 #define SDHC_PRSSTAT_WTA_MASK 0x100u
7003 #define SDHC_PRSSTAT_WTA_SHIFT 8
7004 #define SDHC_PRSSTAT_RTA_MASK 0x200u
7005 #define SDHC_PRSSTAT_RTA_SHIFT 9
7006 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
7007 #define SDHC_PRSSTAT_BWEN_SHIFT 10
7008 #define SDHC_PRSSTAT_BREN_MASK 0x800u
7009 #define SDHC_PRSSTAT_BREN_SHIFT 11
7010 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
7011 #define SDHC_PRSSTAT_CINS_SHIFT 16
7012 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
7013 #define SDHC_PRSSTAT_CLSL_SHIFT 23
7014 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
7015 #define SDHC_PRSSTAT_DLSL_SHIFT 24
7016 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
7017 /* PROCTL Bit Fields */
7018 #define SDHC_PROCTL_LCTL_MASK 0x1u
7019 #define SDHC_PROCTL_LCTL_SHIFT 0
7020 #define SDHC_PROCTL_DTW_MASK 0x6u
7021 #define SDHC_PROCTL_DTW_SHIFT 1
7022 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
7023 #define SDHC_PROCTL_D3CD_MASK 0x8u
7024 #define SDHC_PROCTL_D3CD_SHIFT 3
7025 #define SDHC_PROCTL_EMODE_MASK 0x30u
7026 #define SDHC_PROCTL_EMODE_SHIFT 4
7027 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
7028 #define SDHC_PROCTL_CDTL_MASK 0x40u
7029 #define SDHC_PROCTL_CDTL_SHIFT 6
7030 #define SDHC_PROCTL_CDSS_MASK 0x80u
7031 #define SDHC_PROCTL_CDSS_SHIFT 7
7032 #define SDHC_PROCTL_DMAS_MASK 0x300u
7033 #define SDHC_PROCTL_DMAS_SHIFT 8
7034 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
7035 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
7036 #define SDHC_PROCTL_SABGREQ_SHIFT 16
7037 #define SDHC_PROCTL_CREQ_MASK 0x20000u
7038 #define SDHC_PROCTL_CREQ_SHIFT 17
7039 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
7040 #define SDHC_PROCTL_RWCTL_SHIFT 18
7041 #define SDHC_PROCTL_IABG_MASK 0x80000u
7042 #define SDHC_PROCTL_IABG_SHIFT 19
7043 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
7044 #define SDHC_PROCTL_WECINT_SHIFT 24
7045 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
7046 #define SDHC_PROCTL_WECINS_SHIFT 25
7047 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
7048 #define SDHC_PROCTL_WECRM_SHIFT 26
7049 /* SYSCTL Bit Fields */
7050 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
7051 #define SDHC_SYSCTL_IPGEN_SHIFT 0
7052 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
7053 #define SDHC_SYSCTL_HCKEN_SHIFT 1
7054 #define SDHC_SYSCTL_PEREN_MASK 0x4u
7055 #define SDHC_SYSCTL_PEREN_SHIFT 2
7056 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
7057 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
7058 #define SDHC_SYSCTL_DVS_MASK 0xF0u
7059 #define SDHC_SYSCTL_DVS_SHIFT 4
7060 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
7061 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
7062 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
7063 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
7064 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
7065 #define SDHC_SYSCTL_DTOCV_SHIFT 16
7066 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
7067 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
7068 #define SDHC_SYSCTL_RSTA_SHIFT 24
7069 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
7070 #define SDHC_SYSCTL_RSTC_SHIFT 25
7071 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
7072 #define SDHC_SYSCTL_RSTD_SHIFT 26
7073 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
7074 #define SDHC_SYSCTL_INITA_SHIFT 27
7075 /* IRQSTAT Bit Fields */
7076 #define SDHC_IRQSTAT_CC_MASK 0x1u
7077 #define SDHC_IRQSTAT_CC_SHIFT 0
7078 #define SDHC_IRQSTAT_TC_MASK 0x2u
7079 #define SDHC_IRQSTAT_TC_SHIFT 1
7080 #define SDHC_IRQSTAT_BGE_MASK 0x4u
7081 #define SDHC_IRQSTAT_BGE_SHIFT 2
7082 #define SDHC_IRQSTAT_DINT_MASK 0x8u
7083 #define SDHC_IRQSTAT_DINT_SHIFT 3
7084 #define SDHC_IRQSTAT_BWR_MASK 0x10u
7085 #define SDHC_IRQSTAT_BWR_SHIFT 4
7086 #define SDHC_IRQSTAT_BRR_MASK 0x20u
7087 #define SDHC_IRQSTAT_BRR_SHIFT 5
7088 #define SDHC_IRQSTAT_CINS_MASK 0x40u
7089 #define SDHC_IRQSTAT_CINS_SHIFT 6
7090 #define SDHC_IRQSTAT_CRM_MASK 0x80u
7091 #define SDHC_IRQSTAT_CRM_SHIFT 7
7092 #define SDHC_IRQSTAT_CINT_MASK 0x100u
7093 #define SDHC_IRQSTAT_CINT_SHIFT 8
7094 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
7095 #define SDHC_IRQSTAT_CTOE_SHIFT 16
7096 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
7097 #define SDHC_IRQSTAT_CCE_SHIFT 17
7098 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
7099 #define SDHC_IRQSTAT_CEBE_SHIFT 18
7100 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
7101 #define SDHC_IRQSTAT_CIE_SHIFT 19
7102 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
7103 #define SDHC_IRQSTAT_DTOE_SHIFT 20
7104 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
7105 #define SDHC_IRQSTAT_DCE_SHIFT 21
7106 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
7107 #define SDHC_IRQSTAT_DEBE_SHIFT 22
7108 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
7109 #define SDHC_IRQSTAT_AC12E_SHIFT 24
7110 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
7111 #define SDHC_IRQSTAT_DMAE_SHIFT 28
7112 /* IRQSTATEN Bit Fields */
7113 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
7114 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
7115 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
7116 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
7117 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
7118 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
7119 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
7120 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
7121 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
7122 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
7123 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
7124 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
7125 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
7126 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
7127 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
7128 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
7129 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
7130 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
7131 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
7132 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
7133 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
7134 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
7135 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
7136 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
7137 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
7138 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
7139 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
7140 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
7141 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
7142 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
7143 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
7144 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
7145 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
7146 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
7147 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
7148 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
7149 /* IRQSIGEN Bit Fields */
7150 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
7151 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
7152 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
7153 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
7154 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
7155 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
7156 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
7157 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
7158 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
7159 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
7160 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
7161 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
7162 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
7163 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
7164 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
7165 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
7166 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
7167 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
7168 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
7169 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
7170 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
7171 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
7172 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
7173 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
7174 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
7175 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
7176 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
7177 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
7178 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
7179 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
7180 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
7181 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
7182 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
7183 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
7184 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
7185 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
7186 /* AC12ERR Bit Fields */
7187 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
7188 #define SDHC_AC12ERR_AC12NE_SHIFT 0
7189 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
7190 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
7191 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
7192 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
7193 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
7194 #define SDHC_AC12ERR_AC12CE_SHIFT 3
7195 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
7196 #define SDHC_AC12ERR_AC12IE_SHIFT 4
7197 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
7198 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
7199 /* HTCAPBLT Bit Fields */
7200 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
7201 #define SDHC_HTCAPBLT_MBL_SHIFT 16
7202 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
7203 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
7204 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
7205 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
7206 #define SDHC_HTCAPBLT_HSS_SHIFT 21
7207 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
7208 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
7209 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
7210 #define SDHC_HTCAPBLT_SRS_SHIFT 23
7211 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
7212 #define SDHC_HTCAPBLT_VS33_SHIFT 24
7213 #define SDHC_HTCAPBLT_VS30_MASK 0x2000000u
7214 #define SDHC_HTCAPBLT_VS30_SHIFT 25
7215 #define SDHC_HTCAPBLT_VS18_MASK 0x4000000u
7216 #define SDHC_HTCAPBLT_VS18_SHIFT 26
7217 /* WML Bit Fields */
7218 #define SDHC_WML_RDWML_MASK 0xFFu
7219 #define SDHC_WML_RDWML_SHIFT 0
7220 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
7221 #define SDHC_WML_WRWML_MASK 0xFF0000u
7222 #define SDHC_WML_WRWML_SHIFT 16
7223 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
7224 /* FEVT Bit Fields */
7225 #define SDHC_FEVT_AC12NE_MASK 0x1u
7226 #define SDHC_FEVT_AC12NE_SHIFT 0
7227 #define SDHC_FEVT_AC12TOE_MASK 0x2u
7228 #define SDHC_FEVT_AC12TOE_SHIFT 1
7229 #define SDHC_FEVT_AC12CE_MASK 0x4u
7230 #define SDHC_FEVT_AC12CE_SHIFT 2
7231 #define SDHC_FEVT_AC12EBE_MASK 0x8u
7232 #define SDHC_FEVT_AC12EBE_SHIFT 3
7233 #define SDHC_FEVT_AC12IE_MASK 0x10u
7234 #define SDHC_FEVT_AC12IE_SHIFT 4
7235 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
7236 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
7237 #define SDHC_FEVT_CTOE_MASK 0x10000u
7238 #define SDHC_FEVT_CTOE_SHIFT 16
7239 #define SDHC_FEVT_CCE_MASK 0x20000u
7240 #define SDHC_FEVT_CCE_SHIFT 17
7241 #define SDHC_FEVT_CEBE_MASK 0x40000u
7242 #define SDHC_FEVT_CEBE_SHIFT 18
7243 #define SDHC_FEVT_CIE_MASK 0x80000u
7244 #define SDHC_FEVT_CIE_SHIFT 19
7245 #define SDHC_FEVT_DTOE_MASK 0x100000u
7246 #define SDHC_FEVT_DTOE_SHIFT 20
7247 #define SDHC_FEVT_DCE_MASK 0x200000u
7248 #define SDHC_FEVT_DCE_SHIFT 21
7249 #define SDHC_FEVT_DEBE_MASK 0x400000u
7250 #define SDHC_FEVT_DEBE_SHIFT 22
7251 #define SDHC_FEVT_AC12E_MASK 0x1000000u
7252 #define SDHC_FEVT_AC12E_SHIFT 24
7253 #define SDHC_FEVT_DMAE_MASK 0x10000000u
7254 #define SDHC_FEVT_DMAE_SHIFT 28
7255 #define SDHC_FEVT_CINT_MASK 0x80000000u
7256 #define SDHC_FEVT_CINT_SHIFT 31
7257 /* ADMAES Bit Fields */
7258 #define SDHC_ADMAES_ADMAES_MASK 0x3u
7259 #define SDHC_ADMAES_ADMAES_SHIFT 0
7260 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
7261 #define SDHC_ADMAES_ADMALME_MASK 0x4u
7262 #define SDHC_ADMAES_ADMALME_SHIFT 2
7263 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
7264 #define SDHC_ADMAES_ADMADCE_SHIFT 3
7265 /* ADSADDR Bit Fields */
7266 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
7267 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
7268 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
7269 /* VENDOR Bit Fields */
7270 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
7271 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
7272 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
7273 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
7274 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
7275 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
7276 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
7277 /* MMCBOOT Bit Fields */
7278 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
7279 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
7280 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
7281 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
7282 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
7283 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
7284 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
7285 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
7286 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
7287 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
7288 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
7289 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
7290 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
7291 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
7292 /* HOSTVER Bit Fields */
7293 #define SDHC_HOSTVER_SVN_MASK 0xFFu
7294 #define SDHC_HOSTVER_SVN_SHIFT 0
7295 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
7296 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
7297 #define SDHC_HOSTVER_VVN_SHIFT 8
7298 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
7299 
7300 /**
7301  * @}
7302  */ /* end of group SDHC_Register_Masks */
7303 
7304 
7305 /* SDHC - Peripheral instance base addresses */
7306 /** Peripheral SDHC base address */
7307 #define SDHC_BASE (0x400B1000u)
7308 /** Peripheral SDHC base pointer */
7309 #define SDHC ((SDHC_Type *)SDHC_BASE)
7310 /** Array initializer of SDHC peripheral base pointers */
7311 #define SDHC_BASES { SDHC }
7312 
7313 /**
7314  * @}
7315  */ /* end of group SDHC_Peripheral_Access_Layer */
7316 
7317 
7318 /* ----------------------------------------------------------------------------
7319  -- SIM Peripheral Access Layer
7320  ---------------------------------------------------------------------------- */
7321 
7322 /**
7323  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
7324  * @{
7325  */
7326 
7327 /** SIM - Register Layout Typedef */
7328 typedef struct {
7329  __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
7330  __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
7331  uint8_t RESERVED_0[4092];
7332  __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
7333  uint8_t RESERVED_1[4];
7334  __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
7335  __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
7336  uint8_t RESERVED_2[4];
7337  __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
7338  uint8_t RESERVED_3[8];
7339  __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
7340  __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
7341  __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
7342  __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
7343  __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
7344  __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
7345  __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
7346  __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
7347  __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
7348  __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
7349  __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
7350  __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
7351  __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
7352  __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
7353  __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
7354  __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
7355 } SIM_Type;
7356 
7357 /* ----------------------------------------------------------------------------
7358  -- SIM Register Masks
7359  ---------------------------------------------------------------------------- */
7360 
7361 /**
7362  * @addtogroup SIM_Register_Masks SIM Register Masks
7363  * @{
7364  */
7365 
7366 /* SOPT1 Bit Fields */
7367 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
7368 #define SIM_SOPT1_RAMSIZE_SHIFT 12
7369 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
7370 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
7371 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
7372 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
7373 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
7374 #define SIM_SOPT1_USBVSTBY_SHIFT 29
7375 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
7376 #define SIM_SOPT1_USBSSTBY_SHIFT 30
7377 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
7378 #define SIM_SOPT1_USBREGEN_SHIFT 31
7379 /* SOPT1CFG Bit Fields */
7380 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
7381 #define SIM_SOPT1CFG_URWE_SHIFT 24
7382 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
7383 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
7384 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
7385 #define SIM_SOPT1CFG_USSWE_SHIFT 26
7386 /* SOPT2 Bit Fields */
7387 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
7388 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
7389 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
7390 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
7391 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
7392 #define SIM_SOPT2_FBSL_MASK 0x300u
7393 #define SIM_SOPT2_FBSL_SHIFT 8
7394 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
7395 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
7396 #define SIM_SOPT2_PTD7PAD_SHIFT 11
7397 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
7398 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
7399 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
7400 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
7401 #define SIM_SOPT2_USBSRC_MASK 0x40000u
7402 #define SIM_SOPT2_USBSRC_SHIFT 18
7403 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
7404 #define SIM_SOPT2_RMIISRC_SHIFT 19
7405 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
7406 #define SIM_SOPT2_TIMESRC_SHIFT 20
7407 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
7408 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
7409 #define SIM_SOPT2_SDHCSRC_SHIFT 28
7410 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
7411 /* SOPT4 Bit Fields */
7412 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
7413 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
7414 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
7415 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
7416 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
7417 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
7418 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
7419 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
7420 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
7421 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
7422 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
7423 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
7424 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
7425 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
7426 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
7427 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
7428 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
7429 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
7430 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
7431 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
7432 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
7433 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
7434 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
7435 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
7436 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
7437 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
7438 /* SOPT5 Bit Fields */
7439 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
7440 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
7441 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
7442 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
7443 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
7444 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
7445 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
7446 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
7447 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
7448 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
7449 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
7450 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
7451 /* SOPT7 Bit Fields */
7452 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
7453 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
7454 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
7455 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
7456 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
7457 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
7458 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
7459 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
7460 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
7461 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
7462 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
7463 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
7464 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
7465 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
7466 /* SDID Bit Fields */
7467 #define SIM_SDID_PINID_MASK 0xFu
7468 #define SIM_SDID_PINID_SHIFT 0
7469 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
7470 #define SIM_SDID_FAMID_MASK 0x70u
7471 #define SIM_SDID_FAMID_SHIFT 4
7472 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
7473 #define SIM_SDID_REVID_MASK 0xF000u
7474 #define SIM_SDID_REVID_SHIFT 12
7475 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
7476 /* SCGC1 Bit Fields */
7477 #define SIM_SCGC1_UART4_MASK 0x400u
7478 #define SIM_SCGC1_UART4_SHIFT 10
7479 #define SIM_SCGC1_UART5_MASK 0x800u
7480 #define SIM_SCGC1_UART5_SHIFT 11
7481 /* SCGC2 Bit Fields */
7482 #define SIM_SCGC2_ENET_MASK 0x1u
7483 #define SIM_SCGC2_ENET_SHIFT 0
7484 #define SIM_SCGC2_DAC0_MASK 0x1000u
7485 #define SIM_SCGC2_DAC0_SHIFT 12
7486 #define SIM_SCGC2_DAC1_MASK 0x2000u
7487 #define SIM_SCGC2_DAC1_SHIFT 13
7488 /* SCGC3 Bit Fields */
7489 #define SIM_SCGC3_RNGA_MASK 0x1u
7490 #define SIM_SCGC3_RNGA_SHIFT 0
7491 #define SIM_SCGC3_FLEXCAN1_MASK 0x10u
7492 #define SIM_SCGC3_FLEXCAN1_SHIFT 4
7493 #define SIM_SCGC3_SPI2_MASK 0x1000u
7494 #define SIM_SCGC3_SPI2_SHIFT 12
7495 #define SIM_SCGC3_SDHC_MASK 0x20000u
7496 #define SIM_SCGC3_SDHC_SHIFT 17
7497 #define SIM_SCGC3_FTM2_MASK 0x1000000u
7498 #define SIM_SCGC3_FTM2_SHIFT 24
7499 #define SIM_SCGC3_ADC1_MASK 0x8000000u
7500 #define SIM_SCGC3_ADC1_SHIFT 27
7501 /* SCGC4 Bit Fields */
7502 #define SIM_SCGC4_EWM_MASK 0x2u
7503 #define SIM_SCGC4_EWM_SHIFT 1
7504 #define SIM_SCGC4_CMT_MASK 0x4u
7505 #define SIM_SCGC4_CMT_SHIFT 2
7506 #define SIM_SCGC4_I2C0_MASK 0x40u
7507 #define SIM_SCGC4_I2C0_SHIFT 6
7508 #define SIM_SCGC4_I2C1_MASK 0x80u
7509 #define SIM_SCGC4_I2C1_SHIFT 7
7510 #define SIM_SCGC4_UART0_MASK 0x400u
7511 #define SIM_SCGC4_UART0_SHIFT 10
7512 #define SIM_SCGC4_UART1_MASK 0x800u
7513 #define SIM_SCGC4_UART1_SHIFT 11
7514 #define SIM_SCGC4_UART2_MASK 0x1000u
7515 #define SIM_SCGC4_UART2_SHIFT 12
7516 #define SIM_SCGC4_UART3_MASK 0x2000u
7517 #define SIM_SCGC4_UART3_SHIFT 13
7518 #define SIM_SCGC4_USBOTG_MASK 0x40000u
7519 #define SIM_SCGC4_USBOTG_SHIFT 18
7520 #define SIM_SCGC4_CMP_MASK 0x80000u
7521 #define SIM_SCGC4_CMP_SHIFT 19
7522 #define SIM_SCGC4_VREF_MASK 0x100000u
7523 #define SIM_SCGC4_VREF_SHIFT 20
7524 #define SIM_SCGC4_LLWU_MASK 0x10000000u
7525 #define SIM_SCGC4_LLWU_SHIFT 28
7526 /* SCGC5 Bit Fields */
7527 #define SIM_SCGC5_LPTIMER_MASK 0x1u
7528 #define SIM_SCGC5_LPTIMER_SHIFT 0
7529 #define SIM_SCGC5_TSI_MASK 0x20u
7530 #define SIM_SCGC5_TSI_SHIFT 5
7531 #define SIM_SCGC5_PORTA_MASK 0x200u
7532 #define SIM_SCGC5_PORTA_SHIFT 9
7533 #define SIM_SCGC5_PORTB_MASK 0x400u
7534 #define SIM_SCGC5_PORTB_SHIFT 10
7535 #define SIM_SCGC5_PORTC_MASK 0x800u
7536 #define SIM_SCGC5_PORTC_SHIFT 11
7537 #define SIM_SCGC5_PORTD_MASK 0x1000u
7538 #define SIM_SCGC5_PORTD_SHIFT 12
7539 #define SIM_SCGC5_PORTE_MASK 0x2000u
7540 #define SIM_SCGC5_PORTE_SHIFT 13
7541 /* SCGC6 Bit Fields */
7542 #define SIM_SCGC6_FTFL_MASK 0x1u
7543 #define SIM_SCGC6_FTFL_SHIFT 0
7544 #define SIM_SCGC6_DMAMUX_MASK 0x2u
7545 #define SIM_SCGC6_DMAMUX_SHIFT 1
7546 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
7547 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
7548 #define SIM_SCGC6_SPI0_MASK 0x1000u
7549 #define SIM_SCGC6_SPI0_SHIFT 12
7550 #define SIM_SCGC6_SPI1_MASK 0x2000u
7551 #define SIM_SCGC6_SPI1_SHIFT 13
7552 #define SIM_SCGC6_I2S_MASK 0x8000u
7553 #define SIM_SCGC6_I2S_SHIFT 15
7554 #define SIM_SCGC6_CRC_MASK 0x40000u
7555 #define SIM_SCGC6_CRC_SHIFT 18
7556 #define SIM_SCGC6_USBDCD_MASK 0x200000u
7557 #define SIM_SCGC6_USBDCD_SHIFT 21
7558 #define SIM_SCGC6_PDB_MASK 0x400000u
7559 #define SIM_SCGC6_PDB_SHIFT 22
7560 #define SIM_SCGC6_PIT_MASK 0x800000u
7561 #define SIM_SCGC6_PIT_SHIFT 23
7562 #define SIM_SCGC6_FTM0_MASK 0x1000000u
7563 #define SIM_SCGC6_FTM0_SHIFT 24
7564 #define SIM_SCGC6_FTM1_MASK 0x2000000u
7565 #define SIM_SCGC6_FTM1_SHIFT 25
7566 #define SIM_SCGC6_ADC0_MASK 0x8000000u
7567 #define SIM_SCGC6_ADC0_SHIFT 27
7568 #define SIM_SCGC6_RTC_MASK 0x20000000u
7569 #define SIM_SCGC6_RTC_SHIFT 29
7570 /* SCGC7 Bit Fields */
7571 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
7572 #define SIM_SCGC7_FLEXBUS_SHIFT 0
7573 #define SIM_SCGC7_DMA_MASK 0x2u
7574 #define SIM_SCGC7_DMA_SHIFT 1
7575 #define SIM_SCGC7_MPU_MASK 0x4u
7576 #define SIM_SCGC7_MPU_SHIFT 2
7577 /* CLKDIV1 Bit Fields */
7578 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
7579 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
7580 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
7581 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
7582 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
7583 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
7584 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
7585 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
7586 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
7587 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
7588 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
7589 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
7590 /* CLKDIV2 Bit Fields */
7591 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
7592 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
7593 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
7594 #define SIM_CLKDIV2_USBDIV_SHIFT 1
7595 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
7596 /* FCFG1 Bit Fields */
7597 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
7598 #define SIM_FCFG1_FLASHDIS_SHIFT 0
7599 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
7600 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
7601 #define SIM_FCFG1_DEPART_MASK 0xF00u
7602 #define SIM_FCFG1_DEPART_SHIFT 8
7603 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
7604 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
7605 #define SIM_FCFG1_EESIZE_SHIFT 16
7606 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
7607 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
7608 #define SIM_FCFG1_PFSIZE_SHIFT 24
7609 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
7610 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
7611 #define SIM_FCFG1_NVMSIZE_SHIFT 28
7612 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
7613 /* FCFG2 Bit Fields */
7614 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
7615 #define SIM_FCFG2_MAXADDR1_SHIFT 16
7616 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
7617 #define SIM_FCFG2_PFLSH_MASK 0x800000u
7618 #define SIM_FCFG2_PFLSH_SHIFT 23
7619 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
7620 #define SIM_FCFG2_MAXADDR0_SHIFT 24
7621 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
7622 #define SIM_FCFG2_SWAPPFLSH_MASK 0x80000000u
7623 #define SIM_FCFG2_SWAPPFLSH_SHIFT 31
7624 /* UIDH Bit Fields */
7625 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
7626 #define SIM_UIDH_UID_SHIFT 0
7627 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
7628 /* UIDMH Bit Fields */
7629 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
7630 #define SIM_UIDMH_UID_SHIFT 0
7631 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
7632 /* UIDML Bit Fields */
7633 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
7634 #define SIM_UIDML_UID_SHIFT 0
7635 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
7636 /* UIDL Bit Fields */
7637 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
7638 #define SIM_UIDL_UID_SHIFT 0
7639 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
7640 
7641 /**
7642  * @}
7643  */ /* end of group SIM_Register_Masks */
7644 
7645 
7646 /* SIM - Peripheral instance base addresses */
7647 /** Peripheral SIM base address */
7648 #define SIM_BASE (0x40047000u)
7649 /** Peripheral SIM base pointer */
7650 #define SIM ((SIM_Type *)SIM_BASE)
7651 /** Array initializer of SIM peripheral base pointers */
7652 #define SIM_BASES { SIM }
7653 
7654 /**
7655  * @}
7656  */ /* end of group SIM_Peripheral_Access_Layer */
7657 
7658 
7659 /* ----------------------------------------------------------------------------
7660  -- SMC Peripheral Access Layer
7661  ---------------------------------------------------------------------------- */
7662 
7663 /**
7664  * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
7665  * @{
7666  */
7667 
7668 /** SMC - Register Layout Typedef */
7669 typedef struct {
7670  __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
7671  __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
7672  __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
7673  __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
7674 } SMC_Type;
7675 
7676 /* ----------------------------------------------------------------------------
7677  -- SMC Register Masks
7678  ---------------------------------------------------------------------------- */
7679 
7680 /**
7681  * @addtogroup SMC_Register_Masks SMC Register Masks
7682  * @{
7683  */
7684 
7685 /* PMPROT Bit Fields */
7686 #define SMC_PMPROT_AVLLS_MASK 0x2u
7687 #define SMC_PMPROT_AVLLS_SHIFT 1
7688 #define SMC_PMPROT_ALLS_MASK 0x8u
7689 #define SMC_PMPROT_ALLS_SHIFT 3
7690 #define SMC_PMPROT_AVLP_MASK 0x20u
7691 #define SMC_PMPROT_AVLP_SHIFT 5
7692 /* PMCTRL Bit Fields */
7693 #define SMC_PMCTRL_STOPM_MASK 0x7u
7694 #define SMC_PMCTRL_STOPM_SHIFT 0
7695 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
7696 #define SMC_PMCTRL_STOPA_MASK 0x8u
7697 #define SMC_PMCTRL_STOPA_SHIFT 3
7698 #define SMC_PMCTRL_RUNM_MASK 0x60u
7699 #define SMC_PMCTRL_RUNM_SHIFT 5
7700 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
7701 #define SMC_PMCTRL_LPWUI_MASK 0x80u
7702 #define SMC_PMCTRL_LPWUI_SHIFT 7
7703 /* VLLSCTRL Bit Fields */
7704 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
7705 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
7706 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
7707 #define SMC_VLLSCTRL_RAM2PO_MASK 0x10u
7708 #define SMC_VLLSCTRL_RAM2PO_SHIFT 4
7709 /* PMSTAT Bit Fields */
7710 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
7711 #define SMC_PMSTAT_PMSTAT_SHIFT 0
7712 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
7713 
7714 /**
7715  * @}
7716  */ /* end of group SMC_Register_Masks */
7717 
7718 
7719 /* SMC - Peripheral instance base addresses */
7720 /** Peripheral SMC base address */
7721 #define SMC_BASE (0x4007E000u)
7722 /** Peripheral SMC base pointer */
7723 #define SMC ((SMC_Type *)SMC_BASE)
7724 /** Array initializer of SMC peripheral base pointers */
7725 #define SMC_BASES { SMC }
7726 
7727 /**
7728  * @}
7729  */ /* end of group SMC_Peripheral_Access_Layer */
7730 
7731 
7732 /* ----------------------------------------------------------------------------
7733  -- SPI Peripheral Access Layer
7734  ---------------------------------------------------------------------------- */
7735 
7736 /**
7737  * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
7738  * @{
7739  */
7740 
7741 /** SPI - Register Layout Typedef */
7742 typedef struct {
7743  __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
7744  uint8_t RESERVED_0[4];
7745  __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
7746  union { /* offset: 0xC */
7747  __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
7748  __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
7749  };
7750  uint8_t RESERVED_1[24];
7751  __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
7752  __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
7753  union { /* offset: 0x34 */
7754  __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
7755  __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
7756  };
7757  __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
7758  __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
7759  __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
7760  __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
7761  __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
7762  uint8_t RESERVED_2[48];
7763  __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
7764  __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
7765  __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
7766  __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
7767 } SPI_Type;
7768 
7769 /* ----------------------------------------------------------------------------
7770  -- SPI Register Masks
7771  ---------------------------------------------------------------------------- */
7772 
7773 /**
7774  * @addtogroup SPI_Register_Masks SPI Register Masks
7775  * @{
7776  */
7777 
7778 /* MCR Bit Fields */
7779 #define SPI_MCR_HALT_MASK 0x1u
7780 #define SPI_MCR_HALT_SHIFT 0
7781 #define SPI_MCR_SMPL_PT_MASK 0x300u
7782 #define SPI_MCR_SMPL_PT_SHIFT 8
7783 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
7784 #define SPI_MCR_CLR_RXF_MASK 0x400u
7785 #define SPI_MCR_CLR_RXF_SHIFT 10
7786 #define SPI_MCR_CLR_TXF_MASK 0x800u
7787 #define SPI_MCR_CLR_TXF_SHIFT 11
7788 #define SPI_MCR_DIS_RXF_MASK 0x1000u
7789 #define SPI_MCR_DIS_RXF_SHIFT 12
7790 #define SPI_MCR_DIS_TXF_MASK 0x2000u
7791 #define SPI_MCR_DIS_TXF_SHIFT 13
7792 #define SPI_MCR_MDIS_MASK 0x4000u
7793 #define SPI_MCR_MDIS_SHIFT 14
7794 #define SPI_MCR_DOZE_MASK 0x8000u
7795 #define SPI_MCR_DOZE_SHIFT 15
7796 #define SPI_MCR_PCSIS_MASK 0x1F0000u
7797 #define SPI_MCR_PCSIS_SHIFT 16
7798 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
7799 #define SPI_MCR_ROOE_MASK 0x1000000u
7800 #define SPI_MCR_ROOE_SHIFT 24
7801 #define SPI_MCR_PCSSE_MASK 0x2000000u
7802 #define SPI_MCR_PCSSE_SHIFT 25
7803 #define SPI_MCR_MTFE_MASK 0x4000000u
7804 #define SPI_MCR_MTFE_SHIFT 26
7805 #define SPI_MCR_FRZ_MASK 0x8000000u
7806 #define SPI_MCR_FRZ_SHIFT 27
7807 #define SPI_MCR_DCONF_MASK 0x30000000u
7808 #define SPI_MCR_DCONF_SHIFT 28
7809 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
7810 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
7811 #define SPI_MCR_CONT_SCKE_SHIFT 30
7812 #define SPI_MCR_MSTR_MASK 0x80000000u
7813 #define SPI_MCR_MSTR_SHIFT 31
7814 /* TCR Bit Fields */
7815 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
7816 #define SPI_TCR_SPI_TCNT_SHIFT 16
7817 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
7818 /* CTAR Bit Fields */
7819 #define SPI_CTAR_BR_MASK 0xFu
7820 #define SPI_CTAR_BR_SHIFT 0
7821 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
7822 #define SPI_CTAR_DT_MASK 0xF0u
7823 #define SPI_CTAR_DT_SHIFT 4
7824 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
7825 #define SPI_CTAR_ASC_MASK 0xF00u
7826 #define SPI_CTAR_ASC_SHIFT 8
7827 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
7828 #define SPI_CTAR_CSSCK_MASK 0xF000u
7829 #define SPI_CTAR_CSSCK_SHIFT 12
7830 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
7831 #define SPI_CTAR_PBR_MASK 0x30000u
7832 #define SPI_CTAR_PBR_SHIFT 16
7833 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
7834 #define SPI_CTAR_PDT_MASK 0xC0000u
7835 #define SPI_CTAR_PDT_SHIFT 18
7836 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
7837 #define SPI_CTAR_PASC_MASK 0x300000u
7838 #define SPI_CTAR_PASC_SHIFT 20
7839 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
7840 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
7841 #define SPI_CTAR_PCSSCK_SHIFT 22
7842 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
7843 #define SPI_CTAR_LSBFE_MASK 0x1000000u
7844 #define SPI_CTAR_LSBFE_SHIFT 24
7845 #define SPI_CTAR_CPHA_MASK 0x2000000u
7846 #define SPI_CTAR_CPHA_SHIFT 25
7847 #define SPI_CTAR_CPOL_MASK 0x4000000u
7848 #define SPI_CTAR_CPOL_SHIFT 26
7849 #define SPI_CTAR_FMSZ_MASK 0x78000000u
7850 #define SPI_CTAR_FMSZ_SHIFT 27
7851 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
7852 #define SPI_CTAR_DBR_MASK 0x80000000u
7853 #define SPI_CTAR_DBR_SHIFT 31
7854 /* CTAR_SLAVE Bit Fields */
7855 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
7856 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
7857 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
7858 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
7859 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
7860 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
7861 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
7862 /* SR Bit Fields */
7863 #define SPI_SR_POPNXTPTR_MASK 0xFu
7864 #define SPI_SR_POPNXTPTR_SHIFT 0
7865 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
7866 #define SPI_SR_RXCTR_MASK 0xF0u
7867 #define SPI_SR_RXCTR_SHIFT 4
7868 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
7869 #define SPI_SR_TXNXTPTR_MASK 0xF00u
7870 #define SPI_SR_TXNXTPTR_SHIFT 8
7871 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
7872 #define SPI_SR_TXCTR_MASK 0xF000u
7873 #define SPI_SR_TXCTR_SHIFT 12
7874 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
7875 #define SPI_SR_RFDF_MASK 0x20000u
7876 #define SPI_SR_RFDF_SHIFT 17
7877 #define SPI_SR_RFOF_MASK 0x80000u
7878 #define SPI_SR_RFOF_SHIFT 19
7879 #define SPI_SR_TFFF_MASK 0x2000000u
7880 #define SPI_SR_TFFF_SHIFT 25
7881 #define SPI_SR_TFUF_MASK 0x8000000u
7882 #define SPI_SR_TFUF_SHIFT 27
7883 #define SPI_SR_EOQF_MASK 0x10000000u
7884 #define SPI_SR_EOQF_SHIFT 28
7885 #define SPI_SR_TXRXS_MASK 0x40000000u
7886 #define SPI_SR_TXRXS_SHIFT 30
7887 #define SPI_SR_TCF_MASK 0x80000000u
7888 #define SPI_SR_TCF_SHIFT 31
7889 /* RSER Bit Fields */
7890 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
7891 #define SPI_RSER_RFDF_DIRS_SHIFT 16
7892 #define SPI_RSER_RFDF_RE_MASK 0x20000u
7893 #define SPI_RSER_RFDF_RE_SHIFT 17
7894 #define SPI_RSER_RFOF_RE_MASK 0x80000u
7895 #define SPI_RSER_RFOF_RE_SHIFT 19
7896 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
7897 #define SPI_RSER_TFFF_DIRS_SHIFT 24
7898 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
7899 #define SPI_RSER_TFFF_RE_SHIFT 25
7900 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
7901 #define SPI_RSER_TFUF_RE_SHIFT 27
7902 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
7903 #define SPI_RSER_EOQF_RE_SHIFT 28
7904 #define SPI_RSER_TCF_RE_MASK 0x80000000u
7905 #define SPI_RSER_TCF_RE_SHIFT 31
7906 /* PUSHR Bit Fields */
7907 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
7908 #define SPI_PUSHR_TXDATA_SHIFT 0
7909 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
7910 #define SPI_PUSHR_PCS_MASK 0x3F0000u
7911 #define SPI_PUSHR_PCS_SHIFT 16
7912 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
7913 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
7914 #define SPI_PUSHR_CTCNT_SHIFT 26
7915 #define SPI_PUSHR_EOQ_MASK 0x8000000u
7916 #define SPI_PUSHR_EOQ_SHIFT 27
7917 #define SPI_PUSHR_CTAS_MASK 0x70000000u
7918 #define SPI_PUSHR_CTAS_SHIFT 28
7919 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
7920 #define SPI_PUSHR_CONT_MASK 0x80000000u
7921 #define SPI_PUSHR_CONT_SHIFT 31
7922 /* PUSHR_SLAVE Bit Fields */
7923 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFu
7924 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
7925 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
7926 /* POPR Bit Fields */
7927 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
7928 #define SPI_POPR_RXDATA_SHIFT 0
7929 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
7930 /* TXFR0 Bit Fields */
7931 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
7932 #define SPI_TXFR0_TXDATA_SHIFT 0
7933 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
7934 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
7935 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
7936 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
7937 /* TXFR1 Bit Fields */
7938 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
7939 #define SPI_TXFR1_TXDATA_SHIFT 0
7940 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
7941 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
7942 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
7943 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
7944 /* TXFR2 Bit Fields */
7945 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
7946 #define SPI_TXFR2_TXDATA_SHIFT 0
7947 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
7948 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
7949 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
7950 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
7951 /* TXFR3 Bit Fields */
7952 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
7953 #define SPI_TXFR3_TXDATA_SHIFT 0
7954 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
7955 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
7956 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
7957 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
7958 /* RXFR0 Bit Fields */
7959 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
7960 #define SPI_RXFR0_RXDATA_SHIFT 0
7961 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
7962 /* RXFR1 Bit Fields */
7963 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
7964 #define SPI_RXFR1_RXDATA_SHIFT 0
7965 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
7966 /* RXFR2 Bit Fields */
7967 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
7968 #define SPI_RXFR2_RXDATA_SHIFT 0
7969 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
7970 /* RXFR3 Bit Fields */
7971 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
7972 #define SPI_RXFR3_RXDATA_SHIFT 0
7973 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
7974 
7975 /**
7976  * @}
7977  */ /* end of group SPI_Register_Masks */
7978 
7979 
7980 /* SPI - Peripheral instance base addresses */
7981 /** Peripheral SPI0 base address */
7982 #define SPI0_BASE (0x4002C000u)
7983 /** Peripheral SPI0 base pointer */
7984 #define SPI0 ((SPI_Type *)SPI0_BASE)
7985 /** Peripheral SPI1 base address */
7986 #define SPI1_BASE (0x4002D000u)
7987 /** Peripheral SPI1 base pointer */
7988 #define SPI1 ((SPI_Type *)SPI1_BASE)
7989 /** Peripheral SPI2 base address */
7990 #define SPI2_BASE (0x400AC000u)
7991 /** Peripheral SPI2 base pointer */
7992 #define SPI2 ((SPI_Type *)SPI2_BASE)
7993 /** Array initializer of SPI peripheral base pointers */
7994 #define SPI_BASES { SPI0, SPI1, SPI2 }
7995 
7996 /**
7997  * @}
7998  */ /* end of group SPI_Peripheral_Access_Layer */
7999 
8000 
8001 /* ----------------------------------------------------------------------------
8002  -- TSI Peripheral Access Layer
8003  ---------------------------------------------------------------------------- */
8004 
8005 /**
8006  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
8007  * @{
8008  */
8009 
8010 /** TSI - Register Layout Typedef */
8011 typedef struct {
8012  __IO uint32_t GENCS; /**< General Control and Status register, offset: 0x0 */
8013  __IO uint32_t SCANC; /**< SCAN Control register, offset: 0x4 */
8014  __IO uint32_t PEN; /**< Pin Enable register, offset: 0x8 */
8015  __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
8016  uint8_t RESERVED_0[240];
8017  __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
8018  __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
8019  __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
8020  __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
8021  __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
8022  __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
8023  __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
8024  __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
8025  __IO uint32_t THRESHOLD; /**< Low-Power Channel Threshold register, offset: 0x120 */
8026 } TSI_Type;
8027 
8028 /* ----------------------------------------------------------------------------
8029  -- TSI Register Masks
8030  ---------------------------------------------------------------------------- */
8031 
8032 /**
8033  * @addtogroup TSI_Register_Masks TSI Register Masks
8034  * @{
8035  */
8036 
8037 /* GENCS Bit Fields */
8038 #define TSI_GENCS_STPE_MASK 0x1u
8039 #define TSI_GENCS_STPE_SHIFT 0
8040 #define TSI_GENCS_STM_MASK 0x2u
8041 #define TSI_GENCS_STM_SHIFT 1
8042 #define TSI_GENCS_ESOR_MASK 0x10u
8043 #define TSI_GENCS_ESOR_SHIFT 4
8044 #define TSI_GENCS_ERIE_MASK 0x20u
8045 #define TSI_GENCS_ERIE_SHIFT 5
8046 #define TSI_GENCS_TSIIE_MASK 0x40u
8047 #define TSI_GENCS_TSIIE_SHIFT 6
8048 #define TSI_GENCS_TSIEN_MASK 0x80u
8049 #define TSI_GENCS_TSIEN_SHIFT 7
8050 #define TSI_GENCS_SWTS_MASK 0x100u
8051 #define TSI_GENCS_SWTS_SHIFT 8
8052 #define TSI_GENCS_SCNIP_MASK 0x200u
8053 #define TSI_GENCS_SCNIP_SHIFT 9
8054 #define TSI_GENCS_OVRF_MASK 0x1000u
8055 #define TSI_GENCS_OVRF_SHIFT 12
8056 #define TSI_GENCS_EXTERF_MASK 0x2000u
8057 #define TSI_GENCS_EXTERF_SHIFT 13
8058 #define TSI_GENCS_OUTRGF_MASK 0x4000u
8059 #define TSI_GENCS_OUTRGF_SHIFT 14
8060 #define TSI_GENCS_EOSF_MASK 0x8000u
8061 #define TSI_GENCS_EOSF_SHIFT 15
8062 #define TSI_GENCS_PS_MASK 0x70000u
8063 #define TSI_GENCS_PS_SHIFT 16
8064 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
8065 #define TSI_GENCS_NSCN_MASK 0xF80000u
8066 #define TSI_GENCS_NSCN_SHIFT 19
8067 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
8068 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
8069 #define TSI_GENCS_LPSCNITV_SHIFT 24
8070 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
8071 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
8072 #define TSI_GENCS_LPCLKS_SHIFT 28
8073 /* SCANC Bit Fields */
8074 #define TSI_SCANC_AMPSC_MASK 0x7u
8075 #define TSI_SCANC_AMPSC_SHIFT 0
8076 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
8077 #define TSI_SCANC_AMCLKS_MASK 0x18u
8078 #define TSI_SCANC_AMCLKS_SHIFT 3
8079 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
8080 #define TSI_SCANC_SMOD_MASK 0xFF00u
8081 #define TSI_SCANC_SMOD_SHIFT 8
8082 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
8083 #define TSI_SCANC_EXTCHRG_MASK 0xF0000u
8084 #define TSI_SCANC_EXTCHRG_SHIFT 16
8085 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
8086 #define TSI_SCANC_REFCHRG_MASK 0xF000000u
8087 #define TSI_SCANC_REFCHRG_SHIFT 24
8088 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
8089 /* PEN Bit Fields */
8090 #define TSI_PEN_PEN0_MASK 0x1u
8091 #define TSI_PEN_PEN0_SHIFT 0
8092 #define TSI_PEN_PEN1_MASK 0x2u
8093 #define TSI_PEN_PEN1_SHIFT 1
8094 #define TSI_PEN_PEN2_MASK 0x4u
8095 #define TSI_PEN_PEN2_SHIFT 2
8096 #define TSI_PEN_PEN3_MASK 0x8u
8097 #define TSI_PEN_PEN3_SHIFT 3
8098 #define TSI_PEN_PEN4_MASK 0x10u
8099 #define TSI_PEN_PEN4_SHIFT 4
8100 #define TSI_PEN_PEN5_MASK 0x20u
8101 #define TSI_PEN_PEN5_SHIFT 5
8102 #define TSI_PEN_PEN6_MASK 0x40u
8103 #define TSI_PEN_PEN6_SHIFT 6
8104 #define TSI_PEN_PEN7_MASK 0x80u
8105 #define TSI_PEN_PEN7_SHIFT 7
8106 #define TSI_PEN_PEN8_MASK 0x100u
8107 #define TSI_PEN_PEN8_SHIFT 8
8108 #define TSI_PEN_PEN9_MASK 0x200u
8109 #define TSI_PEN_PEN9_SHIFT 9
8110 #define TSI_PEN_PEN10_MASK 0x400u
8111 #define TSI_PEN_PEN10_SHIFT 10
8112 #define TSI_PEN_PEN11_MASK 0x800u
8113 #define TSI_PEN_PEN11_SHIFT 11
8114 #define TSI_PEN_PEN12_MASK 0x1000u
8115 #define TSI_PEN_PEN12_SHIFT 12
8116 #define TSI_PEN_PEN13_MASK 0x2000u
8117 #define TSI_PEN_PEN13_SHIFT 13
8118 #define TSI_PEN_PEN14_MASK 0x4000u
8119 #define TSI_PEN_PEN14_SHIFT 14
8120 #define TSI_PEN_PEN15_MASK 0x8000u
8121 #define TSI_PEN_PEN15_SHIFT 15
8122 #define TSI_PEN_LPSP_MASK 0xF0000u
8123 #define TSI_PEN_LPSP_SHIFT 16
8124 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
8125 /* WUCNTR Bit Fields */
8126 #define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
8127 #define TSI_WUCNTR_WUCNT_SHIFT 0
8128 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
8129 /* CNTR1 Bit Fields */
8130 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
8131 #define TSI_CNTR1_CTN1_SHIFT 0
8132 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
8133 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
8134 #define TSI_CNTR1_CTN_SHIFT 16
8135 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
8136 /* CNTR3 Bit Fields */
8137 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
8138 #define TSI_CNTR3_CTN1_SHIFT 0
8139 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
8140 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
8141 #define TSI_CNTR3_CTN_SHIFT 16
8142 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
8143 /* CNTR5 Bit Fields */
8144 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
8145 #define TSI_CNTR5_CTN1_SHIFT 0
8146 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
8147 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
8148 #define TSI_CNTR5_CTN_SHIFT 16
8149 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
8150 /* CNTR7 Bit Fields */
8151 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
8152 #define TSI_CNTR7_CTN1_SHIFT 0
8153 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
8154 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
8155 #define TSI_CNTR7_CTN_SHIFT 16
8156 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
8157 /* CNTR9 Bit Fields */
8158 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
8159 #define TSI_CNTR9_CTN1_SHIFT 0
8160 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
8161 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
8162 #define TSI_CNTR9_CTN_SHIFT 16
8163 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
8164 /* CNTR11 Bit Fields */
8165 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
8166 #define TSI_CNTR11_CTN1_SHIFT 0
8167 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
8168 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
8169 #define TSI_CNTR11_CTN_SHIFT 16
8170 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
8171 /* CNTR13 Bit Fields */
8172 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
8173 #define TSI_CNTR13_CTN1_SHIFT 0
8174 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
8175 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
8176 #define TSI_CNTR13_CTN_SHIFT 16
8177 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
8178 /* CNTR15 Bit Fields */
8179 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
8180 #define TSI_CNTR15_CTN1_SHIFT 0
8181 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
8182 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
8183 #define TSI_CNTR15_CTN_SHIFT 16
8184 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
8185 /* THRESHOLD Bit Fields */
8186 #define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
8187 #define TSI_THRESHOLD_HTHH_SHIFT 0
8188 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
8189 #define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
8190 #define TSI_THRESHOLD_LTHH_SHIFT 16
8191 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
8192 
8193 /**
8194  * @}
8195  */ /* end of group TSI_Register_Masks */
8196 
8197 
8198 /* TSI - Peripheral instance base addresses */
8199 /** Peripheral TSI0 base address */
8200 #define TSI0_BASE (0x40045000u)
8201 /** Peripheral TSI0 base pointer */
8202 #define TSI0 ((TSI_Type *)TSI0_BASE)
8203 /** Array initializer of TSI peripheral base pointers */
8204 #define TSI_BASES { TSI0 }
8205 
8206 /**
8207  * @}
8208  */ /* end of group TSI_Peripheral_Access_Layer */
8209 
8210 
8211 /* ----------------------------------------------------------------------------
8212  -- UART Peripheral Access Layer
8213  ---------------------------------------------------------------------------- */
8214 
8215 /**
8216  * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
8217  * @{
8218  */
8219 
8220 /** UART - Register Layout Typedef */
8221 typedef struct {
8222  __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
8223  __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
8224  __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
8225  __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
8226  __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
8227  __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
8228  __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
8229  __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
8230  __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
8231  __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
8232  __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
8233  __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
8234  __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
8235  __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
8236  __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
8237  uint8_t RESERVED_0[1];
8238  __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
8239  __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
8240  __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
8241  __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
8242  __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
8243  __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
8244  __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
8245  uint8_t RESERVED_1[1];
8246  __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
8247  __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
8248  __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
8249  union { /* offset: 0x1B */
8250  __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
8251  __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
8252  };
8253  __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
8254  __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
8255  __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
8256  __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
8257  uint8_t RESERVED_2[1];
8258  __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
8259  __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
8260  __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
8261  __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
8262  __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
8263  __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
8264  __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
8265  __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
8266  __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
8267  __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
8268  __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
8269  __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
8270  __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
8271  __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
8272  __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
8273  __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
8274  __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
8275 } UART_Type;
8276 
8277 /* ----------------------------------------------------------------------------
8278  -- UART Register Masks
8279  ---------------------------------------------------------------------------- */
8280 
8281 /**
8282  * @addtogroup UART_Register_Masks UART Register Masks
8283  * @{
8284  */
8285 
8286 /* BDH Bit Fields */
8287 #define UART_BDH_SBR_MASK 0x1Fu
8288 #define UART_BDH_SBR_SHIFT 0
8289 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
8290 #define UART_BDH_RXEDGIE_MASK 0x40u
8291 #define UART_BDH_RXEDGIE_SHIFT 6
8292 #define UART_BDH_LBKDIE_MASK 0x80u
8293 #define UART_BDH_LBKDIE_SHIFT 7
8294 /* BDL Bit Fields */
8295 #define UART_BDL_SBR_MASK 0xFFu
8296 #define UART_BDL_SBR_SHIFT 0
8297 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
8298 /* C1 Bit Fields */
8299 #define UART_C1_PT_MASK 0x1u
8300 #define UART_C1_PT_SHIFT 0
8301 #define UART_C1_PE_MASK 0x2u
8302 #define UART_C1_PE_SHIFT 1
8303 #define UART_C1_ILT_MASK 0x4u
8304 #define UART_C1_ILT_SHIFT 2
8305 #define UART_C1_WAKE_MASK 0x8u
8306 #define UART_C1_WAKE_SHIFT 3
8307 #define UART_C1_M_MASK 0x10u
8308 #define UART_C1_M_SHIFT 4
8309 #define UART_C1_RSRC_MASK 0x20u
8310 #define UART_C1_RSRC_SHIFT 5
8311 #define UART_C1_UARTSWAI_MASK 0x40u
8312 #define UART_C1_UARTSWAI_SHIFT 6
8313 #define UART_C1_LOOPS_MASK 0x80u
8314 #define UART_C1_LOOPS_SHIFT 7
8315 /* C2 Bit Fields */
8316 #define UART_C2_SBK_MASK 0x1u
8317 #define UART_C2_SBK_SHIFT 0
8318 #define UART_C2_RWU_MASK 0x2u
8319 #define UART_C2_RWU_SHIFT 1
8320 #define UART_C2_RE_MASK 0x4u
8321 #define UART_C2_RE_SHIFT 2
8322 #define UART_C2_TE_MASK 0x8u
8323 #define UART_C2_TE_SHIFT 3
8324 #define UART_C2_ILIE_MASK 0x10u
8325 #define UART_C2_ILIE_SHIFT 4
8326 #define UART_C2_RIE_MASK 0x20u
8327 #define UART_C2_RIE_SHIFT 5
8328 #define UART_C2_TCIE_MASK 0x40u
8329 #define UART_C2_TCIE_SHIFT 6
8330 #define UART_C2_TIE_MASK 0x80u
8331 #define UART_C2_TIE_SHIFT 7
8332 /* S1 Bit Fields */
8333 #define UART_S1_PF_MASK 0x1u
8334 #define UART_S1_PF_SHIFT 0
8335 #define UART_S1_FE_MASK 0x2u
8336 #define UART_S1_FE_SHIFT 1
8337 #define UART_S1_NF_MASK 0x4u
8338 #define UART_S1_NF_SHIFT 2
8339 #define UART_S1_OR_MASK 0x8u
8340 #define UART_S1_OR_SHIFT 3
8341 #define UART_S1_IDLE_MASK 0x10u
8342 #define UART_S1_IDLE_SHIFT 4
8343 #define UART_S1_RDRF_MASK 0x20u
8344 #define UART_S1_RDRF_SHIFT 5
8345 #define UART_S1_TC_MASK 0x40u
8346 #define UART_S1_TC_SHIFT 6
8347 #define UART_S1_TDRE_MASK 0x80u
8348 #define UART_S1_TDRE_SHIFT 7
8349 /* S2 Bit Fields */
8350 #define UART_S2_RAF_MASK 0x1u
8351 #define UART_S2_RAF_SHIFT 0
8352 #define UART_S2_LBKDE_MASK 0x2u
8353 #define UART_S2_LBKDE_SHIFT 1
8354 #define UART_S2_BRK13_MASK 0x4u
8355 #define UART_S2_BRK13_SHIFT 2
8356 #define UART_S2_RWUID_MASK 0x8u
8357 #define UART_S2_RWUID_SHIFT 3
8358 #define UART_S2_RXINV_MASK 0x10u
8359 #define UART_S2_RXINV_SHIFT 4
8360 #define UART_S2_MSBF_MASK 0x20u
8361 #define UART_S2_MSBF_SHIFT 5
8362 #define UART_S2_RXEDGIF_MASK 0x40u
8363 #define UART_S2_RXEDGIF_SHIFT 6
8364 #define UART_S2_LBKDIF_MASK 0x80u
8365 #define UART_S2_LBKDIF_SHIFT 7
8366 /* C3 Bit Fields */
8367 #define UART_C3_PEIE_MASK 0x1u
8368 #define UART_C3_PEIE_SHIFT 0
8369 #define UART_C3_FEIE_MASK 0x2u
8370 #define UART_C3_FEIE_SHIFT 1
8371 #define UART_C3_NEIE_MASK 0x4u
8372 #define UART_C3_NEIE_SHIFT 2
8373 #define UART_C3_ORIE_MASK 0x8u
8374 #define UART_C3_ORIE_SHIFT 3
8375 #define UART_C3_TXINV_MASK 0x10u
8376 #define UART_C3_TXINV_SHIFT 4
8377 #define UART_C3_TXDIR_MASK 0x20u
8378 #define UART_C3_TXDIR_SHIFT 5
8379 #define UART_C3_T8_MASK 0x40u
8380 #define UART_C3_T8_SHIFT 6
8381 #define UART_C3_R8_MASK 0x80u
8382 #define UART_C3_R8_SHIFT 7
8383 /* D Bit Fields */
8384 #define UART_D_RT_MASK 0xFFu
8385 #define UART_D_RT_SHIFT 0
8386 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
8387 /* MA1 Bit Fields */
8388 #define UART_MA1_MA_MASK 0xFFu
8389 #define UART_MA1_MA_SHIFT 0
8390 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
8391 /* MA2 Bit Fields */
8392 #define UART_MA2_MA_MASK 0xFFu
8393 #define UART_MA2_MA_SHIFT 0
8394 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
8395 /* C4 Bit Fields */
8396 #define UART_C4_BRFA_MASK 0x1Fu
8397 #define UART_C4_BRFA_SHIFT 0
8398 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
8399 #define UART_C4_M10_MASK 0x20u
8400 #define UART_C4_M10_SHIFT 5
8401 #define UART_C4_MAEN2_MASK 0x40u
8402 #define UART_C4_MAEN2_SHIFT 6
8403 #define UART_C4_MAEN1_MASK 0x80u
8404 #define UART_C4_MAEN1_SHIFT 7
8405 /* C5 Bit Fields */
8406 #define UART_C5_RDMAS_MASK 0x20u
8407 #define UART_C5_RDMAS_SHIFT 5
8408 #define UART_C5_TDMAS_MASK 0x80u
8409 #define UART_C5_TDMAS_SHIFT 7
8410 /* ED Bit Fields */
8411 #define UART_ED_PARITYE_MASK 0x40u
8412 #define UART_ED_PARITYE_SHIFT 6
8413 #define UART_ED_NOISY_MASK 0x80u
8414 #define UART_ED_NOISY_SHIFT 7
8415 /* MODEM Bit Fields */
8416 #define UART_MODEM_TXCTSE_MASK 0x1u
8417 #define UART_MODEM_TXCTSE_SHIFT 0
8418 #define UART_MODEM_TXRTSE_MASK 0x2u
8419 #define UART_MODEM_TXRTSE_SHIFT 1
8420 #define UART_MODEM_TXRTSPOL_MASK 0x4u
8421 #define UART_MODEM_TXRTSPOL_SHIFT 2
8422 #define UART_MODEM_RXRTSE_MASK 0x8u
8423 #define UART_MODEM_RXRTSE_SHIFT 3
8424 /* IR Bit Fields */
8425 #define UART_IR_TNP_MASK 0x3u
8426 #define UART_IR_TNP_SHIFT 0
8427 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
8428 #define UART_IR_IREN_MASK 0x4u
8429 #define UART_IR_IREN_SHIFT 2
8430 /* PFIFO Bit Fields */
8431 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
8432 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
8433 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
8434 #define UART_PFIFO_RXFE_MASK 0x8u
8435 #define UART_PFIFO_RXFE_SHIFT 3
8436 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
8437 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
8438 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
8439 #define UART_PFIFO_TXFE_MASK 0x80u
8440 #define UART_PFIFO_TXFE_SHIFT 7
8441 /* CFIFO Bit Fields */
8442 #define UART_CFIFO_RXUFE_MASK 0x1u
8443 #define UART_CFIFO_RXUFE_SHIFT 0
8444 #define UART_CFIFO_TXOFE_MASK 0x2u
8445 #define UART_CFIFO_TXOFE_SHIFT 1
8446 #define UART_CFIFO_RXOFE_MASK 0x4u
8447 #define UART_CFIFO_RXOFE_SHIFT 2
8448 #define UART_CFIFO_RXFLUSH_MASK 0x40u
8449 #define UART_CFIFO_RXFLUSH_SHIFT 6
8450 #define UART_CFIFO_TXFLUSH_MASK 0x80u
8451 #define UART_CFIFO_TXFLUSH_SHIFT 7
8452 /* SFIFO Bit Fields */
8453 #define UART_SFIFO_RXUF_MASK 0x1u
8454 #define UART_SFIFO_RXUF_SHIFT 0
8455 #define UART_SFIFO_TXOF_MASK 0x2u
8456 #define UART_SFIFO_TXOF_SHIFT 1
8457 #define UART_SFIFO_RXOF_MASK 0x4u
8458 #define UART_SFIFO_RXOF_SHIFT 2
8459 #define UART_SFIFO_RXEMPT_MASK 0x40u
8460 #define UART_SFIFO_RXEMPT_SHIFT 6
8461 #define UART_SFIFO_TXEMPT_MASK 0x80u
8462 #define UART_SFIFO_TXEMPT_SHIFT 7
8463 /* TWFIFO Bit Fields */
8464 #define UART_TWFIFO_TXWATER_MASK 0xFFu
8465 #define UART_TWFIFO_TXWATER_SHIFT 0
8466 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
8467 /* TCFIFO Bit Fields */
8468 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
8469 #define UART_TCFIFO_TXCOUNT_SHIFT 0
8470 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
8471 /* RWFIFO Bit Fields */
8472 #define UART_RWFIFO_RXWATER_MASK 0xFFu
8473 #define UART_RWFIFO_RXWATER_SHIFT 0
8474 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
8475 /* RCFIFO Bit Fields */
8476 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
8477 #define UART_RCFIFO_RXCOUNT_SHIFT 0
8478 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
8479 /* C7816 Bit Fields */
8480 #define UART_C7816_ISO_7816E_MASK 0x1u
8481 #define UART_C7816_ISO_7816E_SHIFT 0
8482 #define UART_C7816_TTYPE_MASK 0x2u
8483 #define UART_C7816_TTYPE_SHIFT 1
8484 #define UART_C7816_INIT_MASK 0x4u
8485 #define UART_C7816_INIT_SHIFT 2
8486 #define UART_C7816_ANACK_MASK 0x8u
8487 #define UART_C7816_ANACK_SHIFT 3
8488 #define UART_C7816_ONACK_MASK 0x10u
8489 #define UART_C7816_ONACK_SHIFT 4
8490 /* IE7816 Bit Fields */
8491 #define UART_IE7816_RXTE_MASK 0x1u
8492 #define UART_IE7816_RXTE_SHIFT 0
8493 #define UART_IE7816_TXTE_MASK 0x2u
8494 #define UART_IE7816_TXTE_SHIFT 1
8495 #define UART_IE7816_GTVE_MASK 0x4u
8496 #define UART_IE7816_GTVE_SHIFT 2
8497 #define UART_IE7816_INITDE_MASK 0x10u
8498 #define UART_IE7816_INITDE_SHIFT 4
8499 #define UART_IE7816_BWTE_MASK 0x20u
8500 #define UART_IE7816_BWTE_SHIFT 5
8501 #define UART_IE7816_CWTE_MASK 0x40u
8502 #define UART_IE7816_CWTE_SHIFT 6
8503 #define UART_IE7816_WTE_MASK 0x80u
8504 #define UART_IE7816_WTE_SHIFT 7
8505 /* IS7816 Bit Fields */
8506 #define UART_IS7816_RXT_MASK 0x1u
8507 #define UART_IS7816_RXT_SHIFT 0
8508 #define UART_IS7816_TXT_MASK 0x2u
8509 #define UART_IS7816_TXT_SHIFT 1
8510 #define UART_IS7816_GTV_MASK 0x4u
8511 #define UART_IS7816_GTV_SHIFT 2
8512 #define UART_IS7816_INITD_MASK 0x10u
8513 #define UART_IS7816_INITD_SHIFT 4
8514 #define UART_IS7816_BWT_MASK 0x20u
8515 #define UART_IS7816_BWT_SHIFT 5
8516 #define UART_IS7816_CWT_MASK 0x40u
8517 #define UART_IS7816_CWT_SHIFT 6
8518 #define UART_IS7816_WT_MASK 0x80u
8519 #define UART_IS7816_WT_SHIFT 7
8520 /* WP7816_T_TYPE0 Bit Fields */
8521 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
8522 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
8523 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
8524 /* WP7816_T_TYPE1 Bit Fields */
8525 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
8526 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
8527 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
8528 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
8529 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
8530 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
8531 /* WN7816 Bit Fields */
8532 #define UART_WN7816_GTN_MASK 0xFFu
8533 #define UART_WN7816_GTN_SHIFT 0
8534 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
8535 /* WF7816 Bit Fields */
8536 #define UART_WF7816_GTFD_MASK 0xFFu
8537 #define UART_WF7816_GTFD_SHIFT 0
8538 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
8539 /* ET7816 Bit Fields */
8540 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
8541 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
8542 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
8543 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
8544 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
8545 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
8546 /* TL7816 Bit Fields */
8547 #define UART_TL7816_TLEN_MASK 0xFFu
8548 #define UART_TL7816_TLEN_SHIFT 0
8549 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
8550 /* C6 Bit Fields */
8551 #define UART_C6_CP_MASK 0x10u
8552 #define UART_C6_CP_SHIFT 4
8553 #define UART_C6_CE_MASK 0x20u
8554 #define UART_C6_CE_SHIFT 5
8555 #define UART_C6_TX709_MASK 0x40u
8556 #define UART_C6_TX709_SHIFT 6
8557 #define UART_C6_EN709_MASK 0x80u
8558 #define UART_C6_EN709_SHIFT 7
8559 /* PCTH Bit Fields */
8560 #define UART_PCTH_PCTH_MASK 0xFFu
8561 #define UART_PCTH_PCTH_SHIFT 0
8562 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
8563 /* PCTL Bit Fields */
8564 #define UART_PCTL_PCTL_MASK 0xFFu
8565 #define UART_PCTL_PCTL_SHIFT 0
8566 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
8567 /* B1T Bit Fields */
8568 #define UART_B1T_B1T_MASK 0xFFu
8569 #define UART_B1T_B1T_SHIFT 0
8570 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
8571 /* SDTH Bit Fields */
8572 #define UART_SDTH_SDTH_MASK 0xFFu
8573 #define UART_SDTH_SDTH_SHIFT 0
8574 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
8575 /* SDTL Bit Fields */
8576 #define UART_SDTL_SDTL_MASK 0xFFu
8577 #define UART_SDTL_SDTL_SHIFT 0
8578 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
8579 /* PRE Bit Fields */
8580 #define UART_PRE_PREAMBLE_MASK 0xFFu
8581 #define UART_PRE_PREAMBLE_SHIFT 0
8582 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
8583 /* TPL Bit Fields */
8584 #define UART_TPL_TPL_MASK 0xFFu
8585 #define UART_TPL_TPL_SHIFT 0
8586 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
8587 /* IE Bit Fields */
8588 #define UART_IE_TXFIE_MASK 0x1u
8589 #define UART_IE_TXFIE_SHIFT 0
8590 #define UART_IE_PSIE_MASK 0x2u
8591 #define UART_IE_PSIE_SHIFT 1
8592 #define UART_IE_PCTEIE_MASK 0x4u
8593 #define UART_IE_PCTEIE_SHIFT 2
8594 #define UART_IE_PTXIE_MASK 0x8u
8595 #define UART_IE_PTXIE_SHIFT 3
8596 #define UART_IE_PRXIE_MASK 0x10u
8597 #define UART_IE_PRXIE_SHIFT 4
8598 #define UART_IE_ISDIE_MASK 0x20u
8599 #define UART_IE_ISDIE_SHIFT 5
8600 #define UART_IE_WBEIE_MASK 0x40u
8601 #define UART_IE_WBEIE_SHIFT 6
8602 /* WB Bit Fields */
8603 #define UART_WB_WBASE_MASK 0xFFu
8604 #define UART_WB_WBASE_SHIFT 0
8605 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
8606 /* S3 Bit Fields */
8607 #define UART_S3_TXFF_MASK 0x1u
8608 #define UART_S3_TXFF_SHIFT 0
8609 #define UART_S3_PSF_MASK 0x2u
8610 #define UART_S3_PSF_SHIFT 1
8611 #define UART_S3_PCTEF_MASK 0x4u
8612 #define UART_S3_PCTEF_SHIFT 2
8613 #define UART_S3_PTXF_MASK 0x8u
8614 #define UART_S3_PTXF_SHIFT 3
8615 #define UART_S3_PRXF_MASK 0x10u
8616 #define UART_S3_PRXF_SHIFT 4
8617 #define UART_S3_ISD_MASK 0x20u
8618 #define UART_S3_ISD_SHIFT 5
8619 #define UART_S3_WBEF_MASK 0x40u
8620 #define UART_S3_WBEF_SHIFT 6
8621 #define UART_S3_PEF_MASK 0x80u
8622 #define UART_S3_PEF_SHIFT 7
8623 /* S4 Bit Fields */
8624 #define UART_S4_FE_MASK 0x1u
8625 #define UART_S4_FE_SHIFT 0
8626 #define UART_S4_ILCV_MASK 0x2u
8627 #define UART_S4_ILCV_SHIFT 1
8628 #define UART_S4_CDET_MASK 0xCu
8629 #define UART_S4_CDET_SHIFT 2
8630 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
8631 #define UART_S4_INITF_MASK 0x10u
8632 #define UART_S4_INITF_SHIFT 4
8633 /* RPL Bit Fields */
8634 #define UART_RPL_RPL_MASK 0xFFu
8635 #define UART_RPL_RPL_SHIFT 0
8636 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
8637 /* RPREL Bit Fields */
8638 #define UART_RPREL_RPREL_MASK 0xFFu
8639 #define UART_RPREL_RPREL_SHIFT 0
8640 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
8641 /* CPW Bit Fields */
8642 #define UART_CPW_CPW_MASK 0xFFu
8643 #define UART_CPW_CPW_SHIFT 0
8644 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
8645 /* RIDT Bit Fields */
8646 #define UART_RIDT_RIDT_MASK 0xFFu
8647 #define UART_RIDT_RIDT_SHIFT 0
8648 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
8649 /* TIDT Bit Fields */
8650 #define UART_TIDT_TIDT_MASK 0xFFu
8651 #define UART_TIDT_TIDT_SHIFT 0
8652 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
8653 
8654 /**
8655  * @}
8656  */ /* end of group UART_Register_Masks */
8657 
8658 
8659 /* UART - Peripheral instance base addresses */
8660 /** Peripheral UART0 base address */
8661 #define UART0_BASE (0x4006A000u)
8662 /** Peripheral UART0 base pointer */
8663 #define UART0 ((UART_Type *)UART0_BASE)
8664 /** Peripheral UART1 base address */
8665 #define UART1_BASE (0x4006B000u)
8666 /** Peripheral UART1 base pointer */
8667 #define UART1 ((UART_Type *)UART1_BASE)
8668 /** Peripheral UART2 base address */
8669 #define UART2_BASE (0x4006C000u)
8670 /** Peripheral UART2 base pointer */
8671 #define UART2 ((UART_Type *)UART2_BASE)
8672 /** Peripheral UART3 base address */
8673 #define UART3_BASE (0x4006D000u)
8674 /** Peripheral UART3 base pointer */
8675 #define UART3 ((UART_Type *)UART3_BASE)
8676 /** Peripheral UART4 base address */
8677 #define UART4_BASE (0x400EA000u)
8678 /** Peripheral UART4 base pointer */
8679 #define UART4 ((UART_Type *)UART4_BASE)
8680 /** Peripheral UART5 base address */
8681 #define UART5_BASE (0x400EB000u)
8682 /** Peripheral UART5 base pointer */
8683 #define UART5 ((UART_Type *)UART5_BASE)
8684 /** Array initializer of UART peripheral base pointers */
8685 #define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
8686 
8687 /**
8688  * @}
8689  */ /* end of group UART_Peripheral_Access_Layer */
8690 
8691 
8692 /* ----------------------------------------------------------------------------
8693  -- USB Peripheral Access Layer
8694  ---------------------------------------------------------------------------- */
8695 
8696 /**
8697  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
8698  * @{
8699  */
8700 
8701 /** USB - Register Layout Typedef */
8702 typedef struct {
8703  __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
8704  uint8_t RESERVED_0[3];
8705  __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
8706  uint8_t RESERVED_1[3];
8707  __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
8708  uint8_t RESERVED_2[3];
8709  __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
8710  uint8_t RESERVED_3[3];
8711  __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
8712  uint8_t RESERVED_4[3];
8713  __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
8714  uint8_t RESERVED_5[3];
8715  __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
8716  uint8_t RESERVED_6[3];
8717  __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
8718  uint8_t RESERVED_7[99];
8719  __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
8720  uint8_t RESERVED_8[3];
8721  __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
8722  uint8_t RESERVED_9[3];
8723  __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
8724  uint8_t RESERVED_10[3];
8725  __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
8726  uint8_t RESERVED_11[3];
8727  __I uint8_t STAT; /**< Status register, offset: 0x90 */
8728  uint8_t RESERVED_12[3];
8729  __IO uint8_t CTL; /**< Control register, offset: 0x94 */
8730  uint8_t RESERVED_13[3];
8731  __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
8732  uint8_t RESERVED_14[3];
8733  __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
8734  uint8_t RESERVED_15[3];
8735  __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
8736  uint8_t RESERVED_16[3];
8737  __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
8738  uint8_t RESERVED_17[3];
8739  __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
8740  uint8_t RESERVED_18[3];
8741  __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
8742  uint8_t RESERVED_19[3];
8743  __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
8744  uint8_t RESERVED_20[3];
8745  __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
8746  uint8_t RESERVED_21[11];
8747  struct { /* offset: 0xC0, array step: 0x4 */
8748  __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
8749  uint8_t RESERVED_0[3];
8750  } ENDPOINT[16];
8751  __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
8752  uint8_t RESERVED_22[3];
8753  __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
8754  uint8_t RESERVED_23[3];
8755  __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
8756  uint8_t RESERVED_24[3];
8757  __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
8758  uint8_t RESERVED_25[7];
8759  __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
8760 } USB_Type;
8761 
8762 /* ----------------------------------------------------------------------------
8763  -- USB Register Masks
8764  ---------------------------------------------------------------------------- */
8765 
8766 /**
8767  * @addtogroup USB_Register_Masks USB Register Masks
8768  * @{
8769  */
8770 
8771 /* PERID Bit Fields */
8772 #define USB_PERID_ID_MASK 0x3Fu
8773 #define USB_PERID_ID_SHIFT 0
8774 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
8775 /* IDCOMP Bit Fields */
8776 #define USB_IDCOMP_NID_MASK 0x3Fu
8777 #define USB_IDCOMP_NID_SHIFT 0
8778 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
8779 /* REV Bit Fields */
8780 #define USB_REV_REV_MASK 0xFFu
8781 #define USB_REV_REV_SHIFT 0
8782 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
8783 /* ADDINFO Bit Fields */
8784 #define USB_ADDINFO_IEHOST_MASK 0x1u
8785 #define USB_ADDINFO_IEHOST_SHIFT 0
8786 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
8787 #define USB_ADDINFO_IRQNUM_SHIFT 3
8788 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
8789 /* OTGISTAT Bit Fields */
8790 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
8791 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
8792 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
8793 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
8794 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
8795 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
8796 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
8797 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
8798 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
8799 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
8800 #define USB_OTGISTAT_IDCHG_MASK 0x80u
8801 #define USB_OTGISTAT_IDCHG_SHIFT 7
8802 /* OTGICR Bit Fields */
8803 #define USB_OTGICR_AVBUSEN_MASK 0x1u
8804 #define USB_OTGICR_AVBUSEN_SHIFT 0
8805 #define USB_OTGICR_BSESSEN_MASK 0x4u
8806 #define USB_OTGICR_BSESSEN_SHIFT 2
8807 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
8808 #define USB_OTGICR_SESSVLDEN_SHIFT 3
8809 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
8810 #define USB_OTGICR_LINESTATEEN_SHIFT 5
8811 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
8812 #define USB_OTGICR_ONEMSECEN_SHIFT 6
8813 #define USB_OTGICR_IDEN_MASK 0x80u
8814 #define USB_OTGICR_IDEN_SHIFT 7
8815 /* OTGSTAT Bit Fields */
8816 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
8817 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
8818 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
8819 #define USB_OTGSTAT_BSESSEND_SHIFT 2
8820 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
8821 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
8822 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
8823 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
8824 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
8825 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
8826 #define USB_OTGSTAT_ID_MASK 0x80u
8827 #define USB_OTGSTAT_ID_SHIFT 7
8828 /* OTGCTL Bit Fields */
8829 #define USB_OTGCTL_OTGEN_MASK 0x4u
8830 #define USB_OTGCTL_OTGEN_SHIFT 2
8831 #define USB_OTGCTL_DMLOW_MASK 0x10u
8832 #define USB_OTGCTL_DMLOW_SHIFT 4
8833 #define USB_OTGCTL_DPLOW_MASK 0x20u
8834 #define USB_OTGCTL_DPLOW_SHIFT 5
8835 #define USB_OTGCTL_DPHIGH_MASK 0x80u
8836 #define USB_OTGCTL_DPHIGH_SHIFT 7
8837 /* ISTAT Bit Fields */
8838 #define USB_ISTAT_USBRST_MASK 0x1u
8839 #define USB_ISTAT_USBRST_SHIFT 0
8840 #define USB_ISTAT_ERROR_MASK 0x2u
8841 #define USB_ISTAT_ERROR_SHIFT 1
8842 #define USB_ISTAT_SOFTOK_MASK 0x4u
8843 #define USB_ISTAT_SOFTOK_SHIFT 2
8844 #define USB_ISTAT_TOKDNE_MASK 0x8u
8845 #define USB_ISTAT_TOKDNE_SHIFT 3
8846 #define USB_ISTAT_SLEEP_MASK 0x10u
8847 #define USB_ISTAT_SLEEP_SHIFT 4
8848 #define USB_ISTAT_RESUME_MASK 0x20u
8849 #define USB_ISTAT_RESUME_SHIFT 5
8850 #define USB_ISTAT_ATTACH_MASK 0x40u
8851 #define USB_ISTAT_ATTACH_SHIFT 6
8852 #define USB_ISTAT_STALL_MASK 0x80u
8853 #define USB_ISTAT_STALL_SHIFT 7
8854 /* INTEN Bit Fields */
8855 #define USB_INTEN_USBRSTEN_MASK 0x1u
8856 #define USB_INTEN_USBRSTEN_SHIFT 0
8857 #define USB_INTEN_ERROREN_MASK 0x2u
8858 #define USB_INTEN_ERROREN_SHIFT 1
8859 #define USB_INTEN_SOFTOKEN_MASK 0x4u
8860 #define USB_INTEN_SOFTOKEN_SHIFT 2
8861 #define USB_INTEN_TOKDNEEN_MASK 0x8u
8862 #define USB_INTEN_TOKDNEEN_SHIFT 3
8863 #define USB_INTEN_SLEEPEN_MASK 0x10u
8864 #define USB_INTEN_SLEEPEN_SHIFT 4
8865 #define USB_INTEN_RESUMEEN_MASK 0x20u
8866 #define USB_INTEN_RESUMEEN_SHIFT 5
8867 #define USB_INTEN_ATTACHEN_MASK 0x40u
8868 #define USB_INTEN_ATTACHEN_SHIFT 6
8869 #define USB_INTEN_STALLEN_MASK 0x80u
8870 #define USB_INTEN_STALLEN_SHIFT 7
8871 /* ERRSTAT Bit Fields */
8872 #define USB_ERRSTAT_PIDERR_MASK 0x1u
8873 #define USB_ERRSTAT_PIDERR_SHIFT 0
8874 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
8875 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
8876 #define USB_ERRSTAT_CRC16_MASK 0x4u
8877 #define USB_ERRSTAT_CRC16_SHIFT 2
8878 #define USB_ERRSTAT_DFN8_MASK 0x8u
8879 #define USB_ERRSTAT_DFN8_SHIFT 3
8880 #define USB_ERRSTAT_BTOERR_MASK 0x10u
8881 #define USB_ERRSTAT_BTOERR_SHIFT 4
8882 #define USB_ERRSTAT_DMAERR_MASK 0x20u
8883 #define USB_ERRSTAT_DMAERR_SHIFT 5
8884 #define USB_ERRSTAT_BTSERR_MASK 0x80u
8885 #define USB_ERRSTAT_BTSERR_SHIFT 7
8886 /* ERREN Bit Fields */
8887 #define USB_ERREN_PIDERREN_MASK 0x1u
8888 #define USB_ERREN_PIDERREN_SHIFT 0
8889 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
8890 #define USB_ERREN_CRC5EOFEN_SHIFT 1
8891 #define USB_ERREN_CRC16EN_MASK 0x4u
8892 #define USB_ERREN_CRC16EN_SHIFT 2
8893 #define USB_ERREN_DFN8EN_MASK 0x8u
8894 #define USB_ERREN_DFN8EN_SHIFT 3
8895 #define USB_ERREN_BTOERREN_MASK 0x10u
8896 #define USB_ERREN_BTOERREN_SHIFT 4
8897 #define USB_ERREN_DMAERREN_MASK 0x20u
8898 #define USB_ERREN_DMAERREN_SHIFT 5
8899 #define USB_ERREN_BTSERREN_MASK 0x80u
8900 #define USB_ERREN_BTSERREN_SHIFT 7
8901 /* STAT Bit Fields */
8902 #define USB_STAT_ODD_MASK 0x4u
8903 #define USB_STAT_ODD_SHIFT 2
8904 #define USB_STAT_TX_MASK 0x8u
8905 #define USB_STAT_TX_SHIFT 3
8906 #define USB_STAT_ENDP_MASK 0xF0u
8907 #define USB_STAT_ENDP_SHIFT 4
8908 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
8909 /* CTL Bit Fields */
8910 #define USB_CTL_USBENSOFEN_MASK 0x1u
8911 #define USB_CTL_USBENSOFEN_SHIFT 0
8912 #define USB_CTL_ODDRST_MASK 0x2u
8913 #define USB_CTL_ODDRST_SHIFT 1
8914 #define USB_CTL_RESUME_MASK 0x4u
8915 #define USB_CTL_RESUME_SHIFT 2
8916 #define USB_CTL_HOSTMODEEN_MASK 0x8u
8917 #define USB_CTL_HOSTMODEEN_SHIFT 3
8918 #define USB_CTL_RESET_MASK 0x10u
8919 #define USB_CTL_RESET_SHIFT 4
8920 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
8921 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
8922 #define USB_CTL_SE0_MASK 0x40u
8923 #define USB_CTL_SE0_SHIFT 6
8924 #define USB_CTL_JSTATE_MASK 0x80u
8925 #define USB_CTL_JSTATE_SHIFT 7
8926 /* ADDR Bit Fields */
8927 #define USB_ADDR_ADDR_MASK 0x7Fu
8928 #define USB_ADDR_ADDR_SHIFT 0
8929 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
8930 #define USB_ADDR_LSEN_MASK 0x80u
8931 #define USB_ADDR_LSEN_SHIFT 7
8932 /* BDTPAGE1 Bit Fields */
8933 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
8934 #define USB_BDTPAGE1_BDTBA_SHIFT 1
8935 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
8936 /* FRMNUML Bit Fields */
8937 #define USB_FRMNUML_FRM_MASK 0xFFu
8938 #define USB_FRMNUML_FRM_SHIFT 0
8939 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
8940 /* FRMNUMH Bit Fields */
8941 #define USB_FRMNUMH_FRM_MASK 0x7u
8942 #define USB_FRMNUMH_FRM_SHIFT 0
8943 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
8944 /* TOKEN Bit Fields */
8945 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
8946 #define USB_TOKEN_TOKENENDPT_SHIFT 0
8947 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
8948 #define USB_TOKEN_TOKENPID_MASK 0xF0u
8949 #define USB_TOKEN_TOKENPID_SHIFT 4
8950 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
8951 /* SOFTHLD Bit Fields */
8952 #define USB_SOFTHLD_CNT_MASK 0xFFu
8953 #define USB_SOFTHLD_CNT_SHIFT 0
8954 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
8955 /* BDTPAGE2 Bit Fields */
8956 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
8957 #define USB_BDTPAGE2_BDTBA_SHIFT 0
8958 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
8959 /* BDTPAGE3 Bit Fields */
8960 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
8961 #define USB_BDTPAGE3_BDTBA_SHIFT 0
8962 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
8963 /* ENDPT Bit Fields */
8964 #define USB_ENDPT_EPHSHK_MASK 0x1u
8965 #define USB_ENDPT_EPHSHK_SHIFT 0
8966 #define USB_ENDPT_EPSTALL_MASK 0x2u
8967 #define USB_ENDPT_EPSTALL_SHIFT 1
8968 #define USB_ENDPT_EPTXEN_MASK 0x4u
8969 #define USB_ENDPT_EPTXEN_SHIFT 2
8970 #define USB_ENDPT_EPRXEN_MASK 0x8u
8971 #define USB_ENDPT_EPRXEN_SHIFT 3
8972 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
8973 #define USB_ENDPT_EPCTLDIS_SHIFT 4
8974 #define USB_ENDPT_RETRYDIS_MASK 0x40u
8975 #define USB_ENDPT_RETRYDIS_SHIFT 6
8976 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
8977 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
8978 /* USBCTRL Bit Fields */
8979 #define USB_USBCTRL_PDE_MASK 0x40u
8980 #define USB_USBCTRL_PDE_SHIFT 6
8981 #define USB_USBCTRL_SUSP_MASK 0x80u
8982 #define USB_USBCTRL_SUSP_SHIFT 7
8983 /* OBSERVE Bit Fields */
8984 #define USB_OBSERVE_DMPD_MASK 0x10u
8985 #define USB_OBSERVE_DMPD_SHIFT 4
8986 #define USB_OBSERVE_DPPD_MASK 0x40u
8987 #define USB_OBSERVE_DPPD_SHIFT 6
8988 #define USB_OBSERVE_DPPU_MASK 0x80u
8989 #define USB_OBSERVE_DPPU_SHIFT 7
8990 /* CONTROL Bit Fields */
8991 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
8992 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
8993 /* USBTRC0 Bit Fields */
8994 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
8995 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
8996 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
8997 #define USB_USBTRC0_SYNC_DET_SHIFT 1
8998 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
8999 #define USB_USBTRC0_USBRESMEN_SHIFT 5
9000 #define USB_USBTRC0_USBRESET_MASK 0x80u
9001 #define USB_USBTRC0_USBRESET_SHIFT 7
9002 /* USBFRMADJUST Bit Fields */
9003 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
9004 #define USB_USBFRMADJUST_ADJ_SHIFT 0
9005 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
9006 
9007 /**
9008  * @}
9009  */ /* end of group USB_Register_Masks */
9010 
9011 
9012 /* USB - Peripheral instance base addresses */
9013 /** Peripheral USB0 base address */
9014 #define USB0_BASE (0x40072000u)
9015 /** Peripheral USB0 base pointer */
9016 #define USB0 ((USB_Type *)USB0_BASE)
9017 /** Array initializer of USB peripheral base pointers */
9018 #define USB_BASES { USB0 }
9019 
9020 /**
9021  * @}
9022  */ /* end of group USB_Peripheral_Access_Layer */
9023 
9024 
9025 /* ----------------------------------------------------------------------------
9026  -- USBDCD Peripheral Access Layer
9027  ---------------------------------------------------------------------------- */
9028 
9029 /**
9030  * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
9031  * @{
9032  */
9033 
9034 /** USBDCD - Register Layout Typedef */
9035 typedef struct {
9036  __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
9037  __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
9038  __I uint32_t STATUS; /**< Status register, offset: 0x8 */
9039  uint8_t RESERVED_0[4];
9040  __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
9041  __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
9042  __IO uint32_t TIMER2; /**< TIMER2 register, offset: 0x18 */
9043 } USBDCD_Type;
9044 
9045 /* ----------------------------------------------------------------------------
9046  -- USBDCD Register Masks
9047  ---------------------------------------------------------------------------- */
9048 
9049 /**
9050  * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
9051  * @{
9052  */
9053 
9054 /* CONTROL Bit Fields */
9055 #define USBDCD_CONTROL_IACK_MASK 0x1u
9056 #define USBDCD_CONTROL_IACK_SHIFT 0
9057 #define USBDCD_CONTROL_IF_MASK 0x100u
9058 #define USBDCD_CONTROL_IF_SHIFT 8
9059 #define USBDCD_CONTROL_IE_MASK 0x10000u
9060 #define USBDCD_CONTROL_IE_SHIFT 16
9061 #define USBDCD_CONTROL_START_MASK 0x1000000u
9062 #define USBDCD_CONTROL_START_SHIFT 24
9063 #define USBDCD_CONTROL_SR_MASK 0x2000000u
9064 #define USBDCD_CONTROL_SR_SHIFT 25
9065 /* CLOCK Bit Fields */
9066 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
9067 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
9068 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
9069 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
9070 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
9071 /* STATUS Bit Fields */
9072 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
9073 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
9074 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
9075 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
9076 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
9077 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
9078 #define USBDCD_STATUS_ERR_MASK 0x100000u
9079 #define USBDCD_STATUS_ERR_SHIFT 20
9080 #define USBDCD_STATUS_TO_MASK 0x200000u
9081 #define USBDCD_STATUS_TO_SHIFT 21
9082 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
9083 #define USBDCD_STATUS_ACTIVE_SHIFT 22
9084 /* TIMER0 Bit Fields */
9085 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
9086 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
9087 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
9088 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
9089 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
9090 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
9091 /* TIMER1 Bit Fields */
9092 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
9093 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
9094 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
9095 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
9096 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
9097 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
9098 /* TIMER2 Bit Fields */
9099 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
9100 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
9101 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
9102 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
9103 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
9104 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
9105 
9106 /**
9107  * @}
9108  */ /* end of group USBDCD_Register_Masks */
9109 
9110 
9111 /* USBDCD - Peripheral instance base addresses */
9112 /** Peripheral USBDCD base address */
9113 #define USBDCD_BASE (0x40035000u)
9114 /** Peripheral USBDCD base pointer */
9115 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
9116 /** Array initializer of USBDCD peripheral base pointers */
9117 #define USBDCD_BASES { USBDCD }
9118 
9119 /**
9120  * @}
9121  */ /* end of group USBDCD_Peripheral_Access_Layer */
9122 
9123 
9124 /* ----------------------------------------------------------------------------
9125  -- VREF Peripheral Access Layer
9126  ---------------------------------------------------------------------------- */
9127 
9128 /**
9129  * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
9130  * @{
9131  */
9132 
9133 /** VREF - Register Layout Typedef */
9134 typedef struct {
9135  __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
9136  __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
9137 } VREF_Type;
9138 
9139 /* ----------------------------------------------------------------------------
9140  -- VREF Register Masks
9141  ---------------------------------------------------------------------------- */
9142 
9143 /**
9144  * @addtogroup VREF_Register_Masks VREF Register Masks
9145  * @{
9146  */
9147 
9148 /* TRM Bit Fields */
9149 #define VREF_TRM_TRIM_MASK 0x3Fu
9150 #define VREF_TRM_TRIM_SHIFT 0
9151 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
9152 #define VREF_TRM_CHOPEN_MASK 0x40u
9153 #define VREF_TRM_CHOPEN_SHIFT 6
9154 /* SC Bit Fields */
9155 #define VREF_SC_MODE_LV_MASK 0x3u
9156 #define VREF_SC_MODE_LV_SHIFT 0
9157 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
9158 #define VREF_SC_VREFST_MASK 0x4u
9159 #define VREF_SC_VREFST_SHIFT 2
9160 #define VREF_SC_ICOMPEN_MASK 0x20u
9161 #define VREF_SC_ICOMPEN_SHIFT 5
9162 #define VREF_SC_REGEN_MASK 0x40u
9163 #define VREF_SC_REGEN_SHIFT 6
9164 #define VREF_SC_VREFEN_MASK 0x80u
9165 #define VREF_SC_VREFEN_SHIFT 7
9166 
9167 /**
9168  * @}
9169  */ /* end of group VREF_Register_Masks */
9170 
9171 
9172 /* VREF - Peripheral instance base addresses */
9173 /** Peripheral VREF base address */
9174 #define VREF_BASE (0x40074000u)
9175 /** Peripheral VREF base pointer */
9176 #define VREF ((VREF_Type *)VREF_BASE)
9177 /** Array initializer of VREF peripheral base pointers */
9178 #define VREF_BASES { VREF }
9179 
9180 /**
9181  * @}
9182  */ /* end of group VREF_Peripheral_Access_Layer */
9183 
9184 
9185 /* ----------------------------------------------------------------------------
9186  -- WDOG Peripheral Access Layer
9187  ---------------------------------------------------------------------------- */
9188 
9189 /**
9190  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
9191  * @{
9192  */
9193 
9194 /** WDOG - Register Layout Typedef */
9195 typedef struct {
9196  __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
9197  __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
9198  __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
9199  __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
9200  __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
9201  __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
9202  __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
9203  __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
9204  __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
9205  __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
9206  __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
9207  __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
9208 } WDOG_Type;
9209 
9210 /* ----------------------------------------------------------------------------
9211  -- WDOG Register Masks
9212  ---------------------------------------------------------------------------- */
9213 
9214 /**
9215  * @addtogroup WDOG_Register_Masks WDOG Register Masks
9216  * @{
9217  */
9218 
9219 /* STCTRLH Bit Fields */
9220 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
9221 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
9222 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
9223 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
9224 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
9225 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
9226 #define WDOG_STCTRLH_WINEN_MASK 0x8u
9227 #define WDOG_STCTRLH_WINEN_SHIFT 3
9228 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
9229 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
9230 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
9231 #define WDOG_STCTRLH_DBGEN_SHIFT 5
9232 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
9233 #define WDOG_STCTRLH_STOPEN_SHIFT 6
9234 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
9235 #define WDOG_STCTRLH_WAITEN_SHIFT 7
9236 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
9237 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
9238 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
9239 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
9240 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
9241 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
9242 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
9243 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
9244 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
9245 /* STCTRLL Bit Fields */
9246 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
9247 #define WDOG_STCTRLL_INTFLG_SHIFT 15
9248 /* TOVALH Bit Fields */
9249 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
9250 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
9251 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
9252 /* TOVALL Bit Fields */
9253 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
9254 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
9255 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
9256 /* WINH Bit Fields */
9257 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
9258 #define WDOG_WINH_WINHIGH_SHIFT 0
9259 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
9260 /* WINL Bit Fields */
9261 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
9262 #define WDOG_WINL_WINLOW_SHIFT 0
9263 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
9264 /* REFRESH Bit Fields */
9265 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
9266 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
9267 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
9268 /* UNLOCK Bit Fields */
9269 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
9270 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
9271 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
9272 /* TMROUTH Bit Fields */
9273 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
9274 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
9275 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
9276 /* TMROUTL Bit Fields */
9277 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
9278 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
9279 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
9280 /* RSTCNT Bit Fields */
9281 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
9282 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
9283 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
9284 /* PRESC Bit Fields */
9285 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
9286 #define WDOG_PRESC_PRESCVAL_SHIFT 8
9287 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
9288 
9289 /**
9290  * @}
9291  */ /* end of group WDOG_Register_Masks */
9292 
9293 
9294 /* WDOG - Peripheral instance base addresses */
9295 /** Peripheral WDOG base address */
9296 #define WDOG_BASE (0x40052000u)
9297 /** Peripheral WDOG base pointer */
9298 #define WDOG ((WDOG_Type *)WDOG_BASE)
9299 /** Array initializer of WDOG peripheral base pointers */
9300 #define WDOG_BASES { WDOG }
9301 
9302 /**
9303  * @}
9304  */ /* end of group WDOG_Peripheral_Access_Layer */
9305 
9306 
9307 /*
9308 ** End of section using anonymous unions
9309 */
9310 
9311 #if defined(__ARMCC_VERSION)
9312  #pragma pop
9313 #elif defined(__CWCC__)
9314  #pragma pop
9315 #elif defined(__GNUC__)
9316  /* leave anonymous unions enabled */
9317 #elif defined(__IAR_SYSTEMS_ICC__)
9318  #pragma language=default
9319 #else
9320  #error Not supported compiler type
9321 #endif
9322 
9323 /**
9324  * @}
9325  */ /* end of group Peripheral_access_layer */
9326 
9327 
9328 /* ----------------------------------------------------------------------------
9329  -- Backward Compatibility
9330  ---------------------------------------------------------------------------- */
9331 
9332 /**
9333  * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
9334  * @{
9335  */
9336 
9337 #define SDHC_WML_WRBRSTLEN_MASK This_symbol_has_been_deprecated
9338 #define SDHC_WML_WRBRSTLEN_SHIFT This_symbol_has_been_deprecated
9339 #define SDHC_WML_WRBRSTLEN(x) This_symbol_has_been_deprecated
9340 #define CAN_IMASK2_BUFHM_MASK This_symbol_has_been_deprecated
9341 #define CAN_IMASK2_BUFHM_SHIFT This_symbol_has_been_deprecated
9342 #define CAN_IMASK2_BUFHM(x) This_symbol_has_been_deprecated
9343 #define CAN_IFLAG2_BUFHI_MASK This_symbol_has_been_deprecated
9344 #define CAN_IFLAG2_BUFHI_SHIFT This_symbol_has_been_deprecated
9345 #define CAN_IFLAG2_BUFHI(x) This_symbol_has_been_deprecated
9346 #define DAC_DATL_DATA_MASK DAC_DATL_DATA0_MASK
9347 #define DAC_DATL_DATA_SHIFT DAC_DATL_DATA0_SHIFT
9348 #define DAC_DATL_DATA(x) DAC_DATL_DATA0(x)
9349 #define DAC_DATH_DATA_MASK DAC_DATH_DATA1_MASK
9350 #define DAC_DATH_DATA_SHIFT DAC_DATH_DATA1_SHIFT
9351 #define DAC_DATH_DATA(x) DAC_DATH_DATA1(x)
9352 #define MCG_S_LOLS0_MASK MCG_S_LOLS_MASK
9353 #define MCG_S_LOLS0_SHIFT MCG_S_LOLS_SHIFT
9354 #define SIM_SCGC6_RNGA_MASK This_symbol_has_been_deprecated
9355 #define SIM_SCGC6_RNGA_SHIFT This_symbol_has_been_deprecated
9356 
9357 /**
9358  * @}
9359  */ /* end of group Backward_Compatibility_Symbols */
9360 
9361 
9362 #endif /* #if !defined(MK60D10_H_) */
9363 
9364 /* MK60D10.h, eof. */
RCM_Type::MR
__I uint8_t MR
Mode Register, offset: 0x7.
Definition: MK60D10.h:6457
I2S_Type::RCR4
__IO uint32_t RCR4
SAI Receive Configuration 4 Register, offset: 0x90.
Definition: MK60D10.h:4867
DMA_Type::ES
__I uint32_t ES
Error Status Register, offset: 0x4.
Definition: MK60D10.h:2449
PDB_Type::INTC
__IO uint32_t INTC
DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8.
Definition: MK60D10.h:6057
CAN_Type::CTRL2
__IO uint32_t CTRL2
Control 2 register, offset: 0x34.
Definition: MK60D10.h:1502
UART_Type::ED
__I uint8_t ED
UART Extended Data Register, offset: 0xC.
Definition: MK60D10.h:8234
ENET_Type::RMON_R_P65TO127
__IO uint32_t RMON_R_P65TO127
RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC.
Definition: MK60D10.h:3200
CAU_Type::AESC_CAA
__O uint32_t AESC_CAA
Accumulator register - AES Column Operation command, offset: 0xB04.
Definition: MK60D10.h:1840
CAN0_Wake_Up_IRQn
CAN0 wake up interrupt.
Definition: MK60D10.h:130
DMA10_IRQn
DMA Channel 10 Transfer Complete.
Definition: MK60D10.h:106
USB_Type::CONTROL
__IO uint8_t CONTROL
USB OTG Control register, offset: 0x108.
Definition: MK60D10.h:8755
RNG_Type::ER
__O uint32_t ER
RNGA Entropy Register, offset: 0x8.
Definition: MK60D10.h:6652
FTFL_Type::FCCOB7
__IO uint8_t FCCOB7
Flash Common Command Object Registers, offset: 0x8.
Definition: MK60D10.h:3954
DMA8_IRQn
DMA Channel 8 Transfer Complete.
Definition: MK60D10.h:104
NV_Type::FSEC
__I uint8_t FSEC
Non-volatile Flash Security Register, offset: 0xC.
Definition: MK60D10.h:5871
ADC_Type::CFG1
__IO uint32_t CFG1
ADC Configuration Register 1, offset: 0x8.
Definition: MK60D10.h:268
MCG_Type::C2
__IO uint8_t C2
MCG Control 2 Register, offset: 0x1.
Definition: MK60D10.h:5420
AIPS_Type::PACRB
__IO uint32_t PACRB
Peripheral Access Control Register, offset: 0x24.
Definition: MK60D10.h:491
UART_Type::BDL
__IO uint8_t BDL
UART Baud Rate Registers: Low, offset: 0x1.
Definition: MK60D10.h:8223
CMP0_IRQn
CMP0 interrupt.
Definition: MK60D10.h:155
ENET_Type::FTRL
__IO uint32_t FTRL
Frame Truncation Length, offset: 0x1B0.
Definition: MK60D10.h:3154
UART_Type::WP7816_T_TYPE0
__IO uint8_t WP7816_T_TYPE0
UART 7816 Wait Parameter Register, offset: 0x1B.
Definition: MK60D10.h:8250
I2C_Type::S
__IO uint8_t S
I2C Status register, offset: 0x3.
Definition: MK60D10.h:4696
Reserved108_IRQn
Reserved interrupt 108.
Definition: MK60D10.h:188
FTM_Type::EXTTRIG
__IO uint32_t EXTTRIG
FTM External Trigger, offset: 0x6C.
Definition: MK60D10.h:4142
ADC_Type::CLPS
__IO uint32_t CLPS
ADC Plus-Side General Calibration Value Register, offset: 0x38.
Definition: MK60D10.h:279
CAN_Type::ID
__IO uint32_t ID
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10...
Definition: MK60D10.h:1511
ENET_Type::RMON_R_FRAME_OK
__IO uint32_t RMON_R_FRAME_OK
Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC.
Definition: MK60D10.h:3208
UART0_RX_TX_IRQn
UART0 Receive/Transmit interrupt.
Definition: MK60D10.h:141
FTM_Type::FILTER
__IO uint32_t FILTER
Input Capture Filter Control, offset: 0x78.
Definition: MK60D10.h:4145
RNG_IRQn
RNGB Interrupt.
Definition: MK60D10.h:119
CMT_Type::DMA
__IO uint8_t DMA
CMT Direct Memory Access Register, offset: 0xB.
Definition: MK60D10.h:2073
PIT1_IRQn
PIT timer channel 1 interrupt.
Definition: MK60D10.h:165
DMA_Type::ATTR
__IO uint16_t ATTR
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20.
Definition: MK60D10.h:2489
PDB_Type::CNT
__I uint32_t CNT
Counter Register, offset: 0x8.
Definition: MK60D10.h:6047
DAC0_IRQn
DAC0 interrupt.
Definition: MK60D10.h:177
SIM_Type::SOPT1CFG
__IO uint32_t SOPT1CFG
SOPT1 Configuration Register, offset: 0x4.
Definition: MK60D10.h:7330
DMA_Type::DADDR
__IO uint32_t DADDR
TCD Destination Address, array offset: 0x1010, array step: 0x20.
Definition: MK60D10.h:2496
DMA_Type::DCHPRI13
__IO uint8_t DCHPRI13
Channel n Priority Register, offset: 0x10E.
Definition: MK60D10.h:2483
LPTimer_IRQn
LPTimer interrupt.
Definition: MK60D10.h:181
DMA_Type::CEEI
__O uint8_t CEEI
Clear Enable Error Interrupt Register, offset: 0x18.
Definition: MK60D10.h:2454
PMC_Type::LVDSC1
__IO uint8_t LVDSC1
Low Voltage Detect Status And Control 1 register, offset: 0x0.
Definition: MK60D10.h:6258
USB_Type::STAT
__I uint8_t STAT
Status register, offset: 0x90.
Definition: MK60D10.h:8727
PDB0_IRQn
PDB0 Interrupt.
Definition: MK60D10.h:168
ENET_Type::MRBR
__IO uint32_t MRBR
Maximum Receive Buffer Size Register, offset: 0x188.
Definition: MK60D10.h:3144
AXBS_Type::MGPCR1
__IO uint32_t MGPCR1
Master General Purpose Control Register, offset: 0x900.
Definition: MK60D10.h:1382
MPU_Type
MPU - Register Layout Typedef.
Definition: MK60D10.h:5686
SPI_Type::POPR
__I uint32_t POPR
POP RX FIFO Register, offset: 0x38.
Definition: MK60D10.h:7757
I2C_Type::RA
__IO uint8_t RA
I2C Range Address register, offset: 0x7.
Definition: MK60D10.h:4700
FTM_Type::FMS
__IO uint32_t FMS
Fault Mode Status, offset: 0x74.
Definition: MK60D10.h:4144
ENET_Type::PALR
__IO uint32_t PALR
Physical Address Lower Register, offset: 0xE4.
Definition: MK60D10.h:3131
ENET_Type::IAUR
__IO uint32_t IAUR
Descriptor Individual Upper Address Register, offset: 0x118.
Definition: MK60D10.h:3135
VREF_Type::SC
__IO uint8_t SC
VREF Status and Control Register, offset: 0x1.
Definition: MK60D10.h:9136
ENET_Type::IEEE_T_OCTETS_OK
__IO uint32_t IEEE_T_OCTETS_OK
Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK).
Definition: MK60D10.h:3188
CRC_Type::GPOLYLL
__IO uint8_t GPOLYLL
CRC_GPOLYLL register., offset: 0x4.
Definition: MK60D10.h:2197
SIM_Type::CLKDIV2
__IO uint32_t CLKDIV2
System Clock Divider Register 2, offset: 0x1048.
Definition: MK60D10.h:7348
RCM_Type
RCM - Register Layout Typedef.
Definition: MK60D10.h:6450
SIM_Type::UIDH
__I uint32_t UIDH
Unique Identification Register High, offset: 0x1054.
Definition: MK60D10.h:7351
FMC_Type::DATA_L
__IO uint32_t DATA_L
Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8.
Definition: MK60D10.h:3803
DMA_Type::SOFF
__IO uint16_t SOFF
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20.
Definition: MK60D10.h:2488
FTFL_Type::FCCOBB
__IO uint8_t FCCOBB
Flash Common Command Object Registers, offset: 0xC.
Definition: MK60D10.h:3958
DMA_Type::CERR
__O uint8_t CERR
Clear Error Register, offset: 0x1E.
Definition: MK60D10.h:2460
ENET_Type::RSEM
__IO uint32_t RSEM
Receive FIFO Section Empty Threshold, offset: 0x194.
Definition: MK60D10.h:3147
DMA_Type::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016...
Definition: MK60D10.h:2500
SDHC_Type::PRSSTAT
__I uint32_t PRSSTAT
Present State register, offset: 0x24.
Definition: MK60D10.h:6898
NV_Type::FPROT0
__I uint8_t FPROT0
Non-volatile P-Flash Protection 0 - High Register, offset: 0xB.
Definition: MK60D10.h:5870
DMA_Type::DCHPRI0
__IO uint8_t DCHPRI0
Channel n Priority Register, offset: 0x103.
Definition: MK60D10.h:2472
Reserved95_IRQn
Reserved interrupt 95.
Definition: MK60D10.h:175
CRC_Type::CRCH
__IO uint16_t CRCH
CRC_CRCH register., offset: 0x2.
Definition: MK60D10.h:2180
CAU_Type::AESIC_CAA
__O uint32_t AESIC_CAA
Accumulator register - AES Inverse Column Operation command, offset: 0xB44.
Definition: MK60D10.h:1844
UART_Type::C7816
__IO uint8_t C7816
UART 7816 Control Register, offset: 0x18.
Definition: MK60D10.h:8246
DAC_Type::DATH
__IO uint8_t DATH
DAC Data High Register, array offset: 0x1, array step: 0x2.
Definition: MK60D10.h:2347
OSC_Type
OSC - Register Layout Typedef.
Definition: MK60D10.h:5989
FTFL_Type
FTFL - Register Layout Typedef.
Definition: MK60D10.h:3945
WDOG_Type::STCTRLH
__IO uint16_t STCTRLH
Watchdog Status and Control Register High, offset: 0x0.
Definition: MK60D10.h:9196
CMT_IRQn
CMT interrupt.
Definition: MK60D10.h:161
CAU_Type::ROTL_CASR
__O uint32_t ROTL_CASR
Status register - Rotate Left command, offset: 0x9C0.
Definition: MK60D10.h:1835
UART_Type::S4
__IO uint8_t S4
UART CEA709.1-B Status Register, offset: 0x2C.
Definition: MK60D10.h:8269
RCM_Type::RPFW
__IO uint8_t RPFW
Reset Pin Filter Width register, offset: 0x5.
Definition: MK60D10.h:6455
CAN_Type::RX14MASK
__IO uint32_t RX14MASK
Rx 14 Mask register, offset: 0x14.
Definition: MK60D10.h:1494
USB_Type::USBTRC0
__IO uint8_t USBTRC0
USB Transceiver Control Register 0, offset: 0x10C.
Definition: MK60D10.h:8757
FTM_Type::SYNCONF
__IO uint32_t SYNCONF
Synchronization Configuration, offset: 0x8C.
Definition: MK60D10.h:4150
FTFL_Type::FCCOB4
__IO uint8_t FCCOB4
Flash Common Command Object Registers, offset: 0xB.
Definition: MK60D10.h:3957
TSI_Type::CNTR9
__I uint32_t CNTR9
Counter Register, offset: 0x110.
Definition: MK60D10.h:8021
ADC_Type::OFS
__IO uint32_t OFS
ADC Offset Correction Register, offset: 0x28.
Definition: MK60D10.h:275
ADC_Type::CLP4
__IO uint32_t CLP4
ADC Plus-Side General Calibration Value Register, offset: 0x3C.
Definition: MK60D10.h:280
AIPS_Type::PACRH
__IO uint32_t PACRH
Peripheral Access Control Register, offset: 0x4C.
Definition: MK60D10.h:498
MCG_Type::C1
__IO uint8_t C1
MCG Control 1 Register, offset: 0x0.
Definition: MK60D10.h:5419
NV_Type
NV - Register Layout Typedef.
Definition: MK60D10.h:5858
CMP1_IRQn
CMP1 interrupt.
Definition: MK60D10.h:156
I2C0_IRQn
I2C0 interrupt.
Definition: MK60D10.h:120
AIPS_Type::PACRO
__IO uint32_t PACRO
Peripheral Access Control Register, offset: 0x68.
Definition: MK60D10.h:505
CAU_Type::RADR_CAA
__O uint32_t RADR_CAA
Accumulator register - Reverse and Add to Register command, offset: 0x904.
Definition: MK60D10.h:1828
ENET_Type
ENET - Register Layout Typedef.
Definition: MK60D10.h:3112
CAN_Type::RXFIR
__I uint32_t RXFIR
Rx FIFO Information Register, offset: 0x4C.
Definition: MK60D10.h:1507
SDHC_Type::SYSCTL
__IO uint32_t SYSCTL
System Control register, offset: 0x2C.
Definition: MK60D10.h:6900
I2C_Type::SLTH
__IO uint8_t SLTH
I2C SCL Low Timeout Register High, offset: 0xA.
Definition: MK60D10.h:4703
DMA_Type::DCHPRI15
__IO uint8_t DCHPRI15
Channel n Priority Register, offset: 0x10C.
Definition: MK60D10.h:2481
SDHC_Type::IRQSIGEN
__IO uint32_t IRQSIGEN
Interrupt Signal Enable register, offset: 0x38.
Definition: MK60D10.h:6903
FTM_Type::MOD
__IO uint32_t MOD
Modulo, offset: 0x8.
Definition: MK60D10.h:4129
ENET_Type::RMON_R_CRC_ALIGN
__IO uint32_t RMON_R_CRC_ALIGN
RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290.
Definition: MK60D10.h:3193
FTM_Type::COMBINE
__IO uint32_t COMBINE
Function For Linked Channels, offset: 0x64.
Definition: MK60D10.h:4140
FTFL_Type::FOPT
__I uint8_t FOPT
Flash Option Register, offset: 0x3.
Definition: MK60D10.h:3949
UART3_RX_TX_IRQn
UART3 Receive/Transmit interrupt.
Definition: MK60D10.h:147
ENET_Type::TFWR
__IO uint32_t TFWR
Transmit FIFO Watermark Register, offset: 0x144.
Definition: MK60D10.h:3140
UART_Type::C3
__IO uint8_t C3
UART Control Register 3, offset: 0x6.
Definition: MK60D10.h:8228
DMA_Type::SSRT
__O uint8_t SSRT
Set START Bit Register, offset: 0x1D.
Definition: MK60D10.h:2459
MCG_Type::C6
__IO uint8_t C6
MCG Control 6 Register, offset: 0x5.
Definition: MK60D10.h:5424
USB_Type
USB - Register Layout Typedef.
Definition: MK60D10.h:8702
DMA3_IRQn
DMA Channel 3 Transfer Complete.
Definition: MK60D10.h:99
LLWU_Type
LLWU - Register Layout Typedef.
Definition: MK60D10.h:5145
SPI_Type::PUSHR
__IO uint32_t PUSHR
PUSH TX FIFO Register In Master Mode, offset: 0x34.
Definition: MK60D10.h:7754
CRC_Type
CRC - Register Layout Typedef.
Definition: MK60D10.h:2176
UART_Type::PCTL
__IO uint8_t PCTL
UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23.
Definition: MK60D10.h:8260
UART_Type::SDTH
__IO uint8_t SDTH
UART CEA709.1-B Secondary Delay Timer High, offset: 0x25.
Definition: MK60D10.h:8262
Reserved118_IRQn
Reserved interrupt 118.
Definition: MK60D10.h:198
UART_Type::C4
__IO uint8_t C4
UART Control Register 4, offset: 0xA.
Definition: MK60D10.h:8232
FTFL_Type::FPROT2
__IO uint8_t FPROT2
Program Flash Protection Registers, offset: 0x11.
Definition: MK60D10.h:3963
ENET_Type::PAUR
__IO uint32_t PAUR
Physical Address Upper Register, offset: 0xE8.
Definition: MK60D10.h:3132
I2S_Type::MCR
__IO uint32_t MCR
SAI MCLK Control Register, offset: 0x100.
Definition: MK60D10.h:4876
MCM_Type::ISR
__IO uint32_t ISR
Interrupt Status Register, offset: 0x10.
Definition: MK60D10.h:5590
MCG_IRQn
MCG Interrupt.
Definition: MK60D10.h:180
DMA_Type::ERQ
__IO uint32_t ERQ
Enable Request Register, offset: 0xC.
Definition: MK60D10.h:2451
UART_Type::IS7816
__IO uint8_t IS7816
UART 7816 Interrupt Status Register, offset: 0x1A.
Definition: MK60D10.h:8248
SDHC_Type::ADMAES
__I uint32_t ADMAES
ADMA Error Status register, offset: 0x54.
Definition: MK60D10.h:6909
ENET_Type::GAUR
__IO uint32_t GAUR
Descriptor Group Upper Address Register, offset: 0x120.
Definition: MK60D10.h:3137
ADC_Type::CLM0
__IO uint32_t CLM0
ADC Minus-Side General Calibration Value Register, offset: 0x6C.
Definition: MK60D10.h:292
EWM_Type::CTRL
__IO uint8_t CTRL
Control Register, offset: 0x0.
Definition: MK60D10.h:3614
ENET_Type::TAFL
__IO uint32_t TAFL
Transmit FIFO Almost Full Threshold, offset: 0x1A8.
Definition: MK60D10.h:3152
ENET_Type::RMON_R_P64
__IO uint32_t RMON_R_P64
RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8.
Definition: MK60D10.h:3199
I2C_Type::SMB
__IO uint8_t SMB
I2C SMBus Control and Status register, offset: 0x8.
Definition: MK60D10.h:4701
CMP_Type::DACCR
__IO uint8_t DACCR
DAC Control Register, offset: 0x4.
Definition: MK60D10.h:1955
WDOG_Type::TOVALH
__IO uint16_t TOVALH
Watchdog Time-out Value Register High, offset: 0x4.
Definition: MK60D10.h:9198
AXBS_Type::MGPCR5
__IO uint32_t MGPCR5
Master General Purpose Control Register, offset: 0xD00.
Definition: MK60D10.h:1390
SDHC_Type::HOSTVER
__I uint32_t HOSTVER
Host Controller Version, offset: 0xFC.
Definition: MK60D10.h:6915
SDHC_Type
SDHC - Register Layout Typedef.
Definition: MK60D10.h:6891
PIT_Type::MCR
__IO uint32_t MCR
PIT Module Control Register, offset: 0x0.
Definition: MK60D10.h:6186
LVD_LVW_IRQn
Low Voltage Detect, Low Voltage Warning.
Definition: MK60D10.h:116
UART_Type::WF7816
__IO uint8_t WF7816
UART 7816 Wait FD Register, offset: 0x1D.
Definition: MK60D10.h:8254
I2S0_Rx_IRQn
I2S0 receive interrupt.
Definition: MK60D10.h:132
FTFL_Type::FPROT1
__IO uint8_t FPROT1
Program Flash Protection Registers, offset: 0x12.
Definition: MK60D10.h:3964
MCG_Type::C5
__IO uint8_t C5
MCG Control 5 Register, offset: 0x4.
Definition: MK60D10.h:5423
MCG_Type::ATCVL
__IO uint8_t ATCVL
MCG Auto Trim Compare Value Low Register, offset: 0xB.
Definition: MK60D10.h:5430
ENET_Type::RMON_T_P128TO255
__IO uint32_t RMON_T_P128TO255
RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230.
Definition: MK60D10.h:3171
CMP_Type::CR0
__IO uint8_t CR0
CMP Control Register 0, offset: 0x0.
Definition: MK60D10.h:1951
SPI_Type::TXFR1
__I uint32_t TXFR1
DSPI Transmit FIFO Registers, offset: 0x40.
Definition: MK60D10.h:7759
DAC_Type::DATL
__IO uint8_t DATL
DAC Data Low Register, array offset: 0x0, array step: 0x2.
Definition: MK60D10.h:2346
CAN0_Error_IRQn
CAN0 error interrupt.
Definition: MK60D10.h:127
SPI_Type::TXFR2
__I uint32_t TXFR2
DSPI Transmit FIFO Registers, offset: 0x44.
Definition: MK60D10.h:7760
SPI2_IRQn
SPI2 Interrupt.
Definition: MK60D10.h:124
RTC_Type
RTC - Register Layout Typedef.
Definition: MK60D10.h:6730
TSI_Type::WUCNTR
__I uint32_t WUCNTR
Wake-Up Channel Counter Register, offset: 0xC.
Definition: MK60D10.h:8015
I2C_Type::A1
__IO uint8_t A1
I2C Address Register 1, offset: 0x0.
Definition: MK60D10.h:4693
MCG_Type
MCG - Register Layout Typedef.
Definition: MK60D10.h:5418
CRC_Type::CRCLL
__IO uint8_t CRCLL
CRC_CRCLL register., offset: 0x0.
Definition: MK60D10.h:2184
USB_Type::ADDR
__IO uint8_t ADDR
Address register, offset: 0x98.
Definition: MK60D10.h:8731
UART_Type::RCFIFO
__I uint8_t RCFIFO
UART FIFO Receive Count, offset: 0x16.
Definition: MK60D10.h:8244
RTC_Type::RAR
__IO uint32_t RAR
RTC Read Access Register, offset: 0x804.
Definition: MK60D10.h:6741
PDB_Type::C1
__IO uint32_t C1
Channel n Control Register 1, array offset: 0x10, array step: 0x28.
Definition: MK60D10.h:6050
GPIO_Type::PSOR
__O uint32_t PSOR
Port Set Output Register, offset: 0x4.
Definition: MK60D10.h:4607
CAN0_Rx_Warning_IRQn
CAN0 Rx warning interrupt.
Definition: MK60D10.h:129
FMC_Type::PFAPR
__IO uint32_t PFAPR
Flash Access Protection Register, offset: 0x0.
Definition: MK60D10.h:3795
CAN1_ORed_Message_buffer_IRQn
CAN1 OR&#39;d message buffers interrupt.
Definition: MK60D10.h:133
UART_Type::TIDT
__IO uint8_t TIDT
UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31.
Definition: MK60D10.h:8274
AXBS_Type::MGPCR2
__IO uint32_t MGPCR2
Master General Purpose Control Register, offset: 0xA00.
Definition: MK60D10.h:1384
FTFL_Type::FDPROT
__IO uint8_t FDPROT
Data Flash Protection Register, offset: 0x17.
Definition: MK60D10.h:3968
CAN1_Tx_Warning_IRQn
CAN1 Tx warning interrupt.
Definition: MK60D10.h:136
AIPS_Type::PACRE
__IO uint32_t PACRE
Peripheral Access Control Register, offset: 0x40.
Definition: MK60D10.h:495
MPU_Type::EDR
__I uint32_t EDR
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8.
Definition: MK60D10.h:5691
CRC_Type::GPOLYL
__IO uint16_t GPOLYL
CRC_GPOLYL register., offset: 0x4.
Definition: MK60D10.h:2192
I2S_Type::TCR2
__IO uint32_t TCR2
SAI Transmit Configuration 2 Register, offset: 0x8.
Definition: MK60D10.h:4852
Reserved102_IRQn
Reserved interrupt 102.
Definition: MK60D10.h:182
CAN0_Tx_Warning_IRQn
CAN0 Tx warning interrupt.
Definition: MK60D10.h:128
UART_Type::PFIFO
__IO uint8_t PFIFO
UART FIFO Parameters, offset: 0x10.
Definition: MK60D10.h:8238
ENET_Type::RMON_T_FRAG
__IO uint32_t RMON_T_FRAG
RMON Tx Packets &lt; 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C.
Definition: MK60D10.h:3166
SDHC_Type::DSADDR
__IO uint32_t DSADDR
DMA System Address register, offset: 0x0.
Definition: MK60D10.h:6892
I2S0_Tx_IRQn
I2S0 transmit interrupt.
Definition: MK60D10.h:131
ENET_Type::ATPER
__IO uint32_t ATPER
Timer Period Register, offset: 0x40C.
Definition: MK60D10.h:3218
UART_Type::IR
__IO uint8_t IR
UART Infrared Register, offset: 0xE.
Definition: MK60D10.h:8236
PORTC_IRQn
Port C interrupt.
Definition: MK60D10.h:185
CAN_Type::TIMER
__IO uint32_t TIMER
Free Running Timer, offset: 0x8.
Definition: MK60D10.h:1491
ADC_Type::CLP3
__IO uint32_t CLP3
ADC Plus-Side General Calibration Value Register, offset: 0x40.
Definition: MK60D10.h:281
SIM_Type::SOPT1
__IO uint32_t SOPT1
System Options Register 1, offset: 0x0.
Definition: MK60D10.h:7329
I2S_Type::RCR3
__IO uint32_t RCR3
SAI Receive Configuration 3 Register, offset: 0x8C.
Definition: MK60D10.h:4866
Reserved117_IRQn
Reserved interrupt 117.
Definition: MK60D10.h:197
SIM_Type::SCGC7
__IO uint32_t SCGC7
System Clock Gating Control Register 7, offset: 0x1040.
Definition: MK60D10.h:7346
SIM_Type::FCFG1
__IO uint32_t FCFG1
Flash Configuration Register 1, offset: 0x104C.
Definition: MK60D10.h:7349
CMT_Type::CMD1
__IO uint8_t CMD1
CMT Modulator Data Register Mark High, offset: 0x6.
Definition: MK60D10.h:2068
PMC_Type
PMC - Register Layout Typedef.
Definition: MK60D10.h:6257
NV_Type::FOPT
__I uint8_t FOPT
Non-volatile Flash Option Register, offset: 0xD.
Definition: MK60D10.h:5872
DMA12_IRQn
DMA Channel 12 Transfer Complete.
Definition: MK60D10.h:108
RNG_Type::SR
__I uint32_t SR
RNGA Status Register, offset: 0x4.
Definition: MK60D10.h:6651
Reserved113_IRQn
Reserved interrupt 113.
Definition: MK60D10.h:193
ENET_Type::EIMR
__IO uint32_t EIMR
Interrupt Mask Register, offset: 0x8.
Definition: MK60D10.h:3115
ENET_Type::RMON_R_P1024TO2047
__IO uint32_t RMON_R_P1024TO2047
RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC.
Definition: MK60D10.h:3204
DMA_Type::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016...
Definition: MK60D10.h:2499
PIT_Type::TCTRL
__IO uint32_t TCTRL
Timer Control Register, array offset: 0x108, array step: 0x10.
Definition: MK60D10.h:6191
ENET_Receive_IRQn
Ethernet MAC Receive Interrupt.
Definition: MK60D10.h:173
ENET_Type::RSFL
__IO uint32_t RSFL
Receive FIFO Section Full Threshold, offset: 0x190.
Definition: MK60D10.h:3146
USB_Type::CTL
__IO uint8_t CTL
Control register, offset: 0x94.
Definition: MK60D10.h:8729
MPU_Type::EAR
__I uint32_t EAR
Error Address Register, slave port n, array offset: 0x10, array step: 0x8.
Definition: MK60D10.h:5690
MCG_Type::C9
__I uint8_t C9
MCG Control 9 Register, offset: 0xE.
Definition: MK60D10.h:5433
FTM_Type::QDCTRL
__IO uint32_t QDCTRL
Quadrature Decoder Control And Status, offset: 0x80.
Definition: MK60D10.h:4147
DMA_Type::DCHPRI7
__IO uint8_t DCHPRI7
Channel n Priority Register, offset: 0x104.
Definition: MK60D10.h:2473
DMA_Type::HRS
__IO uint32_t HRS
Hardware Request Status Register, offset: 0x34.
Definition: MK60D10.h:2467
ENET_Type::IEEE_T_DEF
__IO uint32_t IEEE_T_DEF
Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258.
Definition: MK60D10.h:3181
RTC_Type::TSR
__IO uint32_t TSR
RTC Time Seconds Register, offset: 0x0.
Definition: MK60D10.h:6731
DAC1_IRQn
DAC1 interrupt.
Definition: MK60D10.h:178
ENET_Type::IEEE_R_MACERR
__IO uint32_t IEEE_R_MACERR
Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8.
Definition: MK60D10.h:3211
SPI_Type::MCR
__IO uint32_t MCR
Module Configuration Register, offset: 0x0.
Definition: MK60D10.h:7743
SPI_Type::TXFR3
__I uint32_t TXFR3
DSPI Transmit FIFO Registers, offset: 0x48.
Definition: MK60D10.h:7761
CMP_Type::SCR
__IO uint8_t SCR
CMP Status and Control Register, offset: 0x3.
Definition: MK60D10.h:1954
NV_Type::FEPROT
__I uint8_t FEPROT
Non-volatile EERAM Protection Register, offset: 0xE.
Definition: MK60D10.h:5873
EWM_Type::CLKPRESCALER
__IO uint8_t CLKPRESCALER
Clock Prescaler Register, offset: 0x5.
Definition: MK60D10.h:3619
DMA_Type::INT
__IO uint32_t INT
Interrupt Request Register, offset: 0x24.
Definition: MK60D10.h:2463
UART_Type
UART - Register Layout Typedef.
Definition: MK60D10.h:8221
RTC_Type::IER
__IO uint32_t IER
RTC Interrupt Enable Register, offset: 0x1C.
Definition: MK60D10.h:6738
MCM_Type::PLASC
__I uint16_t PLASC
Crossbar Switch (AXBS) Slave Configuration, offset: 0x8.
Definition: MK60D10.h:5587
MCM_Type::ETBRL
__IO uint32_t ETBRL
ETB Reload register, offset: 0x18.
Definition: MK60D10.h:5592
CMT_Type::CGL1
__IO uint8_t CGL1
CMT Carrier Generator Low Data Register 1, offset: 0x1.
Definition: MK60D10.h:2063
PIT2_IRQn
PIT timer channel 2 interrupt.
Definition: MK60D10.h:166
UART_Type::WP7816_T_TYPE1
__IO uint8_t WP7816_T_TYPE1
UART 7816 Wait Parameter Register, offset: 0x1B.
Definition: MK60D10.h:8251
LLWU_Type::FILT2
__IO uint8_t FILT2
LLWU Pin Filter 2 register, offset: 0x9.
Definition: MK60D10.h:5155
CMT_Type
CMT - Register Layout Typedef.
Definition: MK60D10.h:2061
UART_Type::MA1
__IO uint8_t MA1
UART Match Address Registers 1, offset: 0x8.
Definition: MK60D10.h:8230
SDHC_Type::CMDARG
__IO uint32_t CMDARG
Command Argument register, offset: 0x8.
Definition: MK60D10.h:6894
SDHC_Type::XFERTYP
__IO uint32_t XFERTYP
Transfer Type register, offset: 0xC.
Definition: MK60D10.h:6895
system_MK60D10.h
Device specific configuration file for MK60D10 (header file)
PDB_Type::S
__IO uint32_t S
Channel n Status Register, array offset: 0x14, array step: 0x28.
Definition: MK60D10.h:6051
CAU_Type::LDR_CAA
__O uint32_t LDR_CAA
Accumulator register - Load Register command, offset: 0x844.
Definition: MK60D10.h:1816
DMA_Type::DCHPRI14
__IO uint8_t DCHPRI14
Channel n Priority Register, offset: 0x10D.
Definition: MK60D10.h:2482
SPI_Type
SPI - Register Layout Typedef.
Definition: MK60D10.h:7742
AIPS_Type::MPRA
__IO uint32_t MPRA
Master Privilege Register A, offset: 0x0.
Definition: MK60D10.h:488
CMT_Type::OC
__IO uint8_t OC
CMT Output Control Register, offset: 0x4.
Definition: MK60D10.h:2066
UART_Type::MA2
__IO uint8_t MA2
UART Match Address Registers 2, offset: 0x9.
Definition: MK60D10.h:8231
SIM_Type::UIDMH
__I uint32_t UIDMH
Unique Identification Register Mid-High, offset: 0x1058.
Definition: MK60D10.h:7352
ADC_Type::CV1
__IO uint32_t CV1
Compare Value Registers, offset: 0x18.
Definition: MK60D10.h:271
TSI_Type::CNTR3
__I uint32_t CNTR3
Counter Register, offset: 0x104.
Definition: MK60D10.h:8018
ENET_Type::RMON_R_JAB
__IO uint32_t RMON_R_JAB
RMON Rx Packets &gt; MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0.
Definition: MK60D10.h:3197
AIPS_Type::PACRL
__IO uint32_t PACRL
Peripheral Access Control Register, offset: 0x5C.
Definition: MK60D10.h:502
DMA13_IRQn
DMA Channel 13 Transfer Complete.
Definition: MK60D10.h:109
AIPS_Type::PACRC
__IO uint32_t PACRC
Peripheral Access Control Register, offset: 0x28.
Definition: MK60D10.h:492
UART_Type::IE
__IO uint8_t IE
UART CEA709.1-B Interrupt Enable Register, offset: 0x29.
Definition: MK60D10.h:8266
ADC_Type::CLPD
__IO uint32_t CLPD
ADC Plus-Side General Calibration Value Register, offset: 0x34.
Definition: MK60D10.h:278
MCM_IRQn
Normal Interrupt.
Definition: MK60D10.h:113
USB_Type::TOKEN
__IO uint8_t TOKEN
Token register, offset: 0xA8.
Definition: MK60D10.h:8739
SMC_Type::VLLSCTRL
__IO uint8_t VLLSCTRL
VLLS Control register, offset: 0x2.
Definition: MK60D10.h:7672
CRC_Type::GPOLY
__IO uint32_t GPOLY
CRC Polynomial register, offset: 0x4.
Definition: MK60D10.h:2195
ENET_Type::RMON_T_UNDERSIZE
__IO uint32_t RMON_T_UNDERSIZE
RMON Tx Packets &lt; 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214.
Definition: MK60D10.h:3164
UART_Type::MODEM
__IO uint8_t MODEM
UART Modem Register, offset: 0xD.
Definition: MK60D10.h:8235
GPIO_Type::PTOR
__O uint32_t PTOR
Port Toggle Output Register, offset: 0xC.
Definition: MK60D10.h:4609
ENET_Type::RDSR
__IO uint32_t RDSR
Receive Descriptor Ring Start Register, offset: 0x180.
Definition: MK60D10.h:3142
CAN1_Rx_Warning_IRQn
CAN1 Rx warning interrupt.
Definition: MK60D10.h:137
ENET_Type::RMON_T_JAB
__IO uint32_t RMON_T_JAB
RMON Tx Packets &gt; MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220.
Definition: MK60D10.h:3167
AXBS_Type::MGPCR3
__IO uint32_t MGPCR3
Master General Purpose Control Register, offset: 0xB00.
Definition: MK60D10.h:1386
PDB_Type::SC
__IO uint32_t SC
Status and Control Register, offset: 0x0.
Definition: MK60D10.h:6045
RNG_Type::OR
__I uint32_t OR
RNGA Output Register, offset: 0xC.
Definition: MK60D10.h:6653
PIT3_IRQn
PIT timer channel 3 interrupt.
Definition: MK60D10.h:167
MCM_Type::CR
__IO uint32_t CR
Control Register, offset: 0xC.
Definition: MK60D10.h:5589
SDHC_Type::WML
__IO uint32_t WML
Watermark Level Register, offset: 0x44.
Definition: MK60D10.h:6906
DMA_Type::CSR
__IO uint16_t CSR
TCD Control and Status, array offset: 0x101C, array step: 0x20.
Definition: MK60D10.h:2503
FTM_Type::FLTPOL
__IO uint32_t FLTPOL
FTM Fault Input Polarity, offset: 0x88.
Definition: MK60D10.h:4149
UART_Type::WB
__IO uint8_t WB
UART CEA709.1-B WBASE, offset: 0x2A.
Definition: MK60D10.h:8267
DMAMUX_Type
DMAMUX - Register Layout Typedef.
Definition: MK60D10.h:3062
CAN_Type::CTRL1
__IO uint32_t CTRL1
Control 1 register, offset: 0x4.
Definition: MK60D10.h:1490
FB_Type
FB - Register Layout Typedef.
Definition: MK60D10.h:3685
FTFL_Type::FCCOB1
__IO uint8_t FCCOB1
Flash Common Command Object Registers, offset: 0x6.
Definition: MK60D10.h:3952
SPI_Type::TXFR0
__I uint32_t TXFR0
DSPI Transmit FIFO Registers, offset: 0x3C.
Definition: MK60D10.h:7758
ENET_Type::RCR
__IO uint32_t RCR
Receive Control Register, offset: 0x84.
Definition: MK60D10.h:3127
PORTA_IRQn
Port A interrupt.
Definition: MK60D10.h:183
DMA11_IRQn
DMA Channel 11 Transfer Complete.
Definition: MK60D10.h:107
USB_Type::ADDINFO
__I uint8_t ADDINFO
Peripheral Additional Info register, offset: 0xC.
Definition: MK60D10.h:8709
FTM_Type::PWMLOAD
__IO uint32_t PWMLOAD
FTM PWM Load, offset: 0x98.
Definition: MK60D10.h:4153
LLWU_Type::F3
__I uint8_t F3
LLWU Flag 3 register, offset: 0x7.
Definition: MK60D10.h:5153
ENET_Type::TCR
__IO uint32_t TCR
Transmit Control Register, offset: 0xC4.
Definition: MK60D10.h:3129
AXBS_Type::PRS
__IO uint32_t PRS
Priority Registers Slave, array offset: 0x0, array step: 0x100.
Definition: MK60D10.h:1374
WDOG_Type::PRESC
__IO uint16_t PRESC
Watchdog Prescaler register, offset: 0x16.
Definition: MK60D10.h:9207
ENET_Type::ECR
__IO uint32_t ECR
Ethernet Control Register, offset: 0x24.
Definition: MK60D10.h:3120
CMT_Type::CGL2
__IO uint8_t CGL2
CMT Carrier Generator Low Data Register 2, offset: 0x3.
Definition: MK60D10.h:2065
ENET_Type::OPD
__IO uint32_t OPD
Opcode/Pause Duration Register, offset: 0xEC.
Definition: MK60D10.h:3133
CAN_Type::ECR
__IO uint32_t ECR
Error Counter, offset: 0x1C.
Definition: MK60D10.h:1496
FTFL_Type::FCNFG
__IO uint8_t FCNFG
Flash Configuration Register, offset: 0x1.
Definition: MK60D10.h:3947
Reserved111_IRQn
Reserved interrupt 111.
Definition: MK60D10.h:191
CAU_Type::ADR_CAA
__O uint32_t ADR_CAA
Accumulator register - Add to register command, offset: 0x8C4.
Definition: MK60D10.h:1824
I2S_Type::TCR5
__IO uint32_t TCR5
SAI Transmit Configuration 5 Register, offset: 0x14.
Definition: MK60D10.h:4855
FTM_Type::DEADTIME
__IO uint32_t DEADTIME
Deadtime Insertion Control, offset: 0x68.
Definition: MK60D10.h:4141
DMA0_IRQn
DMA Channel 0 Transfer Complete.
Definition: MK60D10.h:96
TSI_Type::CNTR15
__I uint32_t CNTR15
Counter Register, offset: 0x11C.
Definition: MK60D10.h:8024
USBDCD_Type::STATUS
__I uint32_t STATUS
Status register, offset: 0x8.
Definition: MK60D10.h:9038
ENET_1588_Timer_IRQn
Ethernet MAC IEEE 1588 Timer Interrupt.
Definition: MK60D10.h:171
ADC_Type::SC3
__IO uint32_t SC3
Status and Control Register 3, offset: 0x24.
Definition: MK60D10.h:274
ENET_Type::RMON_R_DROP
__IO uint32_t RMON_R_DROP
Count of frames not counted correctly (IEEE_R_DROP).
Definition: MK60D10.h:3207
SPI_Type::PUSHR_SLAVE
__IO uint32_t PUSHR_SLAVE
PUSH TX FIFO Register In Slave Mode, offset: 0x34.
Definition: MK60D10.h:7755
EWM_Type::SERV
__O uint8_t SERV
Service Register, offset: 0x1.
Definition: MK60D10.h:3615
I2S_Type::TCR1
__IO uint32_t TCR1
SAI Transmit Configuration 1 Register, offset: 0x4.
Definition: MK60D10.h:4851
ENET_Type::RMON_T_DROP
__IO uint32_t RMON_T_DROP
Count of frames not counted correctly (RMON_T_DROP).
Definition: MK60D10.h:3159
AXBS_Type
AXBS - Register Layout Typedef.
Definition: MK60D10.h:1372
ENET_Type::RMON_T_P_GTE2048
__IO uint32_t RMON_T_P_GTE2048
RMON Tx packets w &gt; 2048 bytes (RMON_T_P_GTE2048), offset: 0x240.
Definition: MK60D10.h:3175
LLWU_Type::PE4
__IO uint8_t PE4
LLWU Pin Enable 4 register, offset: 0x3.
Definition: MK60D10.h:5149
I2S_Type::TCR4
__IO uint32_t TCR4
SAI Transmit Configuration 4 Register, offset: 0x10.
Definition: MK60D10.h:4854
SDHC_Type::BLKATTR
__IO uint32_t BLKATTR
Block Attributes register, offset: 0x4.
Definition: MK60D10.h:6893
SIM_Type::SCGC1
__IO uint32_t SCGC1
System Clock Gating Control Register 1, offset: 0x1028.
Definition: MK60D10.h:7340
CMT_Type::MSC
__IO uint8_t MSC
CMT Modulator Status and Control Register, offset: 0x5.
Definition: MK60D10.h:2067
FTFL_IRQn
FTFL Interrupt.
Definition: MK60D10.h:114
RTC_IRQn
RTC interrupt.
Definition: MK60D10.h:162
UART_Type::TPL
__IO uint8_t TPL
UART CEA709.1-B Transmit Packet Length, offset: 0x28.
Definition: MK60D10.h:8265
UART_Type::TCFIFO
__I uint8_t TCFIFO
UART FIFO Transmit Count, offset: 0x14.
Definition: MK60D10.h:8242
DMA_Type::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20.
Definition: MK60D10.h:2493
ENET_Type::TGSR
__IO uint32_t TGSR
Timer Global Status Register, offset: 0x604.
Definition: MK60D10.h:3223
DMA_Type::DCHPRI5
__IO uint8_t DCHPRI5
Channel n Priority Register, offset: 0x106.
Definition: MK60D10.h:2475
ADC_Type::CLM4
__IO uint32_t CLM4
ADC Minus-Side General Calibration Value Register, offset: 0x5C.
Definition: MK60D10.h:288
CAU_Type::STR_CAA
__I uint32_t STR_CAA
Accumulator register - Store Register command, offset: 0x884.
Definition: MK60D10.h:1820
USB_Type::BDTPAGE3
__IO uint8_t BDTPAGE3
BDT Page Register 3, offset: 0xB4.
Definition: MK60D10.h:8745
UART3_ERR_IRQn
UART3 Error interrupt.
Definition: MK60D10.h:148
NV_Type::FDPROT
__I uint8_t FDPROT
Non-volatile D-Flash Protection Register, offset: 0xF.
Definition: MK60D10.h:5874
I2C1_IRQn
I2C1 interrupt.
Definition: MK60D10.h:121
PDB_Type::IDLY
__IO uint32_t IDLY
Interrupt Delay Register, offset: 0xC.
Definition: MK60D10.h:6048
ENET_Type::RMON_T_P65TO127
__IO uint32_t RMON_T_P65TO127
RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C.
Definition: MK60D10.h:3170
ADC_Type::PG
__IO uint32_t PG
ADC Plus-Side Gain Register, offset: 0x2C.
Definition: MK60D10.h:276
ENET_Type::TSEM
__IO uint32_t TSEM
Transmit FIFO Section Empty Threshold, offset: 0x1A0.
Definition: MK60D10.h:3150
FTFL_Type::FPROT0
__IO uint8_t FPROT0
Program Flash Protection Registers, offset: 0x13.
Definition: MK60D10.h:3965
CMT_Type::PPS
__IO uint8_t PPS
CMT Primary Prescaler Register, offset: 0xA.
Definition: MK60D10.h:2072
CAN_Type::WORD0
__IO uint32_t WORD0
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10.
Definition: MK60D10.h:1512
RNG_Type
RNG - Register Layout Typedef.
Definition: MK60D10.h:6649
AIPS_Type::PACRI
__IO uint32_t PACRI
Peripheral Access Control Register, offset: 0x50.
Definition: MK60D10.h:499
PDB_Type::INT
__IO uint32_t INT
DAC Interval n Register, array offset: 0x154, array step: 0x8.
Definition: MK60D10.h:6058
DMA1_IRQn
DMA Channel 1 Transfer Complete.
Definition: MK60D10.h:97
ENET_Type::RMON_T_P512TO1023
__IO uint32_t RMON_T_P512TO1023
RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238.
Definition: MK60D10.h:3173
DMA_Type::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E...
Definition: MK60D10.h:2505
CMT_Type::CGH2
__IO uint8_t CGH2
CMT Carrier Generator High Data Register 2, offset: 0x2.
Definition: MK60D10.h:2064
ENET_Type::TAEM
__IO uint32_t TAEM
Transmit FIFO Almost Empty Threshold, offset: 0x1A4.
Definition: MK60D10.h:3151
ADC_Type::CLMD
__IO uint32_t CLMD
ADC Minus-Side General Calibration Value Register, offset: 0x54.
Definition: MK60D10.h:286
SIM_Type::CLKDIV1
__IO uint32_t CLKDIV1
System Clock Divider Register 1, offset: 0x1044.
Definition: MK60D10.h:7347
ENET_Type::IEEE_T_1COL
__IO uint32_t IEEE_T_1COL
Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250.
Definition: MK60D10.h:3179
CMP2_IRQn
CMP2 interrupt.
Definition: MK60D10.h:157
ADC_Type::CLP0
__IO uint32_t CLP0
ADC Plus-Side General Calibration Value Register, offset: 0x4C.
Definition: MK60D10.h:284
GPIO_Type::PDDR
__IO uint32_t PDDR
Port Data Direction Register, offset: 0x14.
Definition: MK60D10.h:4611
SWI_IRQn
Software interrupt.
Definition: MK60D10.h:190
WDOG_Type::REFRESH
__IO uint16_t REFRESH
Watchdog Refresh register, offset: 0xC.
Definition: MK60D10.h:9202
UART_Type::TWFIFO
__IO uint8_t TWFIFO
UART FIFO Transmit Watermark, offset: 0x13.
Definition: MK60D10.h:8241
CRC_Type::CRC
__IO uint32_t CRC
CRC Data register, offset: 0x0.
Definition: MK60D10.h:2182
MCG_Type::S
__I uint8_t S
MCG Status Register, offset: 0x6.
Definition: MK60D10.h:5425
UART_Type::PRE
__IO uint8_t PRE
UART CEA709.1-B Preamble, offset: 0x27.
Definition: MK60D10.h:8264
NV_Type::BACKKEY4
__I uint8_t BACKKEY4
Backdoor Comparison Key 4., offset: 0x7.
Definition: MK60D10.h:5866
RCM_Type::SRS0
__I uint8_t SRS0
System Reset Status Register 0, offset: 0x0.
Definition: MK60D10.h:6451
RFVBAT_Type
RFVBAT - Register Layout Typedef.
Definition: MK60D10.h:6594
FTM_Type::OUTINIT
__IO uint32_t OUTINIT
Initial State For Channels Output, offset: 0x5C.
Definition: MK60D10.h:4138
SIM_Type::SCGC6
__IO uint32_t SCGC6
System Clock Gating Control Register 6, offset: 0x103C.
Definition: MK60D10.h:7345
ENET_Type::RMON_T_OVERSIZE
__IO uint32_t RMON_T_OVERSIZE
RMON Tx Packets &gt; MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218.
Definition: MK60D10.h:3165
DMA_Type::DCHPRI3
__IO uint8_t DCHPRI3
Channel n Priority Register, offset: 0x100.
Definition: MK60D10.h:2469
AIPS_Type::PACRM
__IO uint32_t PACRM
Peripheral Access Control Register, offset: 0x60.
Definition: MK60D10.h:503
TSI_Type::CNTR7
__I uint32_t CNTR7
Counter Register, offset: 0x10C.
Definition: MK60D10.h:8020
ENET_Type::TACC
__IO uint32_t TACC
Transmit Accelerator Function Configuration, offset: 0x1C0.
Definition: MK60D10.h:3156
UART_Type::CFIFO
__IO uint8_t CFIFO
UART FIFO Control Register, offset: 0x11.
Definition: MK60D10.h:8239
ENET_Type::IEEE_T_MACERR
__IO uint32_t IEEE_T_MACERR
Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264.
Definition: MK60D10.h:3184
NV_Type::BACKKEY3
__I uint8_t BACKKEY3
Backdoor Comparison Key 3., offset: 0x0.
Definition: MK60D10.h:5859
SDHC_Type::ADSADDR
__IO uint32_t ADSADDR
ADMA System Addressregister, offset: 0x58.
Definition: MK60D10.h:6910
UART_Type::C1
__IO uint8_t C1
UART Control Register 1, offset: 0x2.
Definition: MK60D10.h:8224
CAU_Type::LDR_CASR
__O uint32_t LDR_CASR
Status register - Load Register command, offset: 0x840.
Definition: MK60D10.h:1815
ADC_Type::CFG2
__IO uint32_t CFG2
ADC Configuration Register 2, offset: 0xC.
Definition: MK60D10.h:269
PORT_Type::GPCLR
__O uint32_t GPCLR
Global Pin Control Low Register, offset: 0x80.
Definition: MK60D10.h:6334
ADC_Type::CV2
__IO uint32_t CV2
Compare Value Registers, offset: 0x1C.
Definition: MK60D10.h:272
UART_Type::BDH
__IO uint8_t BDH
UART Baud Rate Registers: High, offset: 0x0.
Definition: MK60D10.h:8222
CMP_Type::CR1
__IO uint8_t CR1
CMP Control Register 1, offset: 0x1.
Definition: MK60D10.h:1952
DAC_Type::C0
__IO uint8_t C0
DAC Control Register, offset: 0x21.
Definition: MK60D10.h:2350
FB_Type::CSMR
__IO uint32_t CSMR
Chip Select Mask Register, array offset: 0x4, array step: 0xC.
Definition: MK60D10.h:3688
ENET_Type::TCSR
__IO uint32_t TCSR
Timer Control Status Register, array offset: 0x608, array step: 0x8.
Definition: MK60D10.h:3225
Read_Collision_IRQn
Read Collision Interrupt.
Definition: MK60D10.h:115
UART_Type::SFIFO
__IO uint8_t SFIFO
UART FIFO Status Register, offset: 0x12.
Definition: MK60D10.h:8240
CRC_Type::CRCLU
__IO uint8_t CRCLU
CRC_CRCLU register., offset: 0x1.
Definition: MK60D10.h:2185
DMA_Type::SEEI
__O uint8_t SEEI
Set Enable Error Interrupt Register, offset: 0x19.
Definition: MK60D10.h:2455
WDOG_Type::UNLOCK
__IO uint16_t UNLOCK
Watchdog Unlock register, offset: 0xE.
Definition: MK60D10.h:9203
DMA_Type::CR
__IO uint32_t CR
Control Register, offset: 0x0.
Definition: MK60D10.h:2448
AXBS_Type::CRS
__IO uint32_t CRS
Control Register, array offset: 0x10, array step: 0x100.
Definition: MK60D10.h:1376
UART_Type::WN7816
__IO uint8_t WN7816
UART 7816 Wait N Register, offset: 0x1C.
Definition: MK60D10.h:8253
ADC_Type::SC2
__IO uint32_t SC2
Status and Control Register 2, offset: 0x20.
Definition: MK60D10.h:273
DMA_Type::CDNE
__O uint8_t CDNE
Clear DONE Status Bit Register, offset: 0x1C.
Definition: MK60D10.h:2458
ENET_Type::IEEE_R_FDXFC
__IO uint32_t IEEE_R_FDXFC
Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC.
Definition: MK60D10.h:3212
FTFL_Type::FCCOB8
__IO uint8_t FCCOB8
Flash Common Command Object Registers, offset: 0xF.
Definition: MK60D10.h:3961
FTM_Type::SYNC
__IO uint32_t SYNC
Synchronization, offset: 0x58.
Definition: MK60D10.h:4137
Reserved114_IRQn
Reserved interrupt 114.
Definition: MK60D10.h:194
SPI_Type::RXFR0
__I uint32_t RXFR0
DSPI Receive FIFO Registers, offset: 0x7C.
Definition: MK60D10.h:7763
PIT0_IRQn
PIT timer channel 0 interrupt.
Definition: MK60D10.h:164
CMT_Type::CMD2
__IO uint8_t CMD2
CMT Modulator Data Register Mark Low, offset: 0x7.
Definition: MK60D10.h:2069
ENET_Type::IEEE_T_MCOL
__IO uint32_t IEEE_T_MCOL
Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254.
Definition: MK60D10.h:3180
FB_Type::CSCR
__IO uint32_t CSCR
Chip Select Control Register, array offset: 0x8, array step: 0xC.
Definition: MK60D10.h:3689
NV_Type::BACKKEY6
__I uint8_t BACKKEY6
Backdoor Comparison Key 6., offset: 0x5.
Definition: MK60D10.h:5864
SIM_Type::FCFG2
__I uint32_t FCFG2
Flash Configuration Register 2, offset: 0x1050.
Definition: MK60D10.h:7350
WDOG_Type::TMROUTL
__IO uint16_t TMROUTL
Watchdog Timer Output Register Low, offset: 0x12.
Definition: MK60D10.h:9205
DAC_Type
DAC - Register Layout Typedef.
Definition: MK60D10.h:2344
CMT_Type::CGH1
__IO uint8_t CGH1
CMT Carrier Generator High Data Register 1, offset: 0x0.
Definition: MK60D10.h:2062
TSI_Type::GENCS
__IO uint32_t GENCS
General Control and Status register, offset: 0x0.
Definition: MK60D10.h:8012
MCM_Type::ETBCNT
__I uint32_t ETBCNT
ETB Counter Value register, offset: 0x1C.
Definition: MK60D10.h:5593
RCM_Type::SRS1
__I uint8_t SRS1
System Reset Status Register 1, offset: 0x1.
Definition: MK60D10.h:6452
I2S_Type::RCSR
__IO uint32_t RCSR
SAI Receive Control Register, offset: 0x80.
Definition: MK60D10.h:4863
SIM_Type::SOPT2
__IO uint32_t SOPT2
System Options Register 2, offset: 0x1004.
Definition: MK60D10.h:7332
ENET_Type::RMON_R_RESVD_0
__IO uint32_t RMON_R_RESVD_0
Reserved (RMON_R_RESVD_0), offset: 0x2A4.
Definition: MK60D10.h:3198
USB_Type::FRMNUMH
__IO uint8_t FRMNUMH
Frame Number Register High, offset: 0xA4.
Definition: MK60D10.h:8737
WDOG_Type::WINL
__IO uint16_t WINL
Watchdog Window Register Low, offset: 0xA.
Definition: MK60D10.h:9201
MCG_Type::C4
__IO uint8_t C4
MCG Control 4 Register, offset: 0x3.
Definition: MK60D10.h:5422
OSC_Type::CR
__IO uint8_t CR
OSC Control Register, offset: 0x0.
Definition: MK60D10.h:5990
GPIO_Type::PCOR
__O uint32_t PCOR
Port Clear Output Register, offset: 0x8.
Definition: MK60D10.h:4608
I2C_Type::FLT
__IO uint8_t FLT
I2C Programmable Input Glitch Filter register, offset: 0x6.
Definition: MK60D10.h:4699
TSI_Type
TSI - Register Layout Typedef.
Definition: MK60D10.h:8011
WDOG_Type::TMROUTH
__IO uint16_t TMROUTH
Watchdog Timer Output Register High, offset: 0x10.
Definition: MK60D10.h:9204
ENET_Type::RMON_R_FRAG
__IO uint32_t RMON_R_FRAG
RMON Rx Packets &lt; 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C.
Definition: MK60D10.h:3196
SMC_Type::PMSTAT
__I uint8_t PMSTAT
Power Mode Status register, offset: 0x3.
Definition: MK60D10.h:7673
CMP_Type
CMP - Register Layout Typedef.
Definition: MK60D10.h:1950
ENET_Type::IEEE_R_ALIGN
__IO uint32_t IEEE_R_ALIGN
Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4.
Definition: MK60D10.h:3210
FTM2_IRQn
FTM2 fault, overflow and channels interrupt.
Definition: MK60D10.h:160
FMC_Type::DATA_U
__IO uint32_t DATA_U
Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8.
Definition: MK60D10.h:3802
DMA9_IRQn
DMA Channel 9 Transfer Complete.
Definition: MK60D10.h:105
ENET_Type::IALR
__IO uint32_t IALR
Descriptor Individual Lower Address Register, offset: 0x11C.
Definition: MK60D10.h:3136
SMC_Type
SMC - Register Layout Typedef.
Definition: MK60D10.h:7669
TSI_Type::PEN
__IO uint32_t PEN
Pin Enable register, offset: 0x8.
Definition: MK60D10.h:8014
RTC_Seconds_IRQn
RTC seconds interrupt.
Definition: MK60D10.h:163
ENET_Type::RMON_R_P512TO1023
__IO uint32_t RMON_R_P512TO1023
RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8.
Definition: MK60D10.h:3203
FTM_Type::POL
__IO uint32_t POL
Channels Polarity, offset: 0x70.
Definition: MK60D10.h:4143
CAU_Type
CAU - Register Layout Typedef.
Definition: MK60D10.h:1812
TSI_Type::CNTR1
__I uint32_t CNTR1
Counter Register, offset: 0x100.
Definition: MK60D10.h:8017
CAN_Type::IMASK1
__IO uint32_t IMASK1
Interrupt Masks 1 register, offset: 0x28.
Definition: MK60D10.h:1499
LLWU_Type::PE2
__IO uint8_t PE2
LLWU Pin Enable 2 register, offset: 0x1.
Definition: MK60D10.h:5147
LPTMR_Type::CNR
__I uint32_t CNR
Low Power Timer Counter Register, offset: 0xC.
Definition: MK60D10.h:5344
Reserved119_IRQn
Reserved interrupt 119.
Definition: MK60D10.h:199
UART_Type::CPW
__IO uint8_t CPW
UART CEA709.1-B Collision Pulse Width, offset: 0x2F.
Definition: MK60D10.h:8272
SIM_Type
SIM - Register Layout Typedef.
Definition: MK60D10.h:7328
__IO
#define __IO
Definition: core_cm0.h:189
UART_Type::PCTH
__IO uint8_t PCTH
UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22.
Definition: MK60D10.h:8259
FTM_Type::CNTIN
__IO uint32_t CNTIN
Counter Initial Value, offset: 0x4C.
Definition: MK60D10.h:4134
CAN_Type::ESR2
__I uint32_t ESR2
Error and Status 2 register, offset: 0x38.
Definition: MK60D10.h:1503
CRC_Type::GPOLYLU
__IO uint8_t GPOLYLU
CRC_GPOLYLU register., offset: 0x5.
Definition: MK60D10.h:2198
GPIO_Type
GPIO - Register Layout Typedef.
Definition: MK60D10.h:4605
AIPS_Type::PACRG
__IO uint32_t PACRG
Peripheral Access Control Register, offset: 0x48.
Definition: MK60D10.h:497
I2S_Type::RCR2
__IO uint32_t RCR2
SAI Receive Configuration 2 Register, offset: 0x88.
Definition: MK60D10.h:4865
CMP_Type::FPR
__IO uint8_t FPR
CMP Filter Period Register, offset: 0x2.
Definition: MK60D10.h:1953
FTM_Type::CONF
__IO uint32_t CONF
Configuration, offset: 0x84.
Definition: MK60D10.h:4148
I2C_Type::F
__IO uint8_t F
I2C Frequency Divider register, offset: 0x1.
Definition: MK60D10.h:4694
CAN_Type::MCR
__IO uint32_t MCR
Module Configuration Register, offset: 0x0.
Definition: MK60D10.h:1489
LPTMR_Type::CMR
__IO uint32_t CMR
Low Power Timer Compare Register, offset: 0x8.
Definition: MK60D10.h:5343
CRC_Type::CRCHL
__IO uint8_t CRCHL
CRC_CRCHL register., offset: 0x2.
Definition: MK60D10.h:2186
ENET_Type::TCCR
__IO uint32_t TCCR
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8.
Definition: MK60D10.h:3226
SDHC_Type::AC12ERR
__I uint32_t AC12ERR
Auto CMD12 Error Status Register, offset: 0x3C.
Definition: MK60D10.h:6904
RCM_Type::RPFC
__IO uint8_t RPFC
Reset Pin Filter Control register, offset: 0x4.
Definition: MK60D10.h:6454
USBDCD_Type::CLOCK
__IO uint32_t CLOCK
Clock register, offset: 0x4.
Definition: MK60D10.h:9037
I2C_Type::SLTL
__IO uint8_t SLTL
I2C SCL Low Timeout Register Low, offset: 0xB.
Definition: MK60D10.h:4704
ENET_Type::RACC
__IO uint32_t RACC
Receive Accelerator Function Configuration, offset: 0x1C4.
Definition: MK60D10.h:3157
EWM_Type
EWM - Register Layout Typedef.
Definition: MK60D10.h:3613
ENET_Type::MSCR
__IO uint32_t MSCR
MII Speed Control Register, offset: 0x44.
Definition: MK60D10.h:3123
Watchdog_IRQn
WDOG Interrupt.
Definition: MK60D10.h:118
FMC_Type::PFB0CR
__IO uint32_t PFB0CR
Flash Bank 0 Control Register, offset: 0x4.
Definition: MK60D10.h:3796
FTFL_Type::FCCOB3
__IO uint8_t FCCOB3
Flash Common Command Object Registers, offset: 0x4.
Definition: MK60D10.h:3950
DMA15_IRQn
DMA Channel 15 Transfer Complete.
Definition: MK60D10.h:111
ENET_Type::RMON_R_P_GTE2048
__IO uint32_t RMON_R_P_GTE2048
RMON Rx packets w &gt; 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0.
Definition: MK60D10.h:3205
DMA5_IRQn
DMA Channel 5 Transfer Complete.
Definition: MK60D10.h:101
UART_Type::RPREL
__I uint8_t RPREL
UART CEA709.1-B Received Preamble Length, offset: 0x2E.
Definition: MK60D10.h:8271
UART0_ERR_IRQn
UART0 Error interrupt.
Definition: MK60D10.h:142
I2C_Type::C2
__IO uint8_t C2
I2C Control Register 2, offset: 0x5.
Definition: MK60D10.h:4698
USBDCD_Type::TIMER1
__IO uint32_t TIMER1
TIMER1 register, offset: 0x14.
Definition: MK60D10.h:9041
LPTMR_Type::CSR
__IO uint32_t CSR
Low Power Timer Control Status Register, offset: 0x0.
Definition: MK60D10.h:5341
SIM_Type::UIDML
__I uint32_t UIDML
Unique Identification Register Mid Low, offset: 0x105C.
Definition: MK60D10.h:7353
VREF_Type
VREF - Register Layout Typedef.
Definition: MK60D10.h:9134
ENET_Type::RMON_R_BC_PKT
__IO uint32_t RMON_R_BC_PKT
RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288.
Definition: MK60D10.h:3191
PORT_Type::DFWR
__IO uint32_t DFWR
Digital Filter Width Register, offset: 0xC8.
Definition: MK60D10.h:6341
UART_Type::TL7816
__IO uint8_t TL7816
UART 7816 Transmit Length Register, offset: 0x1F.
Definition: MK60D10.h:8256
DAC_Type::C2
__IO uint8_t C2
DAC Control Register 2, offset: 0x23.
Definition: MK60D10.h:2352
SMC_Type::PMCTRL
__IO uint8_t PMCTRL
Power Mode Control register, offset: 0x1.
Definition: MK60D10.h:7671
UART1_ERR_IRQn
UART1 Error interrupt.
Definition: MK60D10.h:144
SDHC_Type::MMCBOOT
__IO uint32_t MMCBOOT
MMC Boot register, offset: 0xC4.
Definition: MK60D10.h:6913
ENET_Type::ATINC
__IO uint32_t ATINC
Time-Stamping Clock Period Register, offset: 0x414.
Definition: MK60D10.h:3220
CRC_Type::GPOLYHL
__IO uint8_t GPOLYHL
CRC_GPOLYHL register., offset: 0x6.
Definition: MK60D10.h:2199
UART_Type::IE7816
__IO uint8_t IE7816
UART 7816 Interrupt Enable Register, offset: 0x19.
Definition: MK60D10.h:8247
LLWU_Type::F2
__IO uint8_t F2
LLWU Flag 2 register, offset: 0x6.
Definition: MK60D10.h:5152
CMP_Type::MUXCR
__IO uint8_t MUXCR
MUX Control Register, offset: 0x5.
Definition: MK60D10.h:1956
UART_Type::S2
__IO uint8_t S2
UART Status Register 2, offset: 0x5.
Definition: MK60D10.h:8227
MCM_Type::PLAMC
__I uint16_t PLAMC
Crossbar Switch (AXBS) Master Configuration, offset: 0xA.
Definition: MK60D10.h:5588
UART5_RX_TX_IRQn
UART5 Receive/Transmit interrupt.
Definition: MK60D10.h:151
__O
#define __O
Definition: core_cm0.h:188
EWM_Type::CMPL
__IO uint8_t CMPL
Compare Low Register, offset: 0x2.
Definition: MK60D10.h:3616
CAU_Type::ADR_CASR
__O uint32_t ADR_CASR
Status register - Add Register command, offset: 0x8C0.
Definition: MK60D10.h:1823
I2S_Type
I2S - Register Layout Typedef.
Definition: MK60D10.h:4849
CAN1_Wake_Up_IRQn
CAN1 wake up interrupt.
Definition: MK60D10.h:138
UART_Type::RWFIFO
__IO uint8_t RWFIFO
UART FIFO Receive Watermark, offset: 0x15.
Definition: MK60D10.h:8243
USB_Type::OTGISTAT
__IO uint8_t OTGISTAT
OTG Interrupt Status register, offset: 0x10.
Definition: MK60D10.h:8711
ADC_Type
ADC - Register Layout Typedef.
Definition: MK60D10.h:266
DMA_Type::DCHPRI11
__IO uint8_t DCHPRI11
Channel n Priority Register, offset: 0x108.
Definition: MK60D10.h:2477
WDOG_Type::WINH
__IO uint16_t WINH
Watchdog Window Register High, offset: 0x8.
Definition: MK60D10.h:9200
SIM_Type::SDID
__I uint32_t SDID
System Device Identification Register, offset: 0x1024.
Definition: MK60D10.h:7339
DMA_Type::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E...
Definition: MK60D10.h:2506
CRC_Type::CTRL
__IO uint32_t CTRL
CRC Control register, offset: 0x8.
Definition: MK60D10.h:2204
UART2_ERR_IRQn
UART2 Error interrupt.
Definition: MK60D10.h:146
USB_Type::SOFTHLD
__IO uint8_t SOFTHLD
SOF Threshold Register, offset: 0xAC.
Definition: MK60D10.h:8741
CAN_Type::ESR1
__IO uint32_t ESR1
Error and Status 1 register, offset: 0x20.
Definition: MK60D10.h:1497
UART2_RX_TX_IRQn
UART2 Receive/Transmit interrupt.
Definition: MK60D10.h:145
SDHC_Type::IRQSTAT
__IO uint32_t IRQSTAT
Interrupt Status register, offset: 0x30.
Definition: MK60D10.h:6901
CAN_Type::RXFGMASK
__IO uint32_t RXFGMASK
Rx FIFO Global Mask register, offset: 0x48.
Definition: MK60D10.h:1506
PIT_Type
PIT - Register Layout Typedef.
Definition: MK60D10.h:6185
DMA_Type::DCHPRI6
__IO uint8_t DCHPRI6
Channel n Priority Register, offset: 0x105.
Definition: MK60D10.h:2474
CAN0_Bus_Off_IRQn
CAN0 bus off interrupt.
Definition: MK60D10.h:126
FTM_Type::FLTCTRL
__IO uint32_t FLTCTRL
Fault Control, offset: 0x7C.
Definition: MK60D10.h:4146
MCG_Type::ATCVH
__IO uint8_t ATCVH
MCG Auto Trim Compare Value High Register, offset: 0xA.
Definition: MK60D10.h:5429
USB_Type::USBFRMADJUST
__IO uint8_t USBFRMADJUST
Frame Adjust Register, offset: 0x114.
Definition: MK60D10.h:8759
ENET_Type::EIR
__IO uint32_t EIR
Interrupt Event Register, offset: 0x4.
Definition: MK60D10.h:3114
SPI_Type::RXFR1
__I uint32_t RXFR1
DSPI Receive FIFO Registers, offset: 0x80.
Definition: MK60D10.h:7764
ENET_Type::RMON_T_P256TO511
__IO uint32_t RMON_T_P256TO511
RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234.
Definition: MK60D10.h:3172
ENET_Type::ATOFF
__IO uint32_t ATOFF
Timer Offset Register, offset: 0x408.
Definition: MK60D10.h:3217
USB0_IRQn
USB0 interrupt.
Definition: MK60D10.h:169
CRC_Type::CTRLHU
__IO uint8_t CTRLHU
CRC_CTRLHU register., offset: 0xB.
Definition: MK60D10.h:2207
IRQn_Type
IRQn_Type
Definition: ADuCRF101.h:69
USBDCD_Type::TIMER0
__IO uint32_t TIMER0
TIMER0 register, offset: 0x10.
Definition: MK60D10.h:9040
DMA_Type::SERQ
__O uint8_t SERQ
Set Enable Request Register, offset: 0x1B.
Definition: MK60D10.h:2457
NV_Type::FPROT3
__I uint8_t FPROT3
Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8.
Definition: MK60D10.h:5867
ENET_Type::IEEE_T_FDXFC
__IO uint32_t IEEE_T_FDXFC
Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270.
Definition: MK60D10.h:3187
DMA_Type::CERQ
__O uint8_t CERQ
Clear Enable Request Register, offset: 0x1A.
Definition: MK60D10.h:2456
AIPS_Type::PACRP
__IO uint32_t PACRP
Peripheral Access Control Register, offset: 0x6C.
Definition: MK60D10.h:506
UART_Type::S1
__I uint8_t S1
UART Status Register 1, offset: 0x4.
Definition: MK60D10.h:8226
DAC_Type::C1
__IO uint8_t C1
DAC Control Register 1, offset: 0x22.
Definition: MK60D10.h:2351
PDB_Type::POEN
__IO uint32_t POEN
Pulse-Out n Enable Register, offset: 0x190.
Definition: MK60D10.h:6061
RTC_Type::TPR
__IO uint32_t TPR
RTC Time Prescaler Register, offset: 0x4.
Definition: MK60D10.h:6732
LLWU_Type::F1
__IO uint8_t F1
LLWU Flag 1 register, offset: 0x5.
Definition: MK60D10.h:5151
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
SDHC_Type::VENDOR
__IO uint32_t VENDOR
Vendor Specific register, offset: 0xC0.
Definition: MK60D10.h:6912
PIT_Type::TFLG
__IO uint32_t TFLG
Timer Flag Register, array offset: 0x10C, array step: 0x10.
Definition: MK60D10.h:6192
DMA2_IRQn
DMA Channel 2 Transfer Complete.
Definition: MK60D10.h:98
FTM_Type::CnSC
__IO uint32_t CnSC
Channel (n) Status And Control, array offset: 0xC, array step: 0x8.
Definition: MK60D10.h:4131
UART1_RX_TX_IRQn
UART1 Receive/Transmit interrupt.
Definition: MK60D10.h:143
ADC_Type::CLP2
__IO uint32_t CLP2
ADC Plus-Side General Calibration Value Register, offset: 0x44.
Definition: MK60D10.h:282
Reserved116_IRQn
Reserved interrupt 116.
Definition: MK60D10.h:196
RNG_Type::CR
__IO uint32_t CR
RNGA Control Register, offset: 0x0.
Definition: MK60D10.h:6650
SIM_Type::SOPT4
__IO uint32_t SOPT4
System Options Register 4, offset: 0x100C.
Definition: MK60D10.h:7334
PORTB_IRQn
Port B interrupt.
Definition: MK60D10.h:184
SMC_Type::PMPROT
__IO uint8_t PMPROT
Power Mode Protection register, offset: 0x0.
Definition: MK60D10.h:7670
FTM_Type::INVCTRL
__IO uint32_t INVCTRL
FTM Inverting Control, offset: 0x90.
Definition: MK60D10.h:4151
FTM_Type::SC
__IO uint32_t SC
Status And Control, offset: 0x0.
Definition: MK60D10.h:4127
PORT_Type::DFER
__IO uint32_t DFER
Digital Filter Enable Register, offset: 0xC0.
Definition: MK60D10.h:6339
USB_Type::ERRSTAT
__IO uint8_t ERRSTAT
Error Interrupt Status register, offset: 0x88.
Definition: MK60D10.h:8723
USB_Type::ENDPT
__IO uint8_t ENDPT
Endpoint Control register, array offset: 0xC0, array step: 0x4.
Definition: MK60D10.h:8748
CRC_Type::CRCHU
__IO uint8_t CRCHU
CRC_CRCHU register., offset: 0x3.
Definition: MK60D10.h:2187
CAN1_Bus_Off_IRQn
CAN1 bus off interrupt.
Definition: MK60D10.h:134
CAN_Type::RXMGMASK
__IO uint32_t RXMGMASK
Rx Mailboxes Global Mask Register, offset: 0x10.
Definition: MK60D10.h:1493
ENET_Type::RMON_T_MC_PKT
__IO uint32_t RMON_T_MC_PKT
RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C.
Definition: MK60D10.h:3162
CAN0_ORed_Message_buffer_IRQn
CAN0 OR&#39;d message buffers interrupt.
Definition: MK60D10.h:125
SDHC_Type::PROCTL
__IO uint32_t PROCTL
Protocol Control register, offset: 0x28.
Definition: MK60D10.h:6899
SDHC_Type::DATPORT
__IO uint32_t DATPORT
Buffer Data Port register, offset: 0x20.
Definition: MK60D10.h:6897
SIM_Type::SCGC2
__IO uint32_t SCGC2
System Clock Gating Control Register 2, offset: 0x102C.
Definition: MK60D10.h:7341
GPIO_Type::PDIR
__I uint32_t PDIR
Port Data Input Register, offset: 0x10.
Definition: MK60D10.h:4610
FTFL_Type::FCCOB6
__IO uint8_t FCCOB6
Flash Common Command Object Registers, offset: 0x9.
Definition: MK60D10.h:3955
USB_Type::BDTPAGE1
__IO uint8_t BDTPAGE1
BDT Page Register 1, offset: 0x9C.
Definition: MK60D10.h:8733
DMA_Type::SLAST
__IO uint32_t SLAST
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20.
Definition: MK60D10.h:2495
SDHC_Type::FEVT
__O uint32_t FEVT
Force Event register, offset: 0x50.
Definition: MK60D10.h:6908
ENET_Type::MMFR
__IO uint32_t MMFR
MII Management Frame Register, offset: 0x40.
Definition: MK60D10.h:3122
I2C_Type::A2
__IO uint8_t A2
I2C Address Register 2, offset: 0x9.
Definition: MK60D10.h:4702
MPU_Type::CESR
__IO uint32_t CESR
Control/Error Status Register, offset: 0x0.
Definition: MK60D10.h:5687
UART_Type::C6
__IO uint8_t C6
UART CEA709.1-B Control Register 6, offset: 0x21.
Definition: MK60D10.h:8258
USB_Type::REV
__I uint8_t REV
Peripheral Revision register, offset: 0x8.
Definition: MK60D10.h:8707
USB_Type::OTGICR
__IO uint8_t OTGICR
OTG Interrupt Control Register, offset: 0x14.
Definition: MK60D10.h:8713
MCG_Type::SC
__IO uint8_t SC
MCG Status and Control Register, offset: 0x8.
Definition: MK60D10.h:5427
TSI_Type::THRESHOLD
__IO uint32_t THRESHOLD
Low-Power Channel Threshold register, offset: 0x120.
Definition: MK60D10.h:8025
SIM_Type::UIDL
__I uint32_t UIDL
Unique Identification Register Low, offset: 0x1060.
Definition: MK60D10.h:7354
MCG_Type::C8
__IO uint8_t C8
MCG Control 8 Register, offset: 0xD.
Definition: MK60D10.h:5432
CAU_Type::AESIC_CASR
__O uint32_t AESIC_CASR
Status register - AES Inverse Column Operation command, offset: 0xB40.
Definition: MK60D10.h:1843
I2S_Type::RMR
__IO uint32_t RMR
SAI Receive Mask Register, offset: 0xE0.
Definition: MK60D10.h:4874
DMA_Type
DMA - Register Layout Typedef.
Definition: MK60D10.h:2447
UART0_LON_IRQn
UART0 LON interrupt.
Definition: MK60D10.h:140
DMA_Type::DCHPRI2
__IO uint8_t DCHPRI2
Channel n Priority Register, offset: 0x101.
Definition: MK60D10.h:2470
SDHC_Type::HTCAPBLT
__I uint32_t HTCAPBLT
Host Controller Capabilities, offset: 0x40.
Definition: MK60D10.h:6905
Reserved112_IRQn
Reserved interrupt 112.
Definition: MK60D10.h:192
RTC_Type::LR
__IO uint32_t LR
RTC Lock Register, offset: 0x18.
Definition: MK60D10.h:6737
DMA14_IRQn
DMA Channel 14 Transfer Complete.
Definition: MK60D10.h:110
RTC_Type::SR
__IO uint32_t SR
RTC Status Register, offset: 0x14.
Definition: MK60D10.h:6736
DMA_Type::SADDR
__IO uint32_t SADDR
TCD Source Address, array offset: 0x1000, array step: 0x20.
Definition: MK60D10.h:2487
CAN_Type::CRCR
__I uint32_t CRCR
CRC Register, offset: 0x44.
Definition: MK60D10.h:1505
CRC_Type::CRCL
__IO uint16_t CRCL
CRC_CRCL register., offset: 0x0.
Definition: MK60D10.h:2179
ENET_Type::RMON_T_COL
__IO uint32_t RMON_T_COL
RMON Tx collision count (RMON_T_COL), offset: 0x224.
Definition: MK60D10.h:3168
ENET_Type::ATCR
__IO uint32_t ATCR
Timer Control Register, offset: 0x400.
Definition: MK60D10.h:3215
TSI0_IRQn
TSI0 Interrupt.
Definition: MK60D10.h:179
SIM_Type::SOPT5
__IO uint32_t SOPT5
System Options Register 5, offset: 0x1010.
Definition: MK60D10.h:7335
ENET_Type::TIPG
__IO uint32_t TIPG
Transmit Inter-Packet Gap, offset: 0x1AC.
Definition: MK60D10.h:3153
MCM_Type::PID
__IO uint32_t PID
Process ID register, offset: 0x30.
Definition: MK60D10.h:5595
FMC_Type::PFB1CR
__IO uint32_t PFB1CR
Flash Bank 1 Control Register, offset: 0x8.
Definition: MK60D10.h:3797
SPI_Type::RSER
__IO uint32_t RSER
DMA/Interrupt Request Select and Enable Register, offset: 0x30.
Definition: MK60D10.h:7752
USB_Type::OTGSTAT
__IO uint8_t OTGSTAT
OTG Status register, offset: 0x18.
Definition: MK60D10.h:8715
ADC_Type::CLP1
__IO uint32_t CLP1
ADC Plus-Side General Calibration Value Register, offset: 0x48.
Definition: MK60D10.h:283
FTM_Type::SWOCTRL
__IO uint32_t SWOCTRL
FTM Software Output Control, offset: 0x94.
Definition: MK60D10.h:4152
NV_Type::FPROT1
__I uint8_t FPROT1
Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA.
Definition: MK60D10.h:5869
ADC_Type::PGA
__IO uint32_t PGA
ADC PGA Register, offset: 0x50.
Definition: MK60D10.h:285
VREF_Type::TRM
__IO uint8_t TRM
VREF Trim Register, offset: 0x0.
Definition: MK60D10.h:9135
UART_Type::S3
__IO uint8_t S3
UART CEA709.1-B Status Register, offset: 0x2B.
Definition: MK60D10.h:8268
PMC_Type::LVDSC2
__IO uint8_t LVDSC2
Low Voltage Detect Status And Control 2 register, offset: 0x1.
Definition: MK60D10.h:6259
USB_Type::BDTPAGE2
__IO uint8_t BDTPAGE2
BDT Page Register 2, offset: 0xB0.
Definition: MK60D10.h:8743
RTC_Type::CR
__IO uint32_t CR
RTC Control Register, offset: 0x10.
Definition: MK60D10.h:6735
WDOG_Type::TOVALL
__IO uint16_t TOVALL
Watchdog Time-out Value Register Low, offset: 0x6.
Definition: MK60D10.h:9199
ENET_Error_IRQn
Ethernet MAC Error and miscelaneous Interrupt.
Definition: MK60D10.h:174
FTM1_IRQn
FTM1 fault, overflow and channels interrupt.
Definition: MK60D10.h:159
AIPS_Type::PACRK
__IO uint32_t PACRK
Peripheral Access Control Register, offset: 0x58.
Definition: MK60D10.h:501
ENET_Type::RMON_T_OCTETS
__IO uint32_t RMON_T_OCTETS
RMON Tx Octets (RMON_T_OCTETS), offset: 0x244.
Definition: MK60D10.h:3176
DMA6_IRQn
DMA Channel 6 Transfer Complete.
Definition: MK60D10.h:102
I2S_Type::TCR3
__IO uint32_t TCR3
SAI Transmit Configuration 3 Register, offset: 0xC.
Definition: MK60D10.h:4853
DMA_Type::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20.
Definition: MK60D10.h:2491
ENET_Type::IEEE_T_FRAME_OK
__IO uint32_t IEEE_T_FRAME_OK
Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C.
Definition: MK60D10.h:3178
__I
#define __I
Definition: core_cm0.h:186
ENET_Type::RAEM
__IO uint32_t RAEM
Receive FIFO Almost Empty Threshold, offset: 0x198.
Definition: MK60D10.h:3148
ENET_Type::RDAR
__IO uint32_t RDAR
Receive Descriptor Active Register, offset: 0x10.
Definition: MK60D10.h:3117
UART_Type::RPL
__I uint8_t RPL
UART CEA709.1-B Received Packet Length, offset: 0x2D.
Definition: MK60D10.h:8270
ENET_Type::IEEE_T_CSERR
__IO uint32_t IEEE_T_CSERR
Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268.
Definition: MK60D10.h:3185
DMA_Type::DOFF
__IO uint16_t DOFF
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20.
Definition: MK60D10.h:2497
I2S_Type::TMR
__IO uint32_t TMR
SAI Transmit Mask Register, offset: 0x60.
Definition: MK60D10.h:4861
PIT_Type::CVAL
__I uint32_t CVAL
Current Timer Value Register, array offset: 0x104, array step: 0x10.
Definition: MK60D10.h:6190
LLWU_Type::PE3
__IO uint8_t PE3
LLWU Pin Enable 3 register, offset: 0x2.
Definition: MK60D10.h:5148
DMA_Type::DCHPRI8
__IO uint8_t DCHPRI8
Channel n Priority Register, offset: 0x10B.
Definition: MK60D10.h:2480
ENET_Type::RMON_R_OCTETS
__IO uint32_t RMON_R_OCTETS
RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4.
Definition: MK60D10.h:3206
SPI_Type::SR
__IO uint32_t SR
DSPI Status Register, offset: 0x2C.
Definition: MK60D10.h:7751
ENET_Type::RMON_T_P64
__IO uint32_t RMON_T_P64
RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228.
Definition: MK60D10.h:3169
DMA_Error_IRQn
DMA Error Interrupt.
Definition: MK60D10.h:112
CMT_Type::CMD3
__IO uint8_t CMD3
CMT Modulator Data Register Space High, offset: 0x8.
Definition: MK60D10.h:2070
AIPS_Type::PACRD
__IO uint32_t PACRD
Peripheral Access Control Register, offset: 0x2C.
Definition: MK60D10.h:493
WDOG_Type
WDOG - Register Layout Typedef.
Definition: MK60D10.h:9195
FTFL_Type::FEPROT
__IO uint8_t FEPROT
EEPROM Protection Register, offset: 0x16.
Definition: MK60D10.h:3967
ENET_Type::RMON_R_P128TO255
__IO uint32_t RMON_R_P128TO255
RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0.
Definition: MK60D10.h:3201
ENET_Type::RMON_T_PACKETS
__IO uint32_t RMON_T_PACKETS
RMON Tx packet count (RMON_T_PACKETS), offset: 0x204.
Definition: MK60D10.h:3160
WDOG_Type::STCTRLL
__IO uint16_t STCTRLL
Watchdog Status and Control Register Low, offset: 0x2.
Definition: MK60D10.h:9197
FMC_Type
FMC - Register Layout Typedef.
Definition: MK60D10.h:3794
MCG_Type::C10
__I uint8_t C10
MCG Control 10 Register, offset: 0xF.
Definition: MK60D10.h:5434
TSI_Type::SCANC
__IO uint32_t SCANC
SCAN Control register, offset: 0x4.
Definition: MK60D10.h:8013
FTFL_Type::FSTAT
__IO uint8_t FSTAT
Flash Status Register, offset: 0x0.
Definition: MK60D10.h:3946
USB_Type::FRMNUML
__IO uint8_t FRMNUML
Frame Number Register Low, offset: 0xA0.
Definition: MK60D10.h:8735
ENET_Type::IEEE_T_SQE
__IO uint32_t IEEE_T_SQE
Frames Transmitted with SQE Error (IEEE_T_SQE).
Definition: MK60D10.h:3186
ENET_Type::RMON_T_BC_PKT
__IO uint32_t RMON_T_BC_PKT
RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208.
Definition: MK60D10.h:3161
FTM0_IRQn
FTM0 fault, overflow and channels interrupt.
Definition: MK60D10.h:158
ENET_Type::IEEE_R_OCTETS_OK
__IO uint32_t IEEE_R_OCTETS_OK
Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK).
Definition: MK60D10.h:3213
IRQn
IRQn
Interrupt Number Definitions.
Definition: MK60D10.h:83
SIM_Type::SCGC5
__IO uint32_t SCGC5
System Clock Gating Control Register 5, offset: 0x1038.
Definition: MK60D10.h:7344
RFSYS_Type
RFSYS - Register Layout Typedef.
Definition: MK60D10.h:6539
USBDCD_Type
USBDCD - Register Layout Typedef.
Definition: MK60D10.h:9035
LPTMR_Type
LPTMR - Register Layout Typedef.
Definition: MK60D10.h:5340
FTFL_Type::FCCOB2
__IO uint8_t FCCOB2
Flash Common Command Object Registers, offset: 0x5.
Definition: MK60D10.h:3951
ADC_Type::CLM3
__IO uint32_t CLM3
ADC Minus-Side General Calibration Value Register, offset: 0x60.
Definition: MK60D10.h:289
USB_Type::USBCTRL
__IO uint8_t USBCTRL
USB Control register, offset: 0x100.
Definition: MK60D10.h:8751
LLWU_Type::PE1
__IO uint8_t PE1
LLWU Pin Enable 1 register, offset: 0x0.
Definition: MK60D10.h:5146
UART_Type::SDTL
__IO uint8_t SDTL
UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26.
Definition: MK60D10.h:8263
I2S_Type::RCR1
__IO uint32_t RCR1
SAI Receive Configuration 1 Register, offset: 0x84.
Definition: MK60D10.h:4864
USBDCD_Type::CONTROL
__IO uint32_t CONTROL
Control register, offset: 0x0.
Definition: MK60D10.h:9036
CAU_Type::XOR_CASR
__O uint32_t XOR_CASR
Status register - Exclusive Or command, offset: 0x980.
Definition: MK60D10.h:1831
PORTD_IRQn
Port D interrupt.
Definition: MK60D10.h:186
CMT_Type::CMD4
__IO uint8_t CMD4
CMT Modulator Data Register Space Low, offset: 0x9.
Definition: MK60D10.h:2071
PIT_Type::LDVAL
__IO uint32_t LDVAL
Timer Load Value Register, array offset: 0x100, array step: 0x10.
Definition: MK60D10.h:6189
SPI_Type::TCR
__IO uint32_t TCR
Transfer Count Register, offset: 0x8.
Definition: MK60D10.h:7745
CRC_Type::GPOLYHU
__IO uint8_t GPOLYHU
CRC_GPOLYHU register., offset: 0x7.
Definition: MK60D10.h:2200
ENET_Type::IEEE_T_EXCOL
__IO uint32_t IEEE_T_EXCOL
Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260.
Definition: MK60D10.h:3183
ENET_Type::MIBC
__IO uint32_t MIBC
MIB Control Register, offset: 0x64.
Definition: MK60D10.h:3125
ENET_Type::ATCOR
__IO uint32_t ATCOR
Timer Correction Register, offset: 0x410.
Definition: MK60D10.h:3219
USBDCD_Type::TIMER2
__IO uint32_t TIMER2
TIMER2 register, offset: 0x18.
Definition: MK60D10.h:9042
Reserved115_IRQn
Reserved interrupt 115.
Definition: MK60D10.h:195
ENET_Type::ATSTMP
__IO uint32_t ATSTMP
Timestamp of Last Transmitted Frame, offset: 0x418.
Definition: MK60D10.h:3221
ADC_Type::CLM1
__IO uint32_t CLM1
ADC Minus-Side General Calibration Value Register, offset: 0x68.
Definition: MK60D10.h:291
AXBS_Type::MGPCR0
__IO uint32_t MGPCR0
Master General Purpose Control Register, offset: 0x800.
Definition: MK60D10.h:1380
Reserved109_IRQn
Reserved interrupt 109.
Definition: MK60D10.h:189
FTM_Type::CNT
__IO uint32_t CNT
Counter, offset: 0x4.
Definition: MK60D10.h:4128
DMA_Type::DCHPRI9
__IO uint8_t DCHPRI9
Channel n Priority Register, offset: 0x10A.
Definition: MK60D10.h:2479
CAU_Type::XOR_CAA
__O uint32_t XOR_CAA
Accumulator register - Exclusive Or command, offset: 0x984.
Definition: MK60D10.h:1832
FB_Type::CSAR
__IO uint32_t CSAR
Chip Select Address Register, array offset: 0x0, array step: 0xC.
Definition: MK60D10.h:3687
AXBS_Type::MGPCR4
__IO uint32_t MGPCR4
Master General Purpose Control Register, offset: 0xC00.
Definition: MK60D10.h:1388
NV_Type::BACKKEY5
__I uint8_t BACKKEY5
Backdoor Comparison Key 5., offset: 0x6.
Definition: MK60D10.h:5865
DAC_Type::SR
__IO uint8_t SR
DAC Status Register, offset: 0x20.
Definition: MK60D10.h:2349
GPIO_Type::PDOR
__IO uint32_t PDOR
Port Data Output Register, offset: 0x0.
Definition: MK60D10.h:4606
CAN_Type::WORD1
__IO uint32_t WORD1
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10.
Definition: MK60D10.h:1513
DMA_Type::DCHPRI10
__IO uint8_t DCHPRI10
Channel n Priority Register, offset: 0x109.
Definition: MK60D10.h:2478
RTC_Type::TAR
__IO uint32_t TAR
RTC Time Alarm Register, offset: 0x8.
Definition: MK60D10.h:6733
ENET_Type::RMON_R_UNDERSIZE
__IO uint32_t RMON_R_UNDERSIZE
RMON Rx Packets &lt; 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294.
Definition: MK60D10.h:3194
CAN_Type::CS
__IO uint32_t CS
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10...
Definition: MK60D10.h:1510
I2S_Type::RCR5
__IO uint32_t RCR5
SAI Receive Configuration 5 Register, offset: 0x94.
Definition: MK60D10.h:4868
CRC_Type::GPOLYH
__IO uint16_t GPOLYH
CRC_GPOLYH register., offset: 0x6.
Definition: MK60D10.h:2193
FTFL_Type::FSEC
__I uint8_t FSEC
Flash Security Register, offset: 0x2.
Definition: MK60D10.h:3948
FTM_Type::CnV
__IO uint32_t CnV
Channel (n) Value, array offset: 0x10, array step: 0x8.
Definition: MK60D10.h:4132
FTM_Type::MODE
__IO uint32_t MODE
Features Mode Selection, offset: 0x54.
Definition: MK60D10.h:4136
ENET_Type::IEEE_T_LCOL
__IO uint32_t IEEE_T_LCOL
Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C.
Definition: MK60D10.h:3182
CAN_Type::IFLAG1
__IO uint32_t IFLAG1
Interrupt Flags 1 register, offset: 0x30.
Definition: MK60D10.h:1501
UART4_ERR_IRQn
UART4 Error interrupt.
Definition: MK60D10.h:150
DMA_Type::ERR
__IO uint32_t ERR
Error Register, offset: 0x2C.
Definition: MK60D10.h:2465
ENET_Type::GALR
__IO uint32_t GALR
Descriptor Group Lower Address Register, offset: 0x124.
Definition: MK60D10.h:3138
UART4_RX_TX_IRQn
UART4 Receive/Transmit interrupt.
Definition: MK60D10.h:149
CAU_Type::AESC_CASR
__O uint32_t AESC_CASR
Status register - AES Column Operation command, offset: 0xB00.
Definition: MK60D10.h:1839
UART5_ERR_IRQn
UART5 Error interrupt.
Definition: MK60D10.h:152
PORT_Type
PORT - Register Layout Typedef.
Definition: MK60D10.h:6332
CAN1_Error_IRQn
CAN1 error interrupt.
Definition: MK60D10.h:135
ENET_Type::TDSR
__IO uint32_t TDSR
Transmit Buffer Descriptor Ring Start Register, offset: 0x184.
Definition: MK60D10.h:3143
USB_Type::INTEN
__IO uint8_t INTEN
Interrupt Enable register, offset: 0x84.
Definition: MK60D10.h:8721
ENET_Type::RMON_R_MC_PKT
__IO uint32_t RMON_R_MC_PKT
RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C.
Definition: MK60D10.h:3192
CAN_Type
CAN - Register Layout Typedef.
Definition: MK60D10.h:1488
UART_Type::RIDT
__IO uint8_t RIDT
UART CEA709.1-B Receive Indeterminate Time, offset: 0x30.
Definition: MK60D10.h:8273
LPTMR_Type::PSR
__IO uint32_t PSR
Low Power Timer Prescale Register, offset: 0x4.
Definition: MK60D10.h:5342
UART_Type::C5
__IO uint8_t C5
UART Control Register 5, offset: 0xB.
Definition: MK60D10.h:8233
SPI_Type::RXFR2
__I uint32_t RXFR2
DSPI Receive FIFO Registers, offset: 0x84.
Definition: MK60D10.h:7765
ADC1_IRQn
ADC1 interrupt.
Definition: MK60D10.h:154
RTC_Type::WAR
__IO uint32_t WAR
RTC Write Access Register, offset: 0x800.
Definition: MK60D10.h:6740
USB_Type::PERID
__I uint8_t PERID
Peripheral ID register, offset: 0x0.
Definition: MK60D10.h:8703
SIM_Type::SCGC4
__IO uint32_t SCGC4
System Clock Gating Control Register 4, offset: 0x1034.
Definition: MK60D10.h:7343
ENET_Type::RMON_T_P1024TO2047
__IO uint32_t RMON_T_P1024TO2047
RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C.
Definition: MK60D10.h:3174
ENET_Type::RAFL
__IO uint32_t RAFL
Receive FIFO Almost Full Threshold, offset: 0x19C.
Definition: MK60D10.h:3149
UART_Type::ET7816
__IO uint8_t ET7816
UART 7816 Error Threshold Register, offset: 0x1E.
Definition: MK60D10.h:8255
ENET_Transmit_IRQn
Ethernet MAC Transmit Interrupt.
Definition: MK60D10.h:172
AIPS_Type::PACRF
__IO uint32_t PACRF
Peripheral Access Control Register, offset: 0x44.
Definition: MK60D10.h:496
PORT_Type::DFCR
__IO uint32_t DFCR
Digital Filter Clock Register, offset: 0xC4.
Definition: MK60D10.h:6340
EWM_Type::CMPH
__IO uint8_t CMPH
Compare High Register, offset: 0x3.
Definition: MK60D10.h:3617
FTM_Type
FTM - Register Layout Typedef.
Definition: MK60D10.h:4126
WDOG_Type::RSTCNT
__IO uint16_t RSTCNT
Watchdog Reset Count register, offset: 0x14.
Definition: MK60D10.h:9206
FTFL_Type::FCCOB5
__IO uint8_t FCCOB5
Flash Common Command Object Registers, offset: 0xA.
Definition: MK60D10.h:3956
ENET_Type::IEEE_T_DROP
__IO uint32_t IEEE_T_DROP
Count of frames not counted correctly (IEEE_T_DROP).
Definition: MK60D10.h:3177
USB_Type::ERREN
__IO uint8_t ERREN
Error Interrupt Enable register, offset: 0x8C.
Definition: MK60D10.h:8725
USBDCD_IRQn
USBDCD Interrupt.
Definition: MK60D10.h:170
USB_Type::IDCOMP
__I uint8_t IDCOMP
Peripheral ID Complement register, offset: 0x4.
Definition: MK60D10.h:8705
SDHC_IRQn
SDHC Interrupt.
Definition: MK60D10.h:176
ADC_Type::CLMS
__IO uint32_t CLMS
ADC Minus-Side General Calibration Value Register, offset: 0x58.
Definition: MK60D10.h:287
DMA_Type::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008...
Definition: MK60D10.h:2492
USB_Type::ISTAT
__IO uint8_t ISTAT
Interrupt Status register, offset: 0x80.
Definition: MK60D10.h:8719
AIPS_Type::PACRJ
__IO uint32_t PACRJ
Peripheral Access Control Register, offset: 0x54.
Definition: MK60D10.h:500
TSI_Type::CNTR13
__I uint32_t CNTR13
Counter Register, offset: 0x118.
Definition: MK60D10.h:8023
NV_Type::BACKKEY2
__I uint8_t BACKKEY2
Backdoor Comparison Key 2., offset: 0x1.
Definition: MK60D10.h:5860
I2S_Type::MDR
__IO uint32_t MDR
SAI MCLK Divide Register, offset: 0x104.
Definition: MK60D10.h:4877
ENET_Type::RMON_R_PACKETS
__IO uint32_t RMON_R_PACKETS
RMON Rx packet count (RMON_R_PACKETS), offset: 0x284.
Definition: MK60D10.h:3190
SDHC_Type::IRQSTATEN
__IO uint32_t IRQSTATEN
Interrupt Status Enable register, offset: 0x34.
Definition: MK60D10.h:6902
ENET_Type::ATVR
__IO uint32_t ATVR
Timer Value Register, offset: 0x404.
Definition: MK60D10.h:3216
CAU_Type::STR_CASR
__I uint32_t STR_CASR
Status register - Store Register command, offset: 0x880.
Definition: MK60D10.h:1819
CAU_Type::RADR_CASR
__O uint32_t RADR_CASR
Status register - Reverse and Add to Register command, offset: 0x900.
Definition: MK60D10.h:1827
UART_Type::D
__IO uint8_t D
UART Data Register, offset: 0x7.
Definition: MK60D10.h:8229
DMA_Type::DCHPRI1
__IO uint8_t DCHPRI1
Channel n Priority Register, offset: 0x102.
Definition: MK60D10.h:2471
SIM_Type::SOPT7
__IO uint32_t SOPT7
System Options Register 7, offset: 0x1018.
Definition: MK60D10.h:7337
FTFL_Type::FCCOBA
__IO uint8_t FCCOBA
Flash Common Command Object Registers, offset: 0xD.
Definition: MK60D10.h:3959
CAU_Type::ROTL_CAA
__O uint32_t ROTL_CAA
Accumulator register - Rotate Left command, offset: 0x9C4.
Definition: MK60D10.h:1836
ENET_Type::RMON_R_P256TO511
__IO uint32_t RMON_R_P256TO511
RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4.
Definition: MK60D10.h:3202
I2S_Type::TCSR
__IO uint32_t TCSR
SAI Transmit Control Register, offset: 0x0.
Definition: MK60D10.h:4850
PORT_Type::ISFR
__IO uint32_t ISFR
Interrupt Status Flag Register, offset: 0xA0.
Definition: MK60D10.h:6337
PORTE_IRQn
Port E interrupt.
Definition: MK60D10.h:187
MCM_Type::ETBCC
__IO uint32_t ETBCC
ETB Counter Control register, offset: 0x14.
Definition: MK60D10.h:5591
USB_Type::OBSERVE
__I uint8_t OBSERVE
USB OTG Observe register, offset: 0x104.
Definition: MK60D10.h:8753
SPI_Type::RXFR3
__I uint32_t RXFR3
DSPI Receive FIFO Registers, offset: 0x88.
Definition: MK60D10.h:7766
LLW_IRQn
Low Leakage Wakeup.
Definition: MK60D10.h:117
USB_Type::OTGCTL
__IO uint8_t OTGCTL
OTG Control register, offset: 0x1C.
Definition: MK60D10.h:8717
PORT_Type::GPCHR
__O uint32_t GPCHR
Global Pin Control High Register, offset: 0x84.
Definition: MK60D10.h:6335
LLWU_Type::FILT1
__IO uint8_t FILT1
LLWU Pin Filter 1 register, offset: 0x8.
Definition: MK60D10.h:5154
ENET_Type::TDAR
__IO uint32_t TDAR
Transmit Descriptor Active Register, offset: 0x14.
Definition: MK60D10.h:3118
FTM_Type::STATUS
__I uint32_t STATUS
Capture And Compare Status, offset: 0x50.
Definition: MK60D10.h:4135
NV_Type::BACKKEY7
__I uint8_t BACKKEY7
Backdoor Comparison Key 7., offset: 0x4.
Definition: MK60D10.h:5863
RTC_Type::TCR
__IO uint32_t TCR
RTC Time Compensation Register, offset: 0xC.
Definition: MK60D10.h:6734
MCG_Type::C7
__IO uint8_t C7
MCG Control 7 Register, offset: 0xC.
Definition: MK60D10.h:5431
ENET_Type::IEEE_R_CRC
__IO uint32_t IEEE_R_CRC
Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0.
Definition: MK60D10.h:3209
TSI_Type::CNTR11
__I uint32_t CNTR11
Counter Register, offset: 0x114.
Definition: MK60D10.h:8022
ADC_Type::CLM2
__IO uint32_t CLM2
ADC Minus-Side General Calibration Value Register, offset: 0x64.
Definition: MK60D10.h:290
DMA_Type::CINT
__O uint8_t CINT
Clear Interrupt Request Register, offset: 0x1F.
Definition: MK60D10.h:2461
PMC_Type::REGSC
__IO uint8_t REGSC
Regulator Status And Control register, offset: 0x2.
Definition: MK60D10.h:6260
CAN_Type::RX15MASK
__IO uint32_t RX15MASK
Rx 15 Mask register, offset: 0x18.
Definition: MK60D10.h:1495
UART_Type::C2
__IO uint8_t C2
UART Control Register 2, offset: 0x3.
Definition: MK60D10.h:8225
DMA7_IRQn
DMA Channel 7 Transfer Complete.
Definition: MK60D10.h:103
DMA4_IRQn
DMA Channel 4 Transfer Complete.
Definition: MK60D10.h:100
TSI_Type::CNTR5
__I uint32_t CNTR5
Counter Register, offset: 0x108.
Definition: MK60D10.h:8019
NV_Type::BACKKEY1
__I uint8_t BACKKEY1
Backdoor Comparison Key 1., offset: 0x2.
Definition: MK60D10.h:5861
UART_Type::B1T
__IO uint8_t B1T
UART CEA709.1-B Beta1 Timer, offset: 0x24.
Definition: MK60D10.h:8261
DMA_Type::DCHPRI12
__IO uint8_t DCHPRI12
Channel n Priority Register, offset: 0x10F.
Definition: MK60D10.h:2484
LLWU_Type::ME
__IO uint8_t ME
LLWU Module Enable register, offset: 0x4.
Definition: MK60D10.h:5150
FTFL_Type::FCCOB9
__IO uint8_t FCCOB9
Flash Common Command Object Registers, offset: 0xE.
Definition: MK60D10.h:3960
MCG_Type::C3
__IO uint8_t C3
MCG Control 3 Register, offset: 0x2.
Definition: MK60D10.h:5421
FTFL_Type::FCCOB0
__IO uint8_t FCCOB0
Flash Common Command Object Registers, offset: 0x7.
Definition: MK60D10.h:3953
ENET_Type::RMON_R_OVERSIZE
__IO uint32_t RMON_R_OVERSIZE
RMON Rx Packets &gt; MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298.
Definition: MK60D10.h:3195
DMA_Type::EEI
__IO uint32_t EEI
Enable Error Interrupt Register, offset: 0x14.
Definition: MK60D10.h:2453
I2C_Type::C1
__IO uint8_t C1
I2C Control Register 1, offset: 0x2.
Definition: MK60D10.h:4695
DMA_Type::DCHPRI4
__IO uint8_t DCHPRI4
Channel n Priority Register, offset: 0x107.
Definition: MK60D10.h:2476
PDB_Type
PDB - Register Layout Typedef.
Definition: MK60D10.h:6044
I2C_Type::D
__IO uint8_t D
I2C Data I/O register, offset: 0x4.
Definition: MK60D10.h:4697
I2C_Type
I2C - Register Layout Typedef.
Definition: MK60D10.h:4692
AIPS_Type
AIPS - Register Layout Typedef.
Definition: MK60D10.h:487
FTFL_Type::FPROT3
__IO uint8_t FPROT3
Program Flash Protection Registers, offset: 0x10.
Definition: MK60D10.h:3962
NV_Type::BACKKEY0
__I uint8_t BACKKEY0
Backdoor Comparison Key 0., offset: 0x3.
Definition: MK60D10.h:5862
DMA_Type::DLAST_SGA
__IO uint32_t DLAST_SGA
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20.
Definition: MK60D10.h:2502
LLWU_Type::RST
__IO uint8_t RST
LLWU Reset Enable register, offset: 0xA.
Definition: MK60D10.h:5156
ADC_Type::MG
__IO uint32_t MG
ADC Minus-Side Gain Register, offset: 0x30.
Definition: MK60D10.h:277
SIM_Type::SCGC3
__IO uint32_t SCGC3
System Clock Gating Control Register 3, offset: 0x1030.
Definition: MK60D10.h:7342
FTM_Type::OUTMASK
__IO uint32_t OUTMASK
Output Mask, offset: 0x60.
Definition: MK60D10.h:4139
AIPS_Type::PACRA
__IO uint32_t PACRA
Peripheral Access Control Register, offset: 0x20.
Definition: MK60D10.h:490
NV_Type::FPROT2
__I uint8_t FPROT2
Non-volatile P-Flash Protection 1 - High Register, offset: 0x9.
Definition: MK60D10.h:5868
Reserved59_IRQn
Reserved interrupt 59.
Definition: MK60D10.h:139
AIPS_Type::PACRN
__IO uint32_t PACRN
Peripheral Access Control Register, offset: 0x64.
Definition: MK60D10.h:504
FB_Type::CSPMCR
__IO uint32_t CSPMCR
Chip Select port Multiplexing Control Register, offset: 0x60.
Definition: MK60D10.h:3692
MCM_Type
MCM - Register Layout Typedef.
Definition: MK60D10.h:5585
ENET_Type::RMON_T_CRC_ALIGN
__IO uint32_t RMON_T_CRC_ALIGN
RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210.
Definition: MK60D10.h:3163
PDB_Type::MOD
__IO uint32_t MOD
Modulus Register, offset: 0x4.
Definition: MK60D10.h:6046
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