LLWU - Register Layout Typedef.
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#include <cpu/arm/k60/include/MK60D10.h>
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| __IO uint8_t | PE1 |
| | LLWU Pin Enable 1 register, offset: 0x0. More...
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| __IO uint8_t | PE2 |
| | LLWU Pin Enable 2 register, offset: 0x1. More...
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| __IO uint8_t | PE3 |
| | LLWU Pin Enable 3 register, offset: 0x2. More...
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| __IO uint8_t | PE4 |
| | LLWU Pin Enable 4 register, offset: 0x3. More...
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| __IO uint8_t | ME |
| | LLWU Module Enable register, offset: 0x4. More...
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| __IO uint8_t | F1 |
| | LLWU Flag 1 register, offset: 0x5. More...
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| __IO uint8_t | F2 |
| | LLWU Flag 2 register, offset: 0x6. More...
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__I uint8_t | F3 |
| | LLWU Flag 3 register, offset: 0x7.
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__IO uint8_t | FILT1 |
| | LLWU Pin Filter 1 register, offset: 0x8.
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__IO uint8_t | FILT2 |
| | LLWU Pin Filter 2 register, offset: 0x9.
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__IO uint8_t | RST |
| | LLWU Reset Enable register, offset: 0xA.
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__IO uint8_t | F3 |
| | LLWU Flag 3 Register, offset: 0x7.
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__IO uint8_t | CS |
| | LLWU Control and Status Register, offset: 0x8.
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LLWU - Register Layout Typedef.
Definition at line 5145 of file MK60D10.h.
| __IO uint8_t LLWU_Type::F1 |
LLWU Flag 1 register, offset: 0x5.
LLWU Flag 1 Register, offset: 0x5.
Definition at line 5151 of file MK60D10.h.
| __IO uint8_t LLWU_Type::F2 |
LLWU Flag 2 register, offset: 0x6.
LLWU Flag 2 Register, offset: 0x6.
Definition at line 5152 of file MK60D10.h.
| __IO uint8_t LLWU_Type::ME |
LLWU Module Enable register, offset: 0x4.
LLWU Module Enable Register, offset: 0x4.
Definition at line 5150 of file MK60D10.h.
| __IO uint8_t LLWU_Type::PE1 |
LLWU Pin Enable 1 register, offset: 0x0.
LLWU Pin Enable 1 Register, offset: 0x0.
Definition at line 5146 of file MK60D10.h.
| __IO uint8_t LLWU_Type::PE2 |
LLWU Pin Enable 2 register, offset: 0x1.
LLWU Pin Enable 2 Register, offset: 0x1.
Definition at line 5147 of file MK60D10.h.
| __IO uint8_t LLWU_Type::PE3 |
LLWU Pin Enable 3 register, offset: 0x2.
LLWU Pin Enable 3 Register, offset: 0x2.
Definition at line 5148 of file MK60D10.h.
| __IO uint8_t LLWU_Type::PE4 |
LLWU Pin Enable 4 register, offset: 0x3.
LLWU Pin Enable 4 Register, offset: 0x3.
Definition at line 5149 of file MK60D10.h.
