MCM - Register Layout Typedef.
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#include <cpu/arm/k60/include/MK60D10.h>
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| __I uint16_t | PLASC |
| | Crossbar Switch (AXBS) Slave Configuration, offset: 0x8. More...
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| __I uint16_t | PLAMC |
| | Crossbar Switch (AXBS) Master Configuration, offset: 0xA. More...
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__IO uint32_t | CR |
| | Control Register, offset: 0xC.
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| __IO uint32_t | ISR |
| | Interrupt Status Register, offset: 0x10. More...
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| __IO uint32_t | ETBCC |
| | ETB Counter Control register, offset: 0x14. More...
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| __IO uint32_t | ETBRL |
| | ETB Reload register, offset: 0x18. More...
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| __I uint32_t | ETBCNT |
| | ETB Counter Value register, offset: 0x1C. More...
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__IO uint32_t | PID |
| | Process ID register, offset: 0x30.
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__IO uint32_t | SRAMAP |
| | SRAM arbitration and protection, offset: 0xC.
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MCM - Register Layout Typedef.
Definition at line 5585 of file MK60D10.h.
| __IO uint32_t MCM_Type::ETBCC |
ETB Counter Control register, offset: 0x14.
ETB counter control register, offset: 0x14.
Definition at line 5591 of file MK60D10.h.
| __I uint32_t MCM_Type::ETBCNT |
ETB Counter Value register, offset: 0x1C.
ETB counter value register, offset: 0x1C.
Definition at line 5593 of file MK60D10.h.
| __IO uint32_t MCM_Type::ETBRL |
ETB Reload register, offset: 0x18.
ETB reload register, offset: 0x18.
Definition at line 5592 of file MK60D10.h.
| __IO uint32_t MCM_Type::ISR |
Interrupt Status Register, offset: 0x10.
Interrupt status register, offset: 0x10.
Definition at line 5590 of file MK60D10.h.
| __I uint16_t MCM_Type::PLAMC |
Crossbar Switch (AXBS) Master Configuration, offset: 0xA.
Crossbar switch (AXBS) master configuration, offset: 0xA.
Definition at line 5588 of file MK60D10.h.
| __I uint16_t MCM_Type::PLASC |
Crossbar Switch (AXBS) Slave Configuration, offset: 0x8.
Crossbar switch (AXBS) slave configuration, offset: 0x8.
Definition at line 5587 of file MK60D10.h.
