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PDB - Register Layout Typedef. More...
#include <cpu/arm/k60/include/MK60D10.h>
Data Fields | |
__IO uint32_t | SC |
Status and Control Register, offset: 0x0. | |
__IO uint32_t | MOD |
Modulus Register, offset: 0x4. | |
__I uint32_t | CNT |
Counter Register, offset: 0x8. | |
__IO uint32_t | IDLY |
Interrupt Delay Register, offset: 0xC. | |
__IO uint32_t | POEN |
Pulse-Out n Enable Register, offset: 0x190. | |
__IO uint32_t | PODLY [3] |
Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4. More... | |
__IO uint32_t | C1 |
Channel n Control Register 1, array offset: 0x10, array step: 0x28. | |
__IO uint32_t | S |
Channel n Status Register, array offset: 0x14, array step: 0x28. | |
__IO uint32_t | DLY [2] |
Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4. | |
__IO uint32_t | INTC |
DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8. | |
__IO uint32_t | INT |
DAC Interval n Register, array offset: 0x154, array step: 0x8. | |