SDHC - Register Layout Typedef.
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#include <cpu/arm/k60/include/MK60D10.h>
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| __IO uint32_t | DSADDR |
| | DMA System Address register, offset: 0x0. More...
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| __IO uint32_t | BLKATTR |
| | Block Attributes register, offset: 0x4. More...
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| __IO uint32_t | CMDARG |
| | Command Argument register, offset: 0x8. More...
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| __IO uint32_t | XFERTYP |
| | Transfer Type register, offset: 0xC. More...
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__I uint32_t | CMDRSP [4] |
| | Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4.
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| __IO uint32_t | DATPORT |
| | Buffer Data Port register, offset: 0x20. More...
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| __I uint32_t | PRSSTAT |
| | Present State register, offset: 0x24. More...
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| __IO uint32_t | PROCTL |
| | Protocol Control register, offset: 0x28. More...
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| __IO uint32_t | SYSCTL |
| | System Control register, offset: 0x2C. More...
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| __IO uint32_t | IRQSTAT |
| | Interrupt Status register, offset: 0x30. More...
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| __IO uint32_t | IRQSTATEN |
| | Interrupt Status Enable register, offset: 0x34. More...
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| __IO uint32_t | IRQSIGEN |
| | Interrupt Signal Enable register, offset: 0x38. More...
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__I uint32_t | AC12ERR |
| | Auto CMD12 Error Status Register, offset: 0x3C.
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__I uint32_t | HTCAPBLT |
| | Host Controller Capabilities, offset: 0x40.
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__IO uint32_t | WML |
| | Watermark Level Register, offset: 0x44.
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| __O uint32_t | FEVT |
| | Force Event register, offset: 0x50. More...
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| __I uint32_t | ADMAES |
| | ADMA Error Status register, offset: 0x54. More...
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| __IO uint32_t | ADSADDR |
| | ADMA System Addressregister, offset: 0x58. More...
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| __IO uint32_t | VENDOR |
| | Vendor Specific register, offset: 0xC0. More...
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| __IO uint32_t | MMCBOOT |
| | MMC Boot register, offset: 0xC4. More...
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__I uint32_t | HOSTVER |
| | Host Controller Version, offset: 0xFC.
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SDHC - Register Layout Typedef.
Definition at line 6891 of file MK60D10.h.
| __I uint32_t SDHC_Type::ADMAES |
ADMA Error Status register, offset: 0x54.
ADMA Error Status Register, offset: 0x54.
Definition at line 6909 of file MK60D10.h.
| __IO uint32_t SDHC_Type::ADSADDR |
ADMA System Addressregister, offset: 0x58.
ADMA System Address Register, offset: 0x58.
Definition at line 6910 of file MK60D10.h.
| __IO uint32_t SDHC_Type::BLKATTR |
Block Attributes register, offset: 0x4.
Block Attributes Register, offset: 0x4.
Definition at line 6893 of file MK60D10.h.
| __IO uint32_t SDHC_Type::CMDARG |
Command Argument register, offset: 0x8.
Command Argument Register, offset: 0x8.
Definition at line 6894 of file MK60D10.h.
| __IO uint32_t SDHC_Type::DATPORT |
Buffer Data Port register, offset: 0x20.
Buffer Data Port Register, offset: 0x20.
Definition at line 6897 of file MK60D10.h.
| __IO uint32_t SDHC_Type::DSADDR |
DMA System Address register, offset: 0x0.
DMA System Address Register, offset: 0x0.
Definition at line 6892 of file MK60D10.h.
| __O uint32_t SDHC_Type::FEVT |
Force Event register, offset: 0x50.
Force Event Register, offset: 0x50.
Definition at line 6908 of file MK60D10.h.
| __IO uint32_t SDHC_Type::IRQSIGEN |
Interrupt Signal Enable register, offset: 0x38.
Interrupt Signal Enable Register, offset: 0x38.
Definition at line 6903 of file MK60D10.h.
| __IO uint32_t SDHC_Type::IRQSTAT |
Interrupt Status register, offset: 0x30.
Interrupt Status Register, offset: 0x30.
Definition at line 6901 of file MK60D10.h.
| __IO uint32_t SDHC_Type::IRQSTATEN |
Interrupt Status Enable register, offset: 0x34.
Interrupt Status Enable Register, offset: 0x34.
Definition at line 6902 of file MK60D10.h.
| __IO uint32_t SDHC_Type::MMCBOOT |
MMC Boot register, offset: 0xC4.
MMC Boot Register, offset: 0xC4.
Definition at line 6913 of file MK60D10.h.
| __IO uint32_t SDHC_Type::PROCTL |
Protocol Control register, offset: 0x28.
Protocol Control Register, offset: 0x28.
Definition at line 6899 of file MK60D10.h.
| __I uint32_t SDHC_Type::PRSSTAT |
Present State register, offset: 0x24.
Present State Register, offset: 0x24.
Definition at line 6898 of file MK60D10.h.
| __IO uint32_t SDHC_Type::SYSCTL |
System Control register, offset: 0x2C.
System Control Register, offset: 0x2C.
Definition at line 6900 of file MK60D10.h.
| __IO uint32_t SDHC_Type::VENDOR |
Vendor Specific register, offset: 0xC0.
Vendor Specific Register, offset: 0xC0.
Definition at line 6912 of file MK60D10.h.
| __IO uint32_t SDHC_Type::XFERTYP |
Transfer Type register, offset: 0xC.
Transfer Type Register, offset: 0xC.
Definition at line 6895 of file MK60D10.h.
