SPI - Register Layout Typedef.
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#include <cpu/arm/k60/include/MK60D10.h>
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| __IO uint32_t | MCR |
| | Module Configuration Register, offset: 0x0. More...
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| __IO uint32_t | TCR |
| | Transfer Count Register, offset: 0x8. More...
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__IO uint32_t | SR |
| | DSPI Status Register, offset: 0x2C.
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| __IO uint32_t | RSER |
| | DMA/Interrupt Request Select and Enable Register, offset: 0x30. More...
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| __I uint32_t | POPR |
| | POP RX FIFO Register, offset: 0x38. More...
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__I uint32_t | TXFR0 |
| | DSPI Transmit FIFO Registers, offset: 0x3C.
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__I uint32_t | TXFR1 |
| | DSPI Transmit FIFO Registers, offset: 0x40.
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__I uint32_t | TXFR2 |
| | DSPI Transmit FIFO Registers, offset: 0x44.
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__I uint32_t | TXFR3 |
| | DSPI Transmit FIFO Registers, offset: 0x48.
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__I uint32_t | RXFR0 |
| | DSPI Receive FIFO Registers, offset: 0x7C.
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__I uint32_t | RXFR1 |
| | DSPI Receive FIFO Registers, offset: 0x80.
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__I uint32_t | RXFR2 |
| | DSPI Receive FIFO Registers, offset: 0x84.
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__I uint32_t | RXFR3 |
| | DSPI Receive FIFO Registers, offset: 0x88.
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__IO uint32_t | CTAR [2] |
| | DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4.
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| __IO uint32_t | CTAR_SLAVE [1] |
| | Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4. More...
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| __IO uint32_t | PUSHR |
| | PUSH TX FIFO Register In Master Mode, offset: 0x34. More...
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| __IO uint32_t | PUSHR_SLAVE |
| | PUSH TX FIFO Register In Slave Mode, offset: 0x34. More...
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SPI - Register Layout Typedef.
Definition at line 7742 of file MK60D10.h.
| __IO uint32_t SPI_Type::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.
DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.
Definition at line 7748 of file MK60D10.h.
| __IO uint32_t SPI_Type::MCR |
Module Configuration Register, offset: 0x0.
DSPI Module Configuration Register, offset: 0x0.
Definition at line 7743 of file MK60D10.h.
| __I uint32_t SPI_Type::POPR |
POP RX FIFO Register, offset: 0x38.
DSPI POP RX FIFO Register, offset: 0x38.
Definition at line 7757 of file MK60D10.h.
| __IO uint32_t SPI_Type::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34.
DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34.
Definition at line 7754 of file MK60D10.h.
| __IO uint32_t SPI_Type::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34.
DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34.
Definition at line 7755 of file MK60D10.h.
| __IO uint32_t SPI_Type::RSER |
DMA/Interrupt Request Select and Enable Register, offset: 0x30.
DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30.
Definition at line 7752 of file MK60D10.h.
| __IO uint32_t SPI_Type::TCR |
Transfer Count Register, offset: 0x8.
DSPI Transfer Count Register, offset: 0x8.
Definition at line 7745 of file MK60D10.h.
