TPI_Type Struct Reference

Structure type to access the Trace Port Interface Register (TPI). More...

#include <cpu/arm/common/CMSIS/core_cm3.h>

Data Fields
__IO uint32_t	SSPSR
__IO uint32_t	CSPSR
__IO uint32_t	ACPR
__IO uint32_t	SPPR
__I uint32_t	FFSR
__IO uint32_t	FFCR
__I uint32_t	FSCR
__I uint32_t	TRIGGER
__I uint32_t	FIFO0
__I uint32_t	ITATBCTR2
__I uint32_t	ITATBCTR0
__I uint32_t	FIFO1
__IO uint32_t	ITCTRL
__IO uint32_t	CLAIMSET
__IO uint32_t	CLAIMCLR
__I uint32_t	DEVID
__I uint32_t	DEVTYPE

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Definition at line 897 of file core_cm3.h.

Field Documentation

__IO uint32_t TPI_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 902 of file core_cm3.h.

__IO uint32_t TPI_Type::CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 919 of file core_cm3.h.

__IO uint32_t TPI_Type::CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

Definition at line 918 of file core_cm3.h.

__IO uint32_t TPI_Type::CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 900 of file core_cm3.h.

__I uint32_t TPI_Type::DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 921 of file core_cm3.h.

__I uint32_t TPI_Type::DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Definition at line 922 of file core_cm3.h.

__IO uint32_t TPI_Type::FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 907 of file core_cm3.h.

__I uint32_t TPI_Type::FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 906 of file core_cm3.h.

__I uint32_t TPI_Type::FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 911 of file core_cm3.h.

__I uint32_t TPI_Type::FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 915 of file core_cm3.h.

__I uint32_t TPI_Type::FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 908 of file core_cm3.h.

__I uint32_t TPI_Type::ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 914 of file core_cm3.h.

__I uint32_t TPI_Type::ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 912 of file core_cm3.h.

__IO uint32_t TPI_Type::ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 916 of file core_cm3.h.

__IO uint32_t TPI_Type::SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 904 of file core_cm3.h.

__IO uint32_t TPI_Type::SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 899 of file core_cm3.h.

__I uint32_t TPI_Type::TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

Definition at line 910 of file core_cm3.h.