TSI - Register Layout Typedef.
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#include <cpu/arm/k60/include/MK60D10.h>
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| __IO uint32_t | GENCS |
| | General Control and Status register, offset: 0x0. More...
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| __IO uint32_t | SCANC |
| | SCAN Control register, offset: 0x4. More...
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| __IO uint32_t | PEN |
| | Pin Enable register, offset: 0x8. More...
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__I uint32_t | WUCNTR |
| | Wake-Up Channel Counter Register, offset: 0xC.
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__I uint32_t | CNTR1 |
| | Counter Register, offset: 0x100.
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__I uint32_t | CNTR3 |
| | Counter Register, offset: 0x104.
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__I uint32_t | CNTR5 |
| | Counter Register, offset: 0x108.
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__I uint32_t | CNTR7 |
| | Counter Register, offset: 0x10C.
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__I uint32_t | CNTR9 |
| | Counter Register, offset: 0x110.
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__I uint32_t | CNTR11 |
| | Counter Register, offset: 0x114.
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__I uint32_t | CNTR13 |
| | Counter Register, offset: 0x118.
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__I uint32_t | CNTR15 |
| | Counter Register, offset: 0x11C.
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__IO uint32_t | THRESHOLD |
| | Low-Power Channel Threshold register, offset: 0x120.
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__IO uint32_t | STATUS |
| | Status Register, offset: 0xC.
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__IO uint32_t | THRESHLD [16] |
| | Channel n threshold register, array offset: 0x120, array step: 0x4.
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TSI - Register Layout Typedef.
Definition at line 8011 of file MK60D10.h.
| __IO uint32_t TSI_Type::GENCS |
General Control and Status register, offset: 0x0.
General Control and Status Register, offset: 0x0.
Definition at line 8012 of file MK60D10.h.
| __IO uint32_t TSI_Type::PEN |
Pin Enable register, offset: 0x8.
Pin enable register, offset: 0x8.
Definition at line 8014 of file MK60D10.h.
| __IO uint32_t TSI_Type::SCANC |
SCAN Control register, offset: 0x4.
SCAN control register, offset: 0x4.
Definition at line 8013 of file MK60D10.h.
