Contiki 3.x
adc.c
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1 /*
2  * Copyright (c) 2014, Eistec AB.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the copyright holder nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
21  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27  * POSSIBILITY OF SUCH DAMAGE.
28  *
29  * This file is part of the Mulle platform port of the Contiki operating system.
30  *
31  */
32 
33 /**
34  * \file
35  * ADC interface function implementation for K60 CPU.
36  * \author
37  * Joakim Gebart <joakim.gebart@eistec.se>
38  */
39 
40 #include "adc.h"
41 #include "K60.h"
42 
43 adc_error_t
44 adc_calibrate(adc_number_t adc_num)
45 {
46  uint16_t cal;
47  ADC_Type *ADC_ptr = ADC[adc_num];
48 
49  ADC_ptr->SC3 |= ADC_SC3_CAL_MASK;
50  while(ADC_ptr->SC3 & ADC_SC3_CAL_MASK); /* wait for calibration to finish */
51  while(!(ADC_ptr->SC1[0] & ADC_SC1_COCO_MASK));
52  if(ADC_ptr->SC3 & ADC_SC3_CALF_MASK) {
53  /* calibration failed for some reason, possibly SC2[ADTRG] is 1 ? */
54  return ADC_CAL_FAILED;
55  }
56 
57  /*
58  * Following the steps in the reference manual:
59  */
60  /* 1. Initialize or clear a 16-bit variable in RAM. */
61  /* 2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and
62  * CLPS to the variable. */
63  cal = ADC_ptr->CLP0 + ADC_ptr->CLP1 + ADC_ptr->CLP2 + ADC_ptr->CLP3 +
64  ADC_ptr->CLP4 + ADC_ptr->CLPS;
65  /* 3. Divide the variable by two. */
66  cal /= 2;
67  /* 4. Set the MSB of the variable. */
68  cal |= (1 << 15);
69  /* 5. The previous two steps can be achieved by setting the carry bit,
70  * rotating to the right through the carry bit on the high byte and again on
71  * the low byte.
72  * Don't care about the above optimization, we only do this once on startup
73  * anyway... */
74  /* 6. Store the value in the plus-side gain calibration register PG. */
75  ADC_ptr->PG = cal;
76 
77  /* 7. Repeat the procedure for the minus-side gain calibration value. */
78  cal = ADC_ptr->CLM0 + ADC_ptr->CLM1 + ADC_ptr->CLM2 + ADC_ptr->CLM3 +
79  ADC_ptr->CLM4 + ADC_ptr->CLMS;
80  cal /= 2;
81  cal |= (1 << 15);
82  ADC_ptr->MG = cal;
83 
84  return ADC_SUCCESS;
85 }
86 uint16_t
87 adc_read_raw(adc_number_t adc_num, adc_channel_t adc_channel)
88 {
89  ADC_Type *ADC_ptr = ADC[adc_num];
90 
91  ADC_ptr->SC1[0] = ADC_SC1_ADCH((uint8_t)adc_channel); /* Select the correct channel and initiate a conversion */
92 
93  /* Wait for the conversion to finish */
94  while(!((ADC_ptr->SC1[0]) & ADC_SC1_COCO_MASK));
95 
96  return ADC_ptr->R[0];
97 }
__IO uint32_t CLPS
ADC Plus-Side General Calibration Value Register, offset: 0x38.
Definition: MK60D10.h:279
__IO uint32_t CLP4
ADC Plus-Side General Calibration Value Register, offset: 0x3C.
Definition: MK60D10.h:280
__IO uint32_t CLM0
ADC Minus-Side General Calibration Value Register, offset: 0x6C.
Definition: MK60D10.h:292
__IO uint32_t CLP3
ADC Plus-Side General Calibration Value Register, offset: 0x40.
Definition: MK60D10.h:281
__IO uint32_t SC3
Status and Control Register 3, offset: 0x24.
Definition: MK60D10.h:274
__IO uint32_t CLM4
ADC Minus-Side General Calibration Value Register, offset: 0x5C.
Definition: MK60D10.h:288
__IO uint32_t PG
ADC Plus-Side Gain Register, offset: 0x2C.
Definition: MK60D10.h:276
__IO uint32_t CLP0
ADC Plus-Side General Calibration Value Register, offset: 0x4C.
Definition: MK60D10.h:284
K60 hardware register header wrapper.
ADC - Register Layout Typedef.
Definition: MK60D10.h:266
__IO uint32_t CLP2
ADC Plus-Side General Calibration Value Register, offset: 0x44.
Definition: MK60D10.h:282
__I uint32_t R[2]
ADC Data Result Register, array offset: 0x10, array step: 0x4.
Definition: MK60D10.h:270
__IO uint32_t CLP1
ADC Plus-Side General Calibration Value Register, offset: 0x48.
Definition: MK60D10.h:283
__IO uint32_t SC1[2]
ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.
Definition: MK60D10.h:267
__IO uint32_t CLM3
ADC Minus-Side General Calibration Value Register, offset: 0x60.
Definition: MK60D10.h:289
__IO uint32_t CLM1
ADC Minus-Side General Calibration Value Register, offset: 0x68.
Definition: MK60D10.h:291
__IO uint32_t CLMS
ADC Minus-Side General Calibration Value Register, offset: 0x58.
Definition: MK60D10.h:287
__IO uint32_t CLM2
ADC Minus-Side General Calibration Value Register, offset: 0x64.
Definition: MK60D10.h:290
__IO uint32_t MG
ADC Minus-Side Gain Register, offset: 0x30.
Definition: MK60D10.h:277