44 adc_calibrate(adc_number_t adc_num)
49 ADC_ptr->
SC3 |= ADC_SC3_CAL_MASK;
50 while(ADC_ptr->
SC3 & ADC_SC3_CAL_MASK);
51 while(!(ADC_ptr->
SC1[0] & ADC_SC1_COCO_MASK));
52 if(ADC_ptr->
SC3 & ADC_SC3_CALF_MASK) {
54 return ADC_CAL_FAILED;
87 adc_read_raw(adc_number_t adc_num, adc_channel_t adc_channel)
91 ADC_ptr->
SC1[0] = ADC_SC1_ADCH((uint8_t)adc_channel);
94 while(!((ADC_ptr->
SC1[0]) & ADC_SC1_COCO_MASK));
__IO uint32_t CLPS
ADC Plus-Side General Calibration Value Register, offset: 0x38.
__IO uint32_t CLP4
ADC Plus-Side General Calibration Value Register, offset: 0x3C.
__IO uint32_t CLM0
ADC Minus-Side General Calibration Value Register, offset: 0x6C.
__IO uint32_t CLP3
ADC Plus-Side General Calibration Value Register, offset: 0x40.
__IO uint32_t SC3
Status and Control Register 3, offset: 0x24.
__IO uint32_t CLM4
ADC Minus-Side General Calibration Value Register, offset: 0x5C.
__IO uint32_t PG
ADC Plus-Side Gain Register, offset: 0x2C.
__IO uint32_t CLP0
ADC Plus-Side General Calibration Value Register, offset: 0x4C.
K60 hardware register header wrapper.
ADC - Register Layout Typedef.
__IO uint32_t CLP2
ADC Plus-Side General Calibration Value Register, offset: 0x44.
__I uint32_t R[2]
ADC Data Result Register, array offset: 0x10, array step: 0x4.
__IO uint32_t CLP1
ADC Plus-Side General Calibration Value Register, offset: 0x48.
__IO uint32_t SC1[2]
ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.
__IO uint32_t CLM3
ADC Minus-Side General Calibration Value Register, offset: 0x60.
__IO uint32_t CLM1
ADC Minus-Side General Calibration Value Register, offset: 0x68.
__IO uint32_t CLMS
ADC Minus-Side General Calibration Value Register, offset: 0x58.
__IO uint32_t CLM2
ADC Minus-Side General Calibration Value Register, offset: 0x64.
__IO uint32_t MG
ADC Minus-Side Gain Register, offset: 0x30.