NVIC_Type Struct Reference

Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <cpu/arm/common/CMSIS/core_cm0.h>

Data Fields
__IO uint32_t	ISER [1]
__IO uint32_t	ICER [1]
__IO uint32_t	ISPR [1]
__IO uint32_t	ICPR [1]
__IO uint32_t	IP [8]
__IO uint32_t	IABR [8]
__IO uint8_t	IP [240]
__O uint32_t	STIR

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Definition at line 300 of file core_cm0.h.

Field Documentation

__IO uint32_t NVIC_Type::IABR

Offset: 0x200 (R/W) Interrupt Active bit Register

Definition at line 317 of file core_cm3.h.

__IO uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

Definition at line 304 of file core_cm0.h.

__IO uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

Definition at line 308 of file core_cm0.h.

__IO uint8_t NVIC_Type::IP

Offset: 0x300 (R/W) Interrupt Priority Register

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 311 of file core_cm0.h.

__IO uint8_t NVIC_Type::IP[240]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 319 of file core_cm3.h.

__IO uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

Definition at line 302 of file core_cm0.h.

__IO uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

Definition at line 306 of file core_cm0.h.

__O uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

Definition at line 321 of file core_cm3.h.