Type definitions for the System Control Block Registers. More...

Data Structures
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...

Macros
#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_VTOR_TBLBASE_Pos 29

#define	SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7

#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0

#define	SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

#define	SCB_CFSR_USGFAULTSR_Pos 16

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0

#define	SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0

#define	SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

#define	SCB_CFSR_USGFAULTSR_Pos 16

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0

#define	SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SFCR_UNIBRTIMING_Pos 0

#define	SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SFCR_SECKEY_Pos 16

#define	SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_VTOR_TBLBASE_Pos 29

#define	SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7

#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0

#define	SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)

#define	SCB_CFSR_USGFAULTSR_Pos 16

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0

#define	SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 390 of file core_cm0.h.

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 402 of file core_sc000.h.

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 411 of file core_cm0plus.h.

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 426 of file core_sc300.h.

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 431 of file core_cm3.h.

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 470 of file core_cm4.h.

#define SCB_AIRCR_ENDIANESS_Pos 15

SCB AIRCR: ENDIANESS Position

Definition at line 389 of file core_cm0.h.

#define SCB_AIRCR_ENDIANESS_Pos 15

SCB AIRCR: ENDIANESS Position

Definition at line 401 of file core_sc000.h.

#define SCB_AIRCR_ENDIANESS_Pos 15

SCB AIRCR: ENDIANESS Position

Definition at line 410 of file core_cm0plus.h.

#define SCB_AIRCR_ENDIANESS_Pos 15

SCB AIRCR: ENDIANESS Position

Definition at line 425 of file core_sc300.h.

#define SCB_AIRCR_ENDIANESS_Pos 15

SCB AIRCR: ENDIANESS Position

Definition at line 430 of file core_cm3.h.

#define SCB_AIRCR_ENDIANESS_Pos 15

SCB AIRCR: ENDIANESS Position

Definition at line 469 of file core_cm4.h.

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 429 of file core_sc300.h.

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 434 of file core_cm3.h.

Referenced by NVIC_GetPriorityGrouping(), and NVIC_SetPriorityGrouping().

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 473 of file core_cm4.h.

#define SCB_AIRCR_PRIGROUP_Pos 8

SCB AIRCR: PRIGROUP Position

Definition at line 428 of file core_sc300.h.

#define SCB_AIRCR_PRIGROUP_Pos 8

SCB AIRCR: PRIGROUP Position

Definition at line 433 of file core_cm3.h.

Referenced by NVIC_GetPriorityGrouping().

#define SCB_AIRCR_PRIGROUP_Pos 8

SCB AIRCR: PRIGROUP Position

Definition at line 472 of file core_cm4.h.

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 393 of file core_cm0.h.

Referenced by NVIC_SystemReset().

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 405 of file core_sc000.h.

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 414 of file core_cm0plus.h.

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 432 of file core_sc300.h.

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 437 of file core_cm3.h.

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 476 of file core_cm4.h.

#define SCB_AIRCR_SYSRESETREQ_Pos 2

SCB AIRCR: SYSRESETREQ Position

Definition at line 392 of file core_cm0.h.

#define SCB_AIRCR_SYSRESETREQ_Pos 2

SCB AIRCR: SYSRESETREQ Position

Definition at line 404 of file core_sc000.h.

#define SCB_AIRCR_SYSRESETREQ_Pos 2

SCB AIRCR: SYSRESETREQ Position

Definition at line 413 of file core_cm0plus.h.

#define SCB_AIRCR_SYSRESETREQ_Pos 2

SCB AIRCR: SYSRESETREQ Position

Definition at line 431 of file core_sc300.h.

#define SCB_AIRCR_SYSRESETREQ_Pos 2

SCB AIRCR: SYSRESETREQ Position

Definition at line 436 of file core_cm3.h.

#define SCB_AIRCR_SYSRESETREQ_Pos 2

SCB AIRCR: SYSRESETREQ Position

Definition at line 475 of file core_cm4.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 396 of file core_cm0.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 408 of file core_sc000.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 417 of file core_cm0plus.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 435 of file core_sc300.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 440 of file core_cm3.h.

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 479 of file core_cm4.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 395 of file core_cm0.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 407 of file core_sc000.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 416 of file core_cm0plus.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 434 of file core_sc300.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 439 of file core_cm3.h.

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 478 of file core_cm4.h.

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 384 of file core_cm0.h.

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 396 of file core_sc000.h.

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 405 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 420 of file core_sc300.h.

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 425 of file core_cm3.h.

Referenced by NVIC_SetPriorityGrouping().

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 464 of file core_cm4.h.

#define SCB_AIRCR_VECTKEY_Pos 16

SCB AIRCR: VECTKEY Position

Definition at line 383 of file core_cm0.h.

Referenced by NVIC_SystemReset().

#define SCB_AIRCR_VECTKEY_Pos 16

SCB AIRCR: VECTKEY Position

Definition at line 395 of file core_sc000.h.

#define SCB_AIRCR_VECTKEY_Pos 16

SCB AIRCR: VECTKEY Position

Definition at line 404 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEY_Pos 16

SCB AIRCR: VECTKEY Position

Definition at line 419 of file core_sc300.h.

#define SCB_AIRCR_VECTKEY_Pos 16

SCB AIRCR: VECTKEY Position

Definition at line 424 of file core_cm3.h.

Referenced by NVIC_SetPriorityGrouping().

#define SCB_AIRCR_VECTKEY_Pos 16

SCB AIRCR: VECTKEY Position

Definition at line 463 of file core_cm4.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 387 of file core_cm0.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 399 of file core_sc000.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 408 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 423 of file core_sc300.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 428 of file core_cm3.h.

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 467 of file core_cm4.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos 16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 386 of file core_cm0.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos 16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 398 of file core_sc000.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos 16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 407 of file core_cm0plus.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos 16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 422 of file core_sc300.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos 16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 427 of file core_cm3.h.

#define SCB_AIRCR_VECTKEYSTAT_Pos 16

SCB AIRCR: VECTKEYSTAT Position

Definition at line 466 of file core_cm4.h.

#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 438 of file core_sc300.h.

#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 443 of file core_cm3.h.

#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)

SCB AIRCR: VECTRESET Mask

Definition at line 482 of file core_cm4.h.

#define SCB_AIRCR_VECTRESET_Pos 0

SCB AIRCR: VECTRESET Position

Definition at line 437 of file core_sc300.h.

#define SCB_AIRCR_VECTRESET_Pos 0

SCB AIRCR: VECTRESET Position

Definition at line 442 of file core_cm3.h.

#define SCB_AIRCR_VECTRESET_Pos 0

SCB AIRCR: VECTRESET Position

Definition at line 481 of file core_cm4.h.

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 455 of file core_sc300.h.

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 460 of file core_cm3.h.

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 499 of file core_cm4.h.

#define SCB_CCR_BFHFNMIGN_Pos 8

SCB CCR: BFHFNMIGN Position

Definition at line 454 of file core_sc300.h.

#define SCB_CCR_BFHFNMIGN_Pos 8

SCB CCR: BFHFNMIGN Position

Definition at line 459 of file core_cm3.h.

#define SCB_CCR_BFHFNMIGN_Pos 8

SCB CCR: BFHFNMIGN Position

Definition at line 498 of file core_cm4.h.

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 458 of file core_sc300.h.

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 463 of file core_cm3.h.

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 502 of file core_cm4.h.

#define SCB_CCR_DIV_0_TRP_Pos 4

SCB CCR: DIV_0_TRP Position

Definition at line 457 of file core_sc300.h.

#define SCB_CCR_DIV_0_TRP_Pos 4

SCB CCR: DIV_0_TRP Position

Definition at line 462 of file core_cm3.h.

#define SCB_CCR_DIV_0_TRP_Pos 4

SCB CCR: DIV_0_TRP Position

Definition at line 501 of file core_cm4.h.

#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 467 of file core_sc300.h.

#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 472 of file core_cm3.h.

#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)

SCB CCR: NONBASETHRDENA Mask

Definition at line 511 of file core_cm4.h.

#define SCB_CCR_NONBASETHRDENA_Pos 0

SCB CCR: NONBASETHRDENA Position

Definition at line 466 of file core_sc300.h.

#define SCB_CCR_NONBASETHRDENA_Pos 0

SCB CCR: NONBASETHRDENA Position

Definition at line 471 of file core_cm3.h.

#define SCB_CCR_NONBASETHRDENA_Pos 0

SCB CCR: NONBASETHRDENA Position

Definition at line 510 of file core_cm4.h.

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 410 of file core_cm0.h.

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 422 of file core_sc000.h.

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 431 of file core_cm0plus.h.

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 452 of file core_sc300.h.

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 457 of file core_cm3.h.

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 496 of file core_cm4.h.

#define SCB_CCR_STKALIGN_Pos 9

SCB CCR: STKALIGN Position

Definition at line 409 of file core_cm0.h.

#define SCB_CCR_STKALIGN_Pos 9

SCB CCR: STKALIGN Position

Definition at line 421 of file core_sc000.h.

#define SCB_CCR_STKALIGN_Pos 9

SCB CCR: STKALIGN Position

Definition at line 430 of file core_cm0plus.h.

#define SCB_CCR_STKALIGN_Pos 9

SCB CCR: STKALIGN Position

Definition at line 451 of file core_sc300.h.

#define SCB_CCR_STKALIGN_Pos 9

SCB CCR: STKALIGN Position

Definition at line 456 of file core_cm3.h.

#define SCB_CCR_STKALIGN_Pos 9

SCB CCR: STKALIGN Position

Definition at line 495 of file core_cm4.h.

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 413 of file core_cm0.h.

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 425 of file core_sc000.h.

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 434 of file core_cm0plus.h.

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 461 of file core_sc300.h.

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 466 of file core_cm3.h.

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 505 of file core_cm4.h.

#define SCB_CCR_UNALIGN_TRP_Pos 3

SCB CCR: UNALIGN_TRP Position

Definition at line 412 of file core_cm0.h.

#define SCB_CCR_UNALIGN_TRP_Pos 3

SCB CCR: UNALIGN_TRP Position

Definition at line 424 of file core_sc000.h.

#define SCB_CCR_UNALIGN_TRP_Pos 3

SCB CCR: UNALIGN_TRP Position

Definition at line 433 of file core_cm0plus.h.

#define SCB_CCR_UNALIGN_TRP_Pos 3

SCB CCR: UNALIGN_TRP Position

Definition at line 460 of file core_sc300.h.

#define SCB_CCR_UNALIGN_TRP_Pos 3

SCB CCR: UNALIGN_TRP Position

Definition at line 465 of file core_cm3.h.

#define SCB_CCR_UNALIGN_TRP_Pos 3

SCB CCR: UNALIGN_TRP Position

Definition at line 504 of file core_cm4.h.

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 464 of file core_sc300.h.

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 469 of file core_cm3.h.

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 508 of file core_cm4.h.

#define SCB_CCR_USERSETMPEND_Pos 1

SCB CCR: USERSETMPEND Position

Definition at line 463 of file core_sc300.h.

#define SCB_CCR_USERSETMPEND_Pos 1

SCB CCR: USERSETMPEND Position

Definition at line 468 of file core_cm3.h.

#define SCB_CCR_USERSETMPEND_Pos 1

SCB CCR: USERSETMPEND Position

Definition at line 507 of file core_cm4.h.

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 517 of file core_sc300.h.

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 522 of file core_cm3.h.

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 561 of file core_cm4.h.

#define SCB_CFSR_BUSFAULTSR_Pos 8

SCB CFSR: Bus Fault Status Register Position

Definition at line 516 of file core_sc300.h.

#define SCB_CFSR_BUSFAULTSR_Pos 8

SCB CFSR: Bus Fault Status Register Position

Definition at line 521 of file core_cm3.h.

#define SCB_CFSR_BUSFAULTSR_Pos 8

SCB CFSR: Bus Fault Status Register Position

Definition at line 560 of file core_cm4.h.

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 520 of file core_sc300.h.

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 525 of file core_cm3.h.

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 564 of file core_cm4.h.

#define SCB_CFSR_MEMFAULTSR_Pos 0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 519 of file core_sc300.h.

#define SCB_CFSR_MEMFAULTSR_Pos 0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 524 of file core_cm3.h.

#define SCB_CFSR_MEMFAULTSR_Pos 0

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 563 of file core_cm4.h.

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 514 of file core_sc300.h.

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 519 of file core_cm3.h.

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 558 of file core_cm4.h.

#define SCB_CFSR_USGFAULTSR_Pos 16

SCB CFSR: Usage Fault Status Register Position

Definition at line 513 of file core_sc300.h.

#define SCB_CFSR_USGFAULTSR_Pos 16

SCB CFSR: Usage Fault Status Register Position

Definition at line 518 of file core_cm3.h.

#define SCB_CFSR_USGFAULTSR_Pos 16

SCB CFSR: Usage Fault Status Register Position

Definition at line 557 of file core_cm4.h.

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 346 of file core_cm0.h.

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 354 of file core_sc000.h.

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 361 of file core_cm0plus.h.

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 372 of file core_sc300.h.

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 372 of file core_cm3.h.

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 419 of file core_cm4.h.

#define SCB_CPUID_ARCHITECTURE_Pos 16

SCB CPUID: ARCHITECTURE Position

Definition at line 345 of file core_cm0.h.

#define SCB_CPUID_ARCHITECTURE_Pos 16

SCB CPUID: ARCHITECTURE Position

Definition at line 353 of file core_sc000.h.

#define SCB_CPUID_ARCHITECTURE_Pos 16

SCB CPUID: ARCHITECTURE Position

Definition at line 360 of file core_cm0plus.h.

#define SCB_CPUID_ARCHITECTURE_Pos 16

SCB CPUID: ARCHITECTURE Position

Definition at line 371 of file core_sc300.h.

#define SCB_CPUID_ARCHITECTURE_Pos 16

SCB CPUID: ARCHITECTURE Position

Definition at line 371 of file core_cm3.h.

#define SCB_CPUID_ARCHITECTURE_Pos 16

SCB CPUID: ARCHITECTURE Position

Definition at line 418 of file core_cm4.h.

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 340 of file core_cm0.h.

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 348 of file core_sc000.h.

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 355 of file core_cm0plus.h.

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 366 of file core_sc300.h.

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 366 of file core_cm3.h.

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 413 of file core_cm4.h.

#define SCB_CPUID_IMPLEMENTER_Pos 24

SCB CPUID: IMPLEMENTER Position

Definition at line 339 of file core_cm0.h.

#define SCB_CPUID_IMPLEMENTER_Pos 24

SCB CPUID: IMPLEMENTER Position

Definition at line 347 of file core_sc000.h.

#define SCB_CPUID_IMPLEMENTER_Pos 24

SCB CPUID: IMPLEMENTER Position

Definition at line 354 of file core_cm0plus.h.

#define SCB_CPUID_IMPLEMENTER_Pos 24

SCB CPUID: IMPLEMENTER Position

Definition at line 365 of file core_sc300.h.

#define SCB_CPUID_IMPLEMENTER_Pos 24

SCB CPUID: IMPLEMENTER Position

Definition at line 365 of file core_cm3.h.

#define SCB_CPUID_IMPLEMENTER_Pos 24

SCB CPUID: IMPLEMENTER Position

Definition at line 412 of file core_cm4.h.

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 349 of file core_cm0.h.

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 357 of file core_sc000.h.

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 364 of file core_cm0plus.h.

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 375 of file core_sc300.h.

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 375 of file core_cm3.h.

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 422 of file core_cm4.h.

#define SCB_CPUID_PARTNO_Pos 4

SCB CPUID: PARTNO Position

Definition at line 348 of file core_cm0.h.

#define SCB_CPUID_PARTNO_Pos 4

SCB CPUID: PARTNO Position

Definition at line 356 of file core_sc000.h.

#define SCB_CPUID_PARTNO_Pos 4

SCB CPUID: PARTNO Position

Definition at line 363 of file core_cm0plus.h.

#define SCB_CPUID_PARTNO_Pos 4

SCB CPUID: PARTNO Position

Definition at line 374 of file core_sc300.h.

#define SCB_CPUID_PARTNO_Pos 4

SCB CPUID: PARTNO Position

Definition at line 374 of file core_cm3.h.

#define SCB_CPUID_PARTNO_Pos 4

SCB CPUID: PARTNO Position

Definition at line 421 of file core_cm4.h.

#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 352 of file core_cm0.h.

Referenced by SystemInit().

#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 360 of file core_sc000.h.

#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 367 of file core_cm0plus.h.

#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 378 of file core_sc300.h.

#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 378 of file core_cm3.h.

#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

Definition at line 425 of file core_cm4.h.

#define SCB_CPUID_REVISION_Pos 0

SCB CPUID: REVISION Position

Definition at line 351 of file core_cm0.h.

#define SCB_CPUID_REVISION_Pos 0

SCB CPUID: REVISION Position

Definition at line 359 of file core_sc000.h.

#define SCB_CPUID_REVISION_Pos 0

SCB CPUID: REVISION Position

Definition at line 366 of file core_cm0plus.h.

#define SCB_CPUID_REVISION_Pos 0

SCB CPUID: REVISION Position

Definition at line 377 of file core_sc300.h.

#define SCB_CPUID_REVISION_Pos 0

SCB CPUID: REVISION Position

Definition at line 377 of file core_cm3.h.

#define SCB_CPUID_REVISION_Pos 0

SCB CPUID: REVISION Position

Definition at line 424 of file core_cm4.h.

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 343 of file core_cm0.h.

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 351 of file core_sc000.h.

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 358 of file core_cm0plus.h.

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 369 of file core_sc300.h.

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 369 of file core_cm3.h.

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 416 of file core_cm4.h.

#define SCB_CPUID_VARIANT_Pos 20

SCB CPUID: VARIANT Position

Definition at line 342 of file core_cm0.h.

#define SCB_CPUID_VARIANT_Pos 20

SCB CPUID: VARIANT Position

Definition at line 350 of file core_sc000.h.

#define SCB_CPUID_VARIANT_Pos 20

SCB CPUID: VARIANT Position

Definition at line 357 of file core_cm0plus.h.

#define SCB_CPUID_VARIANT_Pos 20

SCB CPUID: VARIANT Position

Definition at line 368 of file core_cm3.h.

#define SCB_CPUID_VARIANT_Pos 20

SCB CPUID: VARIANT Position

Definition at line 368 of file core_sc300.h.

#define SCB_CPUID_VARIANT_Pos 20

SCB CPUID: VARIANT Position

Definition at line 415 of file core_cm4.h.

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 543 of file core_sc300.h.

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 548 of file core_cm3.h.

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 587 of file core_cm4.h.

#define SCB_DFSR_BKPT_Pos 1

SCB DFSR: BKPT Position

Definition at line 542 of file core_sc300.h.

#define SCB_DFSR_BKPT_Pos 1

SCB DFSR: BKPT Position

Definition at line 547 of file core_cm3.h.

#define SCB_DFSR_BKPT_Pos 1

SCB DFSR: BKPT Position

Definition at line 586 of file core_cm4.h.

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 540 of file core_sc300.h.

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 545 of file core_cm3.h.

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 584 of file core_cm4.h.

#define SCB_DFSR_DWTTRAP_Pos 2

SCB DFSR: DWTTRAP Position

Definition at line 539 of file core_sc300.h.

#define SCB_DFSR_DWTTRAP_Pos 2

SCB DFSR: DWTTRAP Position

Definition at line 544 of file core_cm3.h.

#define SCB_DFSR_DWTTRAP_Pos 2

SCB DFSR: DWTTRAP Position

Definition at line 583 of file core_cm4.h.

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 534 of file core_sc300.h.

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 539 of file core_cm3.h.

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 578 of file core_cm4.h.

#define SCB_DFSR_EXTERNAL_Pos 4

SCB DFSR: EXTERNAL Position

Definition at line 533 of file core_sc300.h.

#define SCB_DFSR_EXTERNAL_Pos 4

SCB DFSR: EXTERNAL Position

Definition at line 538 of file core_cm3.h.

#define SCB_DFSR_EXTERNAL_Pos 4

SCB DFSR: EXTERNAL Position

Definition at line 577 of file core_cm4.h.

#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 546 of file core_sc300.h.

#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 551 of file core_cm3.h.

#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)

SCB DFSR: HALTED Mask

Definition at line 590 of file core_cm4.h.

#define SCB_DFSR_HALTED_Pos 0

SCB DFSR: HALTED Position

Definition at line 545 of file core_sc300.h.

#define SCB_DFSR_HALTED_Pos 0

SCB DFSR: HALTED Position

Definition at line 550 of file core_cm3.h.

#define SCB_DFSR_HALTED_Pos 0

SCB DFSR: HALTED Position

Definition at line 589 of file core_cm4.h.

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 537 of file core_sc300.h.

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 542 of file core_cm3.h.

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 581 of file core_cm4.h.

#define SCB_DFSR_VCATCH_Pos 3

SCB DFSR: VCATCH Position

Definition at line 536 of file core_sc300.h.

#define SCB_DFSR_VCATCH_Pos 3

SCB DFSR: VCATCH Position

Definition at line 541 of file core_cm3.h.

#define SCB_DFSR_VCATCH_Pos 3

SCB DFSR: VCATCH Position

Definition at line 580 of file core_cm4.h.

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 524 of file core_sc300.h.

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 529 of file core_cm3.h.

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 568 of file core_cm4.h.

#define SCB_HFSR_DEBUGEVT_Pos 31

SCB HFSR: DEBUGEVT Position

Definition at line 523 of file core_sc300.h.

#define SCB_HFSR_DEBUGEVT_Pos 31

SCB HFSR: DEBUGEVT Position

Definition at line 528 of file core_cm3.h.

#define SCB_HFSR_DEBUGEVT_Pos 31

SCB HFSR: DEBUGEVT Position

Definition at line 567 of file core_cm4.h.

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 527 of file core_sc300.h.

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 532 of file core_cm3.h.

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 571 of file core_cm4.h.

#define SCB_HFSR_FORCED_Pos 30

SCB HFSR: FORCED Position

Definition at line 526 of file core_sc300.h.

#define SCB_HFSR_FORCED_Pos 30

SCB HFSR: FORCED Position

Definition at line 531 of file core_cm3.h.

#define SCB_HFSR_FORCED_Pos 30

SCB HFSR: FORCED Position

Definition at line 570 of file core_cm4.h.

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 530 of file core_sc300.h.

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 535 of file core_cm3.h.

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 574 of file core_cm4.h.

#define SCB_HFSR_VECTTBL_Pos 1

SCB HFSR: VECTTBL Position

Definition at line 529 of file core_sc300.h.

#define SCB_HFSR_VECTTBL_Pos 1

SCB HFSR: VECTTBL Position

Definition at line 534 of file core_cm3.h.

#define SCB_HFSR_VECTTBL_Pos 1

SCB HFSR: VECTTBL Position

Definition at line 573 of file core_cm4.h.

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 374 of file core_cm0.h.

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 382 of file core_sc000.h.

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 389 of file core_cm0plus.h.

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 400 of file core_cm3.h.

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 400 of file core_sc300.h.

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 447 of file core_cm4.h.

#define SCB_ICSR_ISRPENDING_Pos 22

SCB ICSR: ISRPENDING Position

Definition at line 373 of file core_cm0.h.

#define SCB_ICSR_ISRPENDING_Pos 22

SCB ICSR: ISRPENDING Position

Definition at line 381 of file core_sc000.h.

#define SCB_ICSR_ISRPENDING_Pos 22

SCB ICSR: ISRPENDING Position

Definition at line 388 of file core_cm0plus.h.

#define SCB_ICSR_ISRPENDING_Pos 22

SCB ICSR: ISRPENDING Position

Definition at line 399 of file core_sc300.h.

#define SCB_ICSR_ISRPENDING_Pos 22

SCB ICSR: ISRPENDING Position

Definition at line 399 of file core_cm3.h.

#define SCB_ICSR_ISRPENDING_Pos 22

SCB ICSR: ISRPENDING Position

Definition at line 446 of file core_cm4.h.

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 371 of file core_cm0.h.

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 379 of file core_sc000.h.

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 386 of file core_cm0plus.h.

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 397 of file core_cm3.h.

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 397 of file core_sc300.h.

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 444 of file core_cm4.h.

#define SCB_ICSR_ISRPREEMPT_Pos 23

SCB ICSR: ISRPREEMPT Position

Definition at line 370 of file core_cm0.h.

#define SCB_ICSR_ISRPREEMPT_Pos 23

SCB ICSR: ISRPREEMPT Position

Definition at line 378 of file core_sc000.h.

#define SCB_ICSR_ISRPREEMPT_Pos 23

SCB ICSR: ISRPREEMPT Position

Definition at line 385 of file core_cm0plus.h.

#define SCB_ICSR_ISRPREEMPT_Pos 23

SCB ICSR: ISRPREEMPT Position

Definition at line 396 of file core_sc300.h.

#define SCB_ICSR_ISRPREEMPT_Pos 23

SCB ICSR: ISRPREEMPT Position

Definition at line 396 of file core_cm3.h.

#define SCB_ICSR_ISRPREEMPT_Pos 23

SCB ICSR: ISRPREEMPT Position

Definition at line 443 of file core_cm4.h.

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 356 of file core_cm0.h.

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 364 of file core_sc000.h.

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 371 of file core_cm0plus.h.

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 382 of file core_cm3.h.

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 382 of file core_sc300.h.

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

Definition at line 429 of file core_cm4.h.

#define SCB_ICSR_NMIPENDSET_Pos 31

SCB ICSR: NMIPENDSET Position

Definition at line 355 of file core_cm0.h.

#define SCB_ICSR_NMIPENDSET_Pos 31

SCB ICSR: NMIPENDSET Position

Definition at line 363 of file core_sc000.h.

#define SCB_ICSR_NMIPENDSET_Pos 31

SCB ICSR: NMIPENDSET Position

Definition at line 370 of file core_cm0plus.h.

#define SCB_ICSR_NMIPENDSET_Pos 31

SCB ICSR: NMIPENDSET Position

Definition at line 381 of file core_sc300.h.

#define SCB_ICSR_NMIPENDSET_Pos 31

SCB ICSR: NMIPENDSET Position

Definition at line 381 of file core_cm3.h.

#define SCB_ICSR_NMIPENDSET_Pos 31

SCB ICSR: NMIPENDSET Position

Definition at line 428 of file core_cm4.h.

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 368 of file core_cm0.h.

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 376 of file core_sc000.h.

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 383 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 394 of file core_cm3.h.

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 394 of file core_sc300.h.

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 441 of file core_cm4.h.

#define SCB_ICSR_PENDSTCLR_Pos 25

SCB ICSR: PENDSTCLR Position

Definition at line 367 of file core_cm0.h.

#define SCB_ICSR_PENDSTCLR_Pos 25

SCB ICSR: PENDSTCLR Position

Definition at line 375 of file core_sc000.h.

#define SCB_ICSR_PENDSTCLR_Pos 25

SCB ICSR: PENDSTCLR Position

Definition at line 382 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTCLR_Pos 25

SCB ICSR: PENDSTCLR Position

Definition at line 393 of file core_sc300.h.

#define SCB_ICSR_PENDSTCLR_Pos 25

SCB ICSR: PENDSTCLR Position

Definition at line 393 of file core_cm3.h.

#define SCB_ICSR_PENDSTCLR_Pos 25

SCB ICSR: PENDSTCLR Position

Definition at line 440 of file core_cm4.h.

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 365 of file core_cm0.h.

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 373 of file core_sc000.h.

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 380 of file core_cm0plus.h.

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 391 of file core_sc300.h.

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 391 of file core_cm3.h.

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 438 of file core_cm4.h.