57 #define K60_EXPECTED_CPUID 0x410fc241u
59 #elif K60_CPU_REV == 1
67 #define K60_EXPECTED_CPUID 0x410fc240u
72 #define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK
73 #define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT
75 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
76 #define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK
77 #define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK
81 #define ADC_BASES { ADC0, ADC1 }
82 #define AIPS_BASES { AIPS0, AIPS1 }
83 #define AXBS_BASES { AXBS }
84 #define CAN_BASES { CAN0, CAN1 }
85 #define CAU_BASES { CAU }
86 #define CMP_BASES { CMP0, CMP1, CMP2 }
87 #define CMT_BASES { CMT }
88 #define CRC_BASES { CRC0 }
89 #define DAC_BASES { DAC0, DAC1 }
90 #define DMA_BASES { DMA0 }
91 #define DMAMUX_BASES { DMAMUX }
92 #define ENET_BASES { ENET }
93 #define EWM_BASES { EWM }
94 #define FB_BASES { FB }
95 #define FMC_BASES { FMC }
96 #define FTFL_BASES { FTFL }
97 #define FTM_BASES { FTM0, FTM1, FTM2 }
98 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
99 #define I2C_BASES { I2C0, I2C1 }
100 #define I2S_BASES { I2S0 }
101 #define LLWU_BASES { LLWU }
102 #define LPTMR_BASES { LPTMR0 }
103 #define MCG_BASES { MCG }
104 #define MCM_BASES { MCM }
105 #define MPU_BASES { MPU }
106 #define NV_BASES { FTFL_FlashConfig }
107 #define OSC_BASES { OSC }
108 #define PDB_BASES { PDB0 }
109 #define PIT_BASES { PIT }
110 #define PMC_BASES { PMC }
111 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
114 #define RFSYS_BASES { RFSYS }
115 #define RFVBAT_BASES { RFVBAT }
116 #define RNG_BASES { RNG }
117 #define RTC_BASES { RTC }
118 #define SDHC_BASES { SDHC }
119 #define SIM_BASES { SIM }
121 #define MC_BASES { MC }
122 #define SPI_BASES { SPI0, SPI1, SPI2 }
123 #define TSI_BASES { TSI0 }
124 #define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
125 #define USB_BASES { USB0 }
126 #define USBDCD_BASES { USBDCD }
127 #define VREF_BASES { VREF }
128 #define WDOG_BASES { WDOG }
131 #error K60_CPU_REV must be set to the correct CPU revision!
153 #define K60_RUNNING_CPU_REVISION (SCB_CPUID & SCB_CPUID_REVISION_MASK)
157 #define K60_H_EXPAND_AND_STRINGIFY(s) K60_H_STRINGIFY(s)
158 #define K60_H_STRINGIFY(s) #s
164 #define DEBUGGER_BREAK(sig) asm volatile ("bkpt #" K60_H_EXPAND_AND_STRINGIFY(sig) "\n")
171 #define BREAK_FAULT_HANDLER 0
172 #define BREAK_INVALID_PARAM 1
174 #define BREAK_MEMORY_CORRUPTION 3
175 #define BREAK_WRONG_K60_CPU_REV 99
177 #define BREAK_SEMIHOSTING 0xAB
USB - Register Layout Typedef.
CRC - Register Layout Typedef.
CMSIS Peripheral Access Layer for MK60D10.
UART - Register Layout Typedef.
SPI - Register Layout Typedef.
Board configuration defines for Mulle platform.
DAC - Register Layout Typedef.
TSI - Register Layout Typedef.
CMP - Register Layout Typedef.
GPIO - Register Layout Typedef.
I2S - Register Layout Typedef.
ADC - Register Layout Typedef.
DMA - Register Layout Typedef.
LPTMR - Register Layout Typedef.
CMSIS Peripheral Access Layer for MK60DZ10.
PORT - Register Layout Typedef.
CAN - Register Layout Typedef.
FTM - Register Layout Typedef.
PDB - Register Layout Typedef.
I2C - Register Layout Typedef.
AIPS - Register Layout Typedef.