MK60DZ10.h File Reference

CMSIS Peripheral Access Layer for MK60DZ10. More...

#include "core_cm4.h"
#include "system_MK60DZ10.h"

Go to the source code of this file.

Data Structures
struct	ADC_Type
	ADC - Register Layout Typedef. More...
struct	AIPS_Type
	AIPS - Register Layout Typedef. More...
struct	AXBS_Type
	AXBS - Register Layout Typedef. More...
struct	CAN_Type
	CAN - Register Layout Typedef. More...
struct	CAU_Type
	CAU - Register Layout Typedef. More...
struct	CMP_Type
	CMP - Register Layout Typedef. More...
struct	CMT_Type
	CMT - Register Layout Typedef. More...
struct	CRC_Type
	CRC - Register Layout Typedef. More...
struct	DAC_Type
	DAC - Register Layout Typedef. More...
struct	DMA_Type
	DMA - Register Layout Typedef. More...
struct	DMAMUX_Type
	DMAMUX - Register Layout Typedef. More...
struct	ENET_Type
	ENET - Register Layout Typedef. More...
struct	EWM_Type
	EWM - Register Layout Typedef. More...
struct	FB_Type
	FB - Register Layout Typedef. More...
struct	FMC_Type
	FMC - Register Layout Typedef. More...
struct	FTFL_Type
	FTFL - Register Layout Typedef. More...
struct	FTM_Type
	FTM - Register Layout Typedef. More...
struct	GPIO_Type
	GPIO - Register Layout Typedef. More...
struct	I2C_Type
	I2C - Register Layout Typedef. More...
struct	I2S_Type
	I2S - Register Layout Typedef. More...
struct	LLWU_Type
	LLWU - Register Layout Typedef. More...
struct	LPTMR_Type
	LPTMR - Register Layout Typedef. More...
struct	MC_Type
	MC - Register Layout Typedef. More...
struct	MCG_Type
	MCG - Register Layout Typedef. More...
struct	MCM_Type
	MCM - Register Layout Typedef. More...
struct	MPU_Type
	MPU - Register Layout Typedef. More...
struct	NV_Type
	NV - Register Layout Typedef. More...
struct	OSC_Type
	OSC - Register Layout Typedef. More...
struct	PDB_Type
	PDB - Register Layout Typedef. More...
struct	PIT_Type
	PIT - Register Layout Typedef. More...
struct	PMC_Type
	PMC - Register Layout Typedef. More...
struct	PORT_Type
	PORT - Register Layout Typedef. More...
struct	RFSYS_Type
	RFSYS - Register Layout Typedef. More...
struct	RFVBAT_Type
	RFVBAT - Register Layout Typedef. More...
struct	RNG_Type
	RNG - Register Layout Typedef. More...
struct	RTC_Type
	RTC - Register Layout Typedef. More...
struct	SDHC_Type
	SDHC - Register Layout Typedef. More...
struct	SIM_Type
	SIM - Register Layout Typedef. More...
struct	SPI_Type
	SPI - Register Layout Typedef. More...
struct	TSI_Type
	TSI - Register Layout Typedef. More...
struct	UART_Type
	UART - Register Layout Typedef. More...
struct	USB_Type
	USB - Register Layout Typedef. More...
struct	USBDCD_Type
	USBDCD - Register Layout Typedef. More...
struct	VREF_Type
	VREF - Register Layout Typedef. More...
struct	WDOG_Type
	WDOG - Register Layout Typedef. More...

Macros
#define	MK60DZ10_H_
	Symbol preventing repeated inclusion.
#define	MCU_MEM_MAP_VERSION   0x0102u
	Memory map version 1.2.
#define	BITBAND_REG(Reg, Bit)   (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
	Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. More...
#define	__CM4_REV   0x0001
	Core revision r0p1.
#define	__MPU_PRESENT   0
	MPU present or not.
#define	__NVIC_PRIO_BITS   4
	Number of Bits used for Priority Levels.
#define	__Vendor_SysTickConfig   0
	Set to 1 if different SysTick Config is used.
#define	__FPU_PRESENT   0
	FPU present or not.
#define	ADC0_BASE   (0x4003B000u)
	Peripheral ADC0 base address.
#define	ADC0   ((ADC_Type *)ADC0_BASE)
	Peripheral ADC0 base pointer.
#define	ADC1_BASE   (0x400BB000u)
	Peripheral ADC1 base address.
#define	ADC1   ((ADC_Type *)ADC1_BASE)
	Peripheral ADC1 base pointer.
#define	AIPS0_BASE   (0x40000000u)
	Peripheral AIPS0 base address.
#define	AIPS0   ((AIPS_Type *)AIPS0_BASE)
	Peripheral AIPS0 base pointer.
#define	AIPS1_BASE   (0x40080000u)
	Peripheral AIPS1 base address.
#define	AIPS1   ((AIPS_Type *)AIPS1_BASE)
	Peripheral AIPS1 base pointer.
#define	AXBS_BASE   (0x40004000u)
	Peripheral AXBS base address.
#define	AXBS   ((AXBS_Type *)AXBS_BASE)
	Peripheral AXBS base pointer.
#define	CAN0_BASE   (0x40024000u)
	Peripheral CAN0 base address.
#define	CAN0   ((CAN_Type *)CAN0_BASE)
	Peripheral CAN0 base pointer.
#define	CAN1_BASE   (0x400A4000u)
	Peripheral CAN1 base address.
#define	CAN1   ((CAN_Type *)CAN1_BASE)
	Peripheral CAN1 base pointer.
#define	CAU_BASE   (0xE0081000u)
	Peripheral CAU base address.
#define	CAU   ((CAU_Type *)CAU_BASE)
	Peripheral CAU base pointer.
#define	CMP0_BASE   (0x40073000u)
	Peripheral CMP0 base address.
#define	CMP0   ((CMP_Type *)CMP0_BASE)
	Peripheral CMP0 base pointer.
#define	CMP1_BASE   (0x40073008u)
	Peripheral CMP1 base address.
#define	CMP1   ((CMP_Type *)CMP1_BASE)
	Peripheral CMP1 base pointer.
#define	CMP2_BASE   (0x40073010u)
	Peripheral CMP2 base address.
#define	CMP2   ((CMP_Type *)CMP2_BASE)
	Peripheral CMP2 base pointer.
#define	CMT_BASE   (0x40062000u)
	Peripheral CMT base address.
#define	CMT   ((CMT_Type *)CMT_BASE)
	Peripheral CMT base pointer.
#define	CRC_BASE   (0x40032000u)
	Peripheral CRC base address.
#define	CRC0   ((CRC_Type *)CRC_BASE)
	Peripheral CRC base pointer.
#define	DAC0_BASE   (0x400CC000u)
	Peripheral DAC0 base address.
#define	DAC0   ((DAC_Type *)DAC0_BASE)
	Peripheral DAC0 base pointer.
#define	DAC1_BASE   (0x400CD000u)
	Peripheral DAC1 base address.
#define	DAC1   ((DAC_Type *)DAC1_BASE)
	Peripheral DAC1 base pointer.
#define	DMA_BASE   (0x40008000u)
	Peripheral DMA base address.
#define	DMA0   ((DMA_Type *)DMA_BASE)
	Peripheral DMA base pointer.
#define	DMAMUX_BASE   (0x40021000u)
	Peripheral DMAMUX base address.
#define	DMAMUX   ((DMAMUX_Type *)DMAMUX_BASE)
	Peripheral DMAMUX base pointer.
#define	ENET_BASE   (0x400C0000u)
	Peripheral ENET base address.
#define	ENET   ((ENET_Type *)ENET_BASE)
	Peripheral ENET base pointer.
#define	EWM_BASE   (0x40061000u)
	Peripheral EWM base address.
#define	EWM   ((EWM_Type *)EWM_BASE)
	Peripheral EWM base pointer.
#define	FB_BASE   (0x4000C000u)
	Peripheral FB base address.
#define	FB   ((FB_Type *)FB_BASE)
	Peripheral FB base pointer.
#define	FMC_BASE   (0x4001F000u)
	Peripheral FMC base address.
#define	FMC   ((FMC_Type *)FMC_BASE)
	Peripheral FMC base pointer.
#define	FTFL_BASE   (0x40020000u)
	Peripheral FTFL base address.
#define	FTFL   ((FTFL_Type *)FTFL_BASE)
	Peripheral FTFL base pointer.
#define	FTM0_BASE   (0x40038000u)
	Peripheral FTM0 base address.
#define	FTM0   ((FTM_Type *)FTM0_BASE)
	Peripheral FTM0 base pointer.
#define	FTM1_BASE   (0x40039000u)
	Peripheral FTM1 base address.
#define	FTM1   ((FTM_Type *)FTM1_BASE)
	Peripheral FTM1 base pointer.
#define	FTM2_BASE   (0x400B8000u)
	Peripheral FTM2 base address.
#define	FTM2   ((FTM_Type *)FTM2_BASE)
	Peripheral FTM2 base pointer.
#define	PTA_BASE   (0x400FF000u)
	Peripheral PTA base address.
#define	PTA   ((GPIO_Type *)PTA_BASE)
	Peripheral PTA base pointer.
#define	PTB_BASE   (0x400FF040u)
	Peripheral PTB base address.
#define	PTB   ((GPIO_Type *)PTB_BASE)
	Peripheral PTB base pointer.
#define	PTC_BASE   (0x400FF080u)
	Peripheral PTC base address.
#define	PTC   ((GPIO_Type *)PTC_BASE)
	Peripheral PTC base pointer.
#define	PTD_BASE   (0x400FF0C0u)
	Peripheral PTD base address.
#define	PTD   ((GPIO_Type *)PTD_BASE)
	Peripheral PTD base pointer.
#define	PTE_BASE   (0x400FF100u)
	Peripheral PTE base address.
#define	PTE   ((GPIO_Type *)PTE_BASE)
	Peripheral PTE base pointer.
#define	I2C0_BASE   (0x40066000u)
	Peripheral I2C0 base address.
#define	I2C0   ((I2C_Type *)I2C0_BASE)
	Peripheral I2C0 base pointer.
#define	I2C1_BASE   (0x40067000u)
	Peripheral I2C1 base address.
#define	I2C1   ((I2C_Type *)I2C1_BASE)
	Peripheral I2C1 base pointer.
#define	I2S0_BASE   (0x4002F000u)
	Peripheral I2S0 base address.
#define	I2S0   ((I2S_Type *)I2S0_BASE)
	Peripheral I2S0 base pointer.
#define	LLWU_BASE   (0x4007C000u)
	Peripheral LLWU base address.
#define	LLWU   ((LLWU_Type *)LLWU_BASE)
	Peripheral LLWU base pointer.
#define	LPTMR0_BASE   (0x40040000u)
	Peripheral LPTMR0 base address.
#define	LPTMR0   ((LPTMR_Type *)LPTMR0_BASE)
	Peripheral LPTMR0 base pointer.
#define	MC_BASE   (0x4007E000u)
	Peripheral MC base address.
#define	MC   ((MC_Type *)MC_BASE)
	Peripheral MC base pointer.
#define	MCG_BASE   (0x40064000u)
	Peripheral MCG base address.
#define	MCG   ((MCG_Type *)MCG_BASE)
	Peripheral MCG base pointer.
#define	MCM_BASE   (0xE0080000u)
	Peripheral MCM base address.
#define	MCM   ((MCM_Type *)MCM_BASE)
	Peripheral MCM base pointer.
#define	MPU_BASE   (0x4000D000u)
	Peripheral MPU base address.
#define	MPU   ((MPU_Type *)MPU_BASE)
	Peripheral MPU base pointer.
#define	FTFL_FlashConfig_BASE   (0x400u)
	Peripheral FTFL_FlashConfig base address.
#define	FTFL_FlashConfig   ((NV_Type *)FTFL_FlashConfig_BASE)
	Peripheral FTFL_FlashConfig base pointer.
#define	OSC_BASE   (0x40065000u)
	Peripheral OSC base address.
#define	OSC   ((OSC_Type *)OSC_BASE)
	Peripheral OSC base pointer.
#define	PDB0_BASE   (0x40036000u)
	Peripheral PDB0 base address.
#define	PDB0   ((PDB_Type *)PDB0_BASE)
	Peripheral PDB0 base pointer.
#define	PIT_BASE   (0x40037000u)
	Peripheral PIT base address.
#define	PIT   ((PIT_Type *)PIT_BASE)
	Peripheral PIT base pointer.
#define	PMC_BASE   (0x4007D000u)
	Peripheral PMC base address.
#define	PMC   ((PMC_Type *)PMC_BASE)
	Peripheral PMC base pointer.
#define	PORTA_BASE   (0x40049000u)
	Peripheral PORTA base address.
#define	PORTA   ((PORT_Type *)PORTA_BASE)
	Peripheral PORTA base pointer.
#define	PORTB_BASE   (0x4004A000u)
	Peripheral PORTB base address.
#define	PORTB   ((PORT_Type *)PORTB_BASE)
	Peripheral PORTB base pointer.
#define	PORTC_BASE   (0x4004B000u)
	Peripheral PORTC base address.
#define	PORTC   ((PORT_Type *)PORTC_BASE)
	Peripheral PORTC base pointer.
#define	PORTD_BASE   (0x4004C000u)
	Peripheral PORTD base address.
#define	PORTD   ((PORT_Type *)PORTD_BASE)
	Peripheral PORTD base pointer.
#define	PORTE_BASE   (0x4004D000u)
	Peripheral PORTE base address.
#define	PORTE   ((PORT_Type *)PORTE_BASE)
	Peripheral PORTE base pointer.
#define	RFSYS_BASE   (0x40041000u)
	Peripheral RFSYS base address.
#define	RFSYS   ((RFSYS_Type *)RFSYS_BASE)
	Peripheral RFSYS base pointer.
#define	RFVBAT_BASE   (0x4003E000u)
	Peripheral RFVBAT base address.
#define	RFVBAT   ((RFVBAT_Type *)RFVBAT_BASE)
	Peripheral RFVBAT base pointer.
#define	RNG_BASE   (0x400A0000u)
	Peripheral RNG base address.
#define	RNG   ((RNG_Type *)RNG_BASE)
	Peripheral RNG base pointer.
#define	RTC_BASE   (0x4003D000u)
	Peripheral RTC base address.
#define	RTC   ((RTC_Type *)RTC_BASE)
	Peripheral RTC base pointer.
#define	SDHC_BASE   (0x400B1000u)
	Peripheral SDHC base address.
#define	SDHC   ((SDHC_Type *)SDHC_BASE)
	Peripheral SDHC base pointer.
#define	SIM_BASE   (0x40047000u)
	Peripheral SIM base address.
#define	SIM   ((SIM_Type *)SIM_BASE)
	Peripheral SIM base pointer.
#define	SPI0_BASE   (0x4002C000u)
	Peripheral SPI0 base address.
#define	SPI0   ((SPI_Type *)SPI0_BASE)
	Peripheral SPI0 base pointer.
#define	SPI1_BASE   (0x4002D000u)
	Peripheral SPI1 base address.
#define	SPI1   ((SPI_Type *)SPI1_BASE)
	Peripheral SPI1 base pointer.
#define	SPI2_BASE   (0x400AC000u)
	Peripheral SPI2 base address.
#define	SPI2   ((SPI_Type *)SPI2_BASE)
	Peripheral SPI2 base pointer.
#define	TSI0_BASE   (0x40045000u)
	Peripheral TSI0 base address.
#define	TSI0   ((TSI_Type *)TSI0_BASE)
	Peripheral TSI0 base pointer.
#define	UART0_BASE   (0x4006A000u)
	Peripheral UART0 base address.
#define	UART0   ((UART_Type *)UART0_BASE)
	Peripheral UART0 base pointer.
#define	UART1_BASE   (0x4006B000u)
	Peripheral UART1 base address.
#define	UART1   ((UART_Type *)UART1_BASE)
	Peripheral UART1 base pointer.
#define	UART2_BASE   (0x4006C000u)
	Peripheral UART2 base address.
#define	UART2   ((UART_Type *)UART2_BASE)
	Peripheral UART2 base pointer.
#define	UART3_BASE   (0x4006D000u)
	Peripheral UART3 base address.
#define	UART3   ((UART_Type *)UART3_BASE)
	Peripheral UART3 base pointer.
#define	UART4_BASE   (0x400EA000u)
	Peripheral UART4 base address.
#define	UART4   ((UART_Type *)UART4_BASE)
	Peripheral UART4 base pointer.
#define	UART5_BASE   (0x400EB000u)
	Peripheral UART5 base address.
#define	UART5   ((UART_Type *)UART5_BASE)
	Peripheral UART5 base pointer.
#define	USB0_BASE   (0x40072000u)
	Peripheral USB0 base address.
#define	USB0   ((USB_Type *)USB0_BASE)
	Peripheral USB0 base pointer.
#define	USBDCD_BASE   (0x40035000u)
	Peripheral USBDCD base address.
#define	USBDCD   ((USBDCD_Type *)USBDCD_BASE)
	Peripheral USBDCD base pointer.
#define	VREF_BASE   (0x40074000u)
	Peripheral VREF base address.
#define	VREF   ((VREF_Type *)VREF_BASE)
	Peripheral VREF base pointer.
#define	WDOG_BASE   (0x40052000u)
	Peripheral WDOG base address.
#define	WDOG   ((WDOG_Type *)WDOG_BASE)
	Peripheral WDOG base pointer.

Typedefs
typedef enum IRQn	IRQn_Type
	Interrupt Number Definitions.

Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, DMA0_IRQn = 0, DMA1_IRQn = 1, DMA2_IRQn = 2,   DMA3_IRQn = 3, DMA4_IRQn = 4, DMA5_IRQn = 5, DMA6_IRQn = 6,   DMA7_IRQn = 7, DMA8_IRQn = 8, DMA9_IRQn = 9, DMA10_IRQn = 10,   DMA11_IRQn = 11, DMA12_IRQn = 12, DMA13_IRQn = 13, DMA14_IRQn = 14,   DMA15_IRQn = 15, DMA_Error_IRQn = 16, MCM_IRQn = 17, FTFL_IRQn = 18,   Read_Collision_IRQn = 19, LVD_LVW_IRQn = 20, LLW_IRQn = 21, Watchdog_IRQn = 22,   RNG_IRQn = 23, I2C0_IRQn = 24, I2C1_IRQn = 25, SPI0_IRQn = 26,   SPI1_IRQn = 27, SPI2_IRQn = 28, CAN0_ORed_Message_buffer_IRQn = 29, CAN0_Bus_Off_IRQn = 30,   CAN0_Error_IRQn = 31, CAN0_Tx_Warning_IRQn = 32, CAN0_Rx_Warning_IRQn = 33, CAN0_Wake_Up_IRQn = 34,   I2S0_Tx_IRQn = 35, I2S0_Rx_IRQn = 36, CAN1_ORed_Message_buffer_IRQn = 37, CAN1_Bus_Off_IRQn = 38,   CAN1_Error_IRQn = 39, CAN1_Tx_Warning_IRQn = 40, CAN1_Rx_Warning_IRQn = 41, CAN1_Wake_Up_IRQn = 42,   Reserved59_IRQn = 43, UART0_LON_IRQn = 44, UART0_RX_TX_IRQn = 45, UART0_ERR_IRQn = 46,   UART1_RX_TX_IRQn = 47, UART1_ERR_IRQn = 48, UART2_RX_TX_IRQn = 49, UART2_ERR_IRQn = 50,   UART3_RX_TX_IRQn = 51, UART3_ERR_IRQn = 52, UART4_RX_TX_IRQn = 53, UART4_ERR_IRQn = 54,   UART5_RX_TX_IRQn = 55, UART5_ERR_IRQn = 56, ADC0_IRQn = 57, ADC1_IRQn = 58,   CMP0_IRQn = 59, CMP1_IRQn = 60, CMP2_IRQn = 61, FTM0_IRQn = 62,   FTM1_IRQn = 63, FTM2_IRQn = 64, CMT_IRQn = 65, RTC_IRQn = 66,   RTC_Seconds_IRQn = 67, PIT0_IRQn = 68, PIT1_IRQn = 69, PIT2_IRQn = 70,   PIT3_IRQn = 71, PDB0_IRQn = 72, USB0_IRQn = 73, USBDCD_IRQn = 74,   ENET_1588_Timer_IRQn = 75, ENET_Transmit_IRQn = 76, ENET_Receive_IRQn = 77, ENET_Error_IRQn = 78,   Reserved95_IRQn = 79, SDHC_IRQn = 80, DAC0_IRQn = 81, DAC1_IRQn = 82,   TSI0_IRQn = 83, MCG_IRQn = 84, LPTimer_IRQn = 85, Reserved102_IRQn = 86,   PORTA_IRQn = 87, PORTB_IRQn = 88, PORTC_IRQn = 89, PORTD_IRQn = 90,   PORTE_IRQn = 91, Reserved108_IRQn = 92, Reserved109_IRQn = 93, SWI_IRQn = 94,   Reserved111_IRQn = 95, Reserved112_IRQn = 96, Reserved113_IRQn = 97, Reserved114_IRQn = 98,   Reserved115_IRQn = 99, Reserved116_IRQn = 100, Reserved117_IRQn = 101, Reserved118_IRQn = 102,   Reserved119_IRQn = 103, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, DMA0_IRQn = 0, DMA1_IRQn = 1, DMA2_IRQn = 2,   DMA3_IRQn = 3, DMA4_IRQn = 4, DMA5_IRQn = 5, DMA6_IRQn = 6,   DMA7_IRQn = 7, DMA8_IRQn = 8, DMA9_IRQn = 9, DMA10_IRQn = 10,   DMA11_IRQn = 11, DMA12_IRQn = 12, DMA13_IRQn = 13, DMA14_IRQn = 14,   DMA15_IRQn = 15, DMA_Error_IRQn = 16, MCM_IRQn = 17, FTFL_IRQn = 18,   Read_Collision_IRQn = 19, LVD_LVW_IRQn = 20, LLW_IRQn = 21, Watchdog_IRQn = 22,   RNG_IRQn = 23, I2C0_IRQn = 24, I2C1_IRQn = 25, SPI0_IRQn = 26,   SPI1_IRQn = 27, SPI2_IRQn = 28, CAN0_ORed_Message_buffer_IRQn = 29, CAN0_Bus_Off_IRQn = 30,   CAN0_Error_IRQn = 31, CAN0_Tx_Warning_IRQn = 32, CAN0_Rx_Warning_IRQn = 33, CAN0_Wake_Up_IRQn = 34,   Reserved51_IRQn = 35, Reserved52_IRQn = 36, CAN1_ORed_Message_buffer_IRQn = 37, CAN1_Bus_Off_IRQn = 38,   CAN1_Error_IRQn = 39, CAN1_Tx_Warning_IRQn = 40, CAN1_Rx_Warning_IRQn = 41, CAN1_Wake_Up_IRQn = 42,   Reserved59_IRQn = 43, Reserved60_IRQn = 44, UART0_RX_TX_IRQn = 45, UART0_ERR_IRQn = 46,   UART1_RX_TX_IRQn = 47, UART1_ERR_IRQn = 48, UART2_RX_TX_IRQn = 49, UART2_ERR_IRQn = 50,   UART3_RX_TX_IRQn = 51, UART3_ERR_IRQn = 52, UART4_RX_TX_IRQn = 53, UART4_ERR_IRQn = 54,   UART5_RX_TX_IRQn = 55, UART5_ERR_IRQn = 56, ADC0_IRQn = 57, ADC1_IRQn = 58,   CMP0_IRQn = 59, CMP1_IRQn = 60, CMP2_IRQn = 61, FTM0_IRQn = 62,   FTM1_IRQn = 63, FTM2_IRQn = 64, CMT_IRQn = 65, RTC_IRQn = 66,   Reserved83_IRQn = 67, PIT0_IRQn = 68, PIT1_IRQn = 69, PIT2_IRQn = 70,   PIT3_IRQn = 71, PDB0_IRQn = 72, USB0_IRQn = 73, USBDCD_IRQn = 74,   ENET_1588_Timer_IRQn = 75, ENET_Transmit_IRQn = 76, ENET_Receive_IRQn = 77, ENET_Error_IRQn = 78,   I2S0_IRQn = 79, SDHC_IRQn = 80, DAC0_IRQn = 81, DAC1_IRQn = 82,   TSI0_IRQn = 83, MCG_IRQn = 84, LPTimer_IRQn = 85, Reserved102_IRQn = 86,   PORTA_IRQn = 87, PORTB_IRQn = 88, PORTC_IRQn = 89, PORTD_IRQn = 90,   PORTE_IRQn = 91, Reserved108_IRQn = 92, Reserved109_IRQn = 93, Reserved110_IRQn = 94,   Reserved111_IRQn = 95, Reserved112_IRQn = 96, Reserved113_IRQn = 97, Reserved114_IRQn = 98,   Reserved115_IRQn = 99, Reserved116_IRQn = 100, Reserved117_IRQn = 101, Reserved118_IRQn = 102,   Reserved119_IRQn = 103 }
	Interrupt Number Definitions. More...

Detailed Description

CMSIS Peripheral Access Layer for MK60DZ10.

Version

1.2

Date

2011-09-08 CMSIS Peripheral Access Layer for MK60DZ10

Definition in file MK60DZ10.h.

Macro Definition Documentation

#define BITBAND_REG	(		Reg,
			Bit
	)		(*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))

Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access.

Parameters

Reg	Register to access.
Bit	Bit number to access.

Returns

Value of the targeted bit in the bit band region.

Definition at line 73 of file MK60DZ10.h.