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MK60DZ10.h
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1 /*
2 ** ###################################################################
3 ** Processors: MK60DN512ZVLL10
4 ** MK60DX256ZVLL10
5 ** MK60DN256ZVLL10
6 ** MK60DN512ZVLQ10
7 ** MK60DN256ZVLQ10
8 ** MK60DX256ZVLQ10
9 ** MK60DN512ZVMC10
10 ** MK60DN256ZVMC10
11 ** MK60DX256ZVMC10
12 ** MK60DN512ZVMD10
13 ** MK60DX256ZVMD10
14 ** MK60DN256ZVMD10
15 **
16 ** Compilers: ARM Compiler
17 ** Freescale C/C++ for Embedded ARM
18 ** GNU C Compiler
19 ** IAR ANSI C/C++ Compiler for ARM
20 **
21 ** Reference manual: K60P144M100SF2RM, Rev. 5, 8 May 2011
22 ** Version: rev. 1.2, 2011-09-08
23 **
24 ** Abstract:
25 ** CMSIS Peripheral Access Layer for MK60DZ10
26 **
27 ** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
28 **
29 ** http: www.freescale.com
30 ** mail: support@freescale.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2011-06-10)
34 ** Initial version.
35 ** Changes with respect to the previous MK60NxxxMD100 header file:
36 ** RTC - CCR register removed. Replaced by IER register.
37 ** CRC - added CTRLHU register for 8-bit access to the CTRL register.
38 ** FB - bit FB_CSCR_EXALE renamed to FB_CSCR_EXTS.
39 ** SIM - bit group FSIZE in SIM_FCFG1 split into groups PFSIZE and NVMSIZE.
40 ** I2S - bit SSIEN in I2S_CR register renamed to I2SEN.
41 ** SDHC - bit VOLTSEL in SDHC_VENDOR register removed.
42 ** - rev. 1.1 (2011-06-29)
43 ** Order of declarations changed.
44 ** - rev. 1.2 (2011-09-08)
45 ** Cortex_Core_Configuration extended with additional parameters.
46 ** Gap between end of interrupt vector table and flash configuration field filled by default ISR.
47 **
48 ** ###################################################################
49 */
50 
51 /**
52  * @file MK60DZ10.h
53  * @version 1.2
54  * @date 2011-09-08
55  * @brief CMSIS Peripheral Access Layer for MK60DZ10
56  *
57  * CMSIS Peripheral Access Layer for MK60DZ10
58  */
59 
60 #if !defined(MK60DZ10_H_)
61 #define MK60DZ10_H_ /**< Symbol preventing repeated inclusion */
62 
63 /** Memory map version 1.2 */
64 #define MCU_MEM_MAP_VERSION 0x0102u
65 
66 /**
67  * @brief Macro to access a single bit of a peripheral register (bit band region
68  * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
69  * @param Reg Register to access.
70  * @param Bit Bit number to access.
71  * @return Value of the targeted bit in the bit band region.
72  */
73 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
74 
75 /* ----------------------------------------------------------------------------
76  -- Interrupt vector numbers
77  ---------------------------------------------------------------------------- */
78 
79 /**
80  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
81  * @{
82  */
83 
84 /** Interrupt Number Definitions */
85 typedef enum IRQn {
86  /* Core interrupts */
87  NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
88  MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
89  BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
90  UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
91  SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
92  DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
93  PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
94  SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
95 
96  /* Device specific interrupts */
97  DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
98  DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
99  DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
100  DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
101  DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
102  DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
103  DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
104  DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
105  DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
106  DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
107  DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
108  DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
109  DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
110  DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
111  DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
112  DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
113  DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
114  MCM_IRQn = 17, /**< Normal Interrupt */
115  FTFL_IRQn = 18, /**< FTFL Interrupt */
116  Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
117  LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
118  LLW_IRQn = 21, /**< Low Leakage Wakeup */
119  Watchdog_IRQn = 22, /**< WDOG Interrupt */
120  RNG_IRQn = 23, /**< RNGB Interrupt */
121  I2C0_IRQn = 24, /**< I2C0 interrupt */
122  I2C1_IRQn = 25, /**< I2C1 interrupt */
123  SPI0_IRQn = 26, /**< SPI0 Interrupt */
124  SPI1_IRQn = 27, /**< SPI1 Interrupt */
125  SPI2_IRQn = 28, /**< SPI2 Interrupt */
126  CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd Message Buffers Interrupt */
127  CAN0_Bus_Off_IRQn = 30, /**< CAN0 Bus Off Interrupt */
128  CAN0_Error_IRQn = 31, /**< CAN0 Error Interrupt */
129  CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx Warning Interrupt */
130  CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx Warning Interrupt */
131  CAN0_Wake_Up_IRQn = 34, /**< CAN0 Wake Up Interrupt */
132  Reserved51_IRQn = 35, /**< Reserved interrupt 51 */
133  Reserved52_IRQn = 36, /**< Reserved interrupt 52 */
134  CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd Message Buffers Interrupt */
135  CAN1_Bus_Off_IRQn = 38, /**< CAN1 Bus Off Interrupt */
136  CAN1_Error_IRQn = 39, /**< CAN1 Error Interrupt */
137  CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx Warning Interrupt */
138  CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx Warning Interrupt */
139  CAN1_Wake_Up_IRQn = 42, /**< CAN1 Wake Up Interrupt */
140  Reserved59_IRQn = 43, /**< Reserved interrupt 59 */
141  Reserved60_IRQn = 44, /**< Reserved interrupt 60 */
142  UART0_RX_TX_IRQn = 45, /**< UART0 Receive/Transmit interrupt */
143  UART0_ERR_IRQn = 46, /**< UART0 Error interrupt */
144  UART1_RX_TX_IRQn = 47, /**< UART1 Receive/Transmit interrupt */
145  UART1_ERR_IRQn = 48, /**< UART1 Error interrupt */
146  UART2_RX_TX_IRQn = 49, /**< UART2 Receive/Transmit interrupt */
147  UART2_ERR_IRQn = 50, /**< UART2 Error interrupt */
148  UART3_RX_TX_IRQn = 51, /**< UART3 Receive/Transmit interrupt */
149  UART3_ERR_IRQn = 52, /**< UART3 Error interrupt */
150  UART4_RX_TX_IRQn = 53, /**< UART4 Receive/Transmit interrupt */
151  UART4_ERR_IRQn = 54, /**< UART4 Error interrupt */
152  UART5_RX_TX_IRQn = 55, /**< UART5 Receive/Transmit interrupt */
153  UART5_ERR_IRQn = 56, /**< UART5 Error interrupt */
154  ADC0_IRQn = 57, /**< ADC0 interrupt */
155  ADC1_IRQn = 58, /**< ADC1 interrupt */
156  CMP0_IRQn = 59, /**< CMP0 interrupt */
157  CMP1_IRQn = 60, /**< CMP1 interrupt */
158  CMP2_IRQn = 61, /**< CMP2 interrupt */
159  FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
160  FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
161  FTM2_IRQn = 64, /**< FTM2 fault, overflow and channels interrupt */
162  CMT_IRQn = 65, /**< CMT interrupt */
163  RTC_IRQn = 66, /**< RTC interrupt */
164  Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
165  PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
166  PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
167  PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
168  PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
169  PDB0_IRQn = 72, /**< PDB0 Interrupt */
170  USB0_IRQn = 73, /**< USB0 interrupt */
171  USBDCD_IRQn = 74, /**< USBDCD Interrupt */
172  ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
173  ENET_Transmit_IRQn = 76, /**< Ethernet MAC Transmit Interrupt */
174  ENET_Receive_IRQn = 77, /**< Ethernet MAC Receive Interrupt */
175  ENET_Error_IRQn = 78, /**< Ethernet MAC Error and miscelaneous Interrupt */
176  I2S0_IRQn = 79, /**< I2S0 Interrupt */
177  SDHC_IRQn = 80, /**< SDHC Interrupt */
178  DAC0_IRQn = 81, /**< DAC0 interrupt */
179  DAC1_IRQn = 82, /**< DAC1 interrupt */
180  TSI0_IRQn = 83, /**< TSI0 Interrupt */
181  MCG_IRQn = 84, /**< MCG Interrupt */
182  LPTimer_IRQn = 85, /**< LPTimer interrupt */
183  Reserved102_IRQn = 86, /**< Reserved interrupt 102 */
184  PORTA_IRQn = 87, /**< Port A interrupt */
185  PORTB_IRQn = 88, /**< Port B interrupt */
186  PORTC_IRQn = 89, /**< Port C interrupt */
187  PORTD_IRQn = 90, /**< Port D interrupt */
188  PORTE_IRQn = 91, /**< Port E interrupt */
189  Reserved108_IRQn = 92, /**< Reserved interrupt 108 */
190  Reserved109_IRQn = 93, /**< Reserved interrupt 109 */
191  Reserved110_IRQn = 94, /**< Reserved interrupt 110 */
192  Reserved111_IRQn = 95, /**< Reserved interrupt 111 */
193  Reserved112_IRQn = 96, /**< Reserved interrupt 112 */
194  Reserved113_IRQn = 97, /**< Reserved interrupt 113 */
195  Reserved114_IRQn = 98, /**< Reserved interrupt 114 */
196  Reserved115_IRQn = 99, /**< Reserved interrupt 115 */
197  Reserved116_IRQn = 100, /**< Reserved interrupt 116 */
198  Reserved117_IRQn = 101, /**< Reserved interrupt 117 */
199  Reserved118_IRQn = 102, /**< Reserved interrupt 118 */
200  Reserved119_IRQn = 103 /**< Reserved interrupt 119 */
201 } IRQn_Type;
202 
203 /**
204  * @}
205  */ /* end of group Interrupt_vector_numbers */
206 
207 
208 /* ----------------------------------------------------------------------------
209  -- Configuration of the Cortex-M4 Processor and Core Peripherals
210  ---------------------------------------------------------------------------- */
211 
212 /**
213  * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
214  * @{
215  */
216 
217 #define __CM4_REV 0x0001 /**< Core revision r0p1 */
218 #define __MPU_PRESENT 0 /**< MPU present or not */
219 #define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
220 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
221 #define __FPU_PRESENT 0 /**< FPU present or not */
222 
223 #include "core_cm4.h" /* Core Peripheral Access Layer */
224 #include "system_MK60DZ10.h" /* Device specific configuration file */
225 
226 /**
227  * @}
228  */ /* end of group Cortex_Core_Configuration */
229 
230 
231 /* ----------------------------------------------------------------------------
232  -- Device Peripheral Access Layer
233  ---------------------------------------------------------------------------- */
234 
235 /**
236  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
237  * @{
238  */
239 
240 
241 /*
242 ** Start of section using anonymous unions
243 */
244 
245 #if defined(__ARMCC_VERSION)
246  #pragma push
247  #pragma anon_unions
248 #elif defined(__CWCC__)
249  #pragma push
250  #pragma cpp_extensions on
251 #elif defined(__GNUC__)
252  /* anonymous unions are enabled by default */
253 #elif defined(__IAR_SYSTEMS_ICC__)
254  #pragma language=extended
255 #else
256  #error Not supported compiler type
257 #endif
258 
259 /* ----------------------------------------------------------------------------
260  -- ADC Peripheral Access Layer
261  ---------------------------------------------------------------------------- */
262 
263 /**
264  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
265  * @{
266  */
267 
268 /** ADC - Register Layout Typedef */
269 typedef struct {
270  __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
271  __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
272  __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
273  __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
274  __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
275  __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
276  __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
277  __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
278  __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
279  __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
280  __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
281  __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
282  __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
283  __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
284  __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
285  __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
286  __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
287  __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
288  __IO uint32_t PGA; /**< ADC PGA register, offset: 0x50 */
289  __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
290  __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
291  __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
292  __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
293  __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
294  __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
295  __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
296 } ADC_Type;
297 
298 /* ----------------------------------------------------------------------------
299  -- ADC Register Masks
300  ---------------------------------------------------------------------------- */
301 
302 /**
303  * @addtogroup ADC_Register_Masks ADC Register Masks
304  * @{
305  */
306 
307 /* SC1 Bit Fields */
308 #define ADC_SC1_ADCH_MASK 0x1Fu
309 #define ADC_SC1_ADCH_SHIFT 0
310 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
311 #define ADC_SC1_DIFF_MASK 0x20u
312 #define ADC_SC1_DIFF_SHIFT 5
313 #define ADC_SC1_AIEN_MASK 0x40u
314 #define ADC_SC1_AIEN_SHIFT 6
315 #define ADC_SC1_COCO_MASK 0x80u
316 #define ADC_SC1_COCO_SHIFT 7
317 /* CFG1 Bit Fields */
318 #define ADC_CFG1_ADICLK_MASK 0x3u
319 #define ADC_CFG1_ADICLK_SHIFT 0
320 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
321 #define ADC_CFG1_MODE_MASK 0xCu
322 #define ADC_CFG1_MODE_SHIFT 2
323 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
324 #define ADC_CFG1_ADLSMP_MASK 0x10u
325 #define ADC_CFG1_ADLSMP_SHIFT 4
326 #define ADC_CFG1_ADIV_MASK 0x60u
327 #define ADC_CFG1_ADIV_SHIFT 5
328 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
329 #define ADC_CFG1_ADLPC_MASK 0x80u
330 #define ADC_CFG1_ADLPC_SHIFT 7
331 /* CFG2 Bit Fields */
332 #define ADC_CFG2_ADLSTS_MASK 0x3u
333 #define ADC_CFG2_ADLSTS_SHIFT 0
334 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
335 #define ADC_CFG2_ADHSC_MASK 0x4u
336 #define ADC_CFG2_ADHSC_SHIFT 2
337 #define ADC_CFG2_ADACKEN_MASK 0x8u
338 #define ADC_CFG2_ADACKEN_SHIFT 3
339 #define ADC_CFG2_MUXSEL_MASK 0x10u
340 #define ADC_CFG2_MUXSEL_SHIFT 4
341 /* R Bit Fields */
342 #define ADC_R_D_MASK 0xFFFFu
343 #define ADC_R_D_SHIFT 0
344 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
345 /* CV1 Bit Fields */
346 #define ADC_CV1_CV_MASK 0xFFFFu
347 #define ADC_CV1_CV_SHIFT 0
348 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
349 /* CV2 Bit Fields */
350 #define ADC_CV2_CV_MASK 0xFFFFu
351 #define ADC_CV2_CV_SHIFT 0
352 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
353 /* SC2 Bit Fields */
354 #define ADC_SC2_REFSEL_MASK 0x3u
355 #define ADC_SC2_REFSEL_SHIFT 0
356 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
357 #define ADC_SC2_DMAEN_MASK 0x4u
358 #define ADC_SC2_DMAEN_SHIFT 2
359 #define ADC_SC2_ACREN_MASK 0x8u
360 #define ADC_SC2_ACREN_SHIFT 3
361 #define ADC_SC2_ACFGT_MASK 0x10u
362 #define ADC_SC2_ACFGT_SHIFT 4
363 #define ADC_SC2_ACFE_MASK 0x20u
364 #define ADC_SC2_ACFE_SHIFT 5
365 #define ADC_SC2_ADTRG_MASK 0x40u
366 #define ADC_SC2_ADTRG_SHIFT 6
367 #define ADC_SC2_ADACT_MASK 0x80u
368 #define ADC_SC2_ADACT_SHIFT 7
369 /* SC3 Bit Fields */
370 #define ADC_SC3_AVGS_MASK 0x3u
371 #define ADC_SC3_AVGS_SHIFT 0
372 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
373 #define ADC_SC3_AVGE_MASK 0x4u
374 #define ADC_SC3_AVGE_SHIFT 2
375 #define ADC_SC3_ADCO_MASK 0x8u
376 #define ADC_SC3_ADCO_SHIFT 3
377 #define ADC_SC3_CALF_MASK 0x40u
378 #define ADC_SC3_CALF_SHIFT 6
379 #define ADC_SC3_CAL_MASK 0x80u
380 #define ADC_SC3_CAL_SHIFT 7
381 /* OFS Bit Fields */
382 #define ADC_OFS_OFS_MASK 0xFFFFu
383 #define ADC_OFS_OFS_SHIFT 0
384 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
385 /* PG Bit Fields */
386 #define ADC_PG_PG_MASK 0xFFFFu
387 #define ADC_PG_PG_SHIFT 0
388 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
389 /* MG Bit Fields */
390 #define ADC_MG_MG_MASK 0xFFFFu
391 #define ADC_MG_MG_SHIFT 0
392 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
393 /* CLPD Bit Fields */
394 #define ADC_CLPD_CLPD_MASK 0x3Fu
395 #define ADC_CLPD_CLPD_SHIFT 0
396 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
397 /* CLPS Bit Fields */
398 #define ADC_CLPS_CLPS_MASK 0x3Fu
399 #define ADC_CLPS_CLPS_SHIFT 0
400 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
401 /* CLP4 Bit Fields */
402 #define ADC_CLP4_CLP4_MASK 0x3FFu
403 #define ADC_CLP4_CLP4_SHIFT 0
404 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
405 /* CLP3 Bit Fields */
406 #define ADC_CLP3_CLP3_MASK 0x1FFu
407 #define ADC_CLP3_CLP3_SHIFT 0
408 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
409 /* CLP2 Bit Fields */
410 #define ADC_CLP2_CLP2_MASK 0xFFu
411 #define ADC_CLP2_CLP2_SHIFT 0
412 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
413 /* CLP1 Bit Fields */
414 #define ADC_CLP1_CLP1_MASK 0x7Fu
415 #define ADC_CLP1_CLP1_SHIFT 0
416 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
417 /* CLP0 Bit Fields */
418 #define ADC_CLP0_CLP0_MASK 0x3Fu
419 #define ADC_CLP0_CLP0_SHIFT 0
420 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
421 /* PGA Bit Fields */
422 #define ADC_PGA_PGAG_MASK 0xF0000u
423 #define ADC_PGA_PGAG_SHIFT 16
424 #define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
425 #define ADC_PGA_PGAEN_MASK 0x800000u
426 #define ADC_PGA_PGAEN_SHIFT 23
427 /* CLMD Bit Fields */
428 #define ADC_CLMD_CLMD_MASK 0x3Fu
429 #define ADC_CLMD_CLMD_SHIFT 0
430 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
431 /* CLMS Bit Fields */
432 #define ADC_CLMS_CLMS_MASK 0x3Fu
433 #define ADC_CLMS_CLMS_SHIFT 0
434 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
435 /* CLM4 Bit Fields */
436 #define ADC_CLM4_CLM4_MASK 0x3FFu
437 #define ADC_CLM4_CLM4_SHIFT 0
438 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
439 /* CLM3 Bit Fields */
440 #define ADC_CLM3_CLM3_MASK 0x1FFu
441 #define ADC_CLM3_CLM3_SHIFT 0
442 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
443 /* CLM2 Bit Fields */
444 #define ADC_CLM2_CLM2_MASK 0xFFu
445 #define ADC_CLM2_CLM2_SHIFT 0
446 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
447 /* CLM1 Bit Fields */
448 #define ADC_CLM1_CLM1_MASK 0x7Fu
449 #define ADC_CLM1_CLM1_SHIFT 0
450 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
451 /* CLM0 Bit Fields */
452 #define ADC_CLM0_CLM0_MASK 0x3Fu
453 #define ADC_CLM0_CLM0_SHIFT 0
454 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
455 
456 /**
457  * @}
458  */ /* end of group ADC_Register_Masks */
459 
460 
461 /* ADC - Peripheral instance base addresses */
462 /** Peripheral ADC0 base address */
463 #define ADC0_BASE (0x4003B000u)
464 /** Peripheral ADC0 base pointer */
465 #define ADC0 ((ADC_Type *)ADC0_BASE)
466 /** Peripheral ADC1 base address */
467 #define ADC1_BASE (0x400BB000u)
468 /** Peripheral ADC1 base pointer */
469 #define ADC1 ((ADC_Type *)ADC1_BASE)
470 
471 /**
472  * @}
473  */ /* end of group ADC_Peripheral_Access_Layer */
474 
475 
476 /* ----------------------------------------------------------------------------
477  -- AIPS Peripheral Access Layer
478  ---------------------------------------------------------------------------- */
479 
480 /**
481  * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
482  * @{
483  */
484 
485 /** AIPS - Register Layout Typedef */
486 typedef struct {
487  __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
488  uint8_t RESERVED_0[28];
489  __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
490  __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
491  __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
492  __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
493  uint8_t RESERVED_1[16];
494  __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
495  __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
496  __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
497  __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
498  __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
499  __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
500  __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
501  __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
502  __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
503  __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
504  __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
505  __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
506 } AIPS_Type;
507 
508 /* ----------------------------------------------------------------------------
509  -- AIPS Register Masks
510  ---------------------------------------------------------------------------- */
511 
512 /**
513  * @addtogroup AIPS_Register_Masks AIPS Register Masks
514  * @{
515  */
516 
517 /* MPRA Bit Fields */
518 #define AIPS_MPRA_MPL5_MASK 0x100u
519 #define AIPS_MPRA_MPL5_SHIFT 8
520 #define AIPS_MPRA_MTW5_MASK 0x200u
521 #define AIPS_MPRA_MTW5_SHIFT 9
522 #define AIPS_MPRA_MTR5_MASK 0x400u
523 #define AIPS_MPRA_MTR5_SHIFT 10
524 #define AIPS_MPRA_MPL4_MASK 0x1000u
525 #define AIPS_MPRA_MPL4_SHIFT 12
526 #define AIPS_MPRA_MTW4_MASK 0x2000u
527 #define AIPS_MPRA_MTW4_SHIFT 13
528 #define AIPS_MPRA_MTR4_MASK 0x4000u
529 #define AIPS_MPRA_MTR4_SHIFT 14
530 #define AIPS_MPRA_MPL3_MASK 0x10000u
531 #define AIPS_MPRA_MPL3_SHIFT 16
532 #define AIPS_MPRA_MTW3_MASK 0x20000u
533 #define AIPS_MPRA_MTW3_SHIFT 17
534 #define AIPS_MPRA_MTR3_MASK 0x40000u
535 #define AIPS_MPRA_MTR3_SHIFT 18
536 #define AIPS_MPRA_MPL2_MASK 0x100000u
537 #define AIPS_MPRA_MPL2_SHIFT 20
538 #define AIPS_MPRA_MTW2_MASK 0x200000u
539 #define AIPS_MPRA_MTW2_SHIFT 21
540 #define AIPS_MPRA_MTR2_MASK 0x400000u
541 #define AIPS_MPRA_MTR2_SHIFT 22
542 #define AIPS_MPRA_MPL1_MASK 0x1000000u
543 #define AIPS_MPRA_MPL1_SHIFT 24
544 #define AIPS_MPRA_MTW1_MASK 0x2000000u
545 #define AIPS_MPRA_MTW1_SHIFT 25
546 #define AIPS_MPRA_MTR1_MASK 0x4000000u
547 #define AIPS_MPRA_MTR1_SHIFT 26
548 #define AIPS_MPRA_MPL0_MASK 0x10000000u
549 #define AIPS_MPRA_MPL0_SHIFT 28
550 #define AIPS_MPRA_MTW0_MASK 0x20000000u
551 #define AIPS_MPRA_MTW0_SHIFT 29
552 #define AIPS_MPRA_MTR0_MASK 0x40000000u
553 #define AIPS_MPRA_MTR0_SHIFT 30
554 /* PACRA Bit Fields */
555 #define AIPS_PACRA_TP7_MASK 0x1u
556 #define AIPS_PACRA_TP7_SHIFT 0
557 #define AIPS_PACRA_WP7_MASK 0x2u
558 #define AIPS_PACRA_WP7_SHIFT 1
559 #define AIPS_PACRA_SP7_MASK 0x4u
560 #define AIPS_PACRA_SP7_SHIFT 2
561 #define AIPS_PACRA_TP6_MASK 0x10u
562 #define AIPS_PACRA_TP6_SHIFT 4
563 #define AIPS_PACRA_WP6_MASK 0x20u
564 #define AIPS_PACRA_WP6_SHIFT 5
565 #define AIPS_PACRA_SP6_MASK 0x40u
566 #define AIPS_PACRA_SP6_SHIFT 6
567 #define AIPS_PACRA_TP5_MASK 0x100u
568 #define AIPS_PACRA_TP5_SHIFT 8
569 #define AIPS_PACRA_WP5_MASK 0x200u
570 #define AIPS_PACRA_WP5_SHIFT 9
571 #define AIPS_PACRA_SP5_MASK 0x400u
572 #define AIPS_PACRA_SP5_SHIFT 10
573 #define AIPS_PACRA_TP4_MASK 0x1000u
574 #define AIPS_PACRA_TP4_SHIFT 12
575 #define AIPS_PACRA_WP4_MASK 0x2000u
576 #define AIPS_PACRA_WP4_SHIFT 13
577 #define AIPS_PACRA_SP4_MASK 0x4000u
578 #define AIPS_PACRA_SP4_SHIFT 14
579 #define AIPS_PACRA_TP3_MASK 0x10000u
580 #define AIPS_PACRA_TP3_SHIFT 16
581 #define AIPS_PACRA_WP3_MASK 0x20000u
582 #define AIPS_PACRA_WP3_SHIFT 17
583 #define AIPS_PACRA_SP3_MASK 0x40000u
584 #define AIPS_PACRA_SP3_SHIFT 18
585 #define AIPS_PACRA_TP2_MASK 0x100000u
586 #define AIPS_PACRA_TP2_SHIFT 20
587 #define AIPS_PACRA_WP2_MASK 0x200000u
588 #define AIPS_PACRA_WP2_SHIFT 21
589 #define AIPS_PACRA_SP2_MASK 0x400000u
590 #define AIPS_PACRA_SP2_SHIFT 22
591 #define AIPS_PACRA_TP1_MASK 0x1000000u
592 #define AIPS_PACRA_TP1_SHIFT 24
593 #define AIPS_PACRA_WP1_MASK 0x2000000u
594 #define AIPS_PACRA_WP1_SHIFT 25
595 #define AIPS_PACRA_SP1_MASK 0x4000000u
596 #define AIPS_PACRA_SP1_SHIFT 26
597 #define AIPS_PACRA_TP0_MASK 0x10000000u
598 #define AIPS_PACRA_TP0_SHIFT 28
599 #define AIPS_PACRA_WP0_MASK 0x20000000u
600 #define AIPS_PACRA_WP0_SHIFT 29
601 #define AIPS_PACRA_SP0_MASK 0x40000000u
602 #define AIPS_PACRA_SP0_SHIFT 30
603 /* PACRB Bit Fields */
604 #define AIPS_PACRB_TP7_MASK 0x1u
605 #define AIPS_PACRB_TP7_SHIFT 0
606 #define AIPS_PACRB_WP7_MASK 0x2u
607 #define AIPS_PACRB_WP7_SHIFT 1
608 #define AIPS_PACRB_SP7_MASK 0x4u
609 #define AIPS_PACRB_SP7_SHIFT 2
610 #define AIPS_PACRB_TP6_MASK 0x10u
611 #define AIPS_PACRB_TP6_SHIFT 4
612 #define AIPS_PACRB_WP6_MASK 0x20u
613 #define AIPS_PACRB_WP6_SHIFT 5
614 #define AIPS_PACRB_SP6_MASK 0x40u
615 #define AIPS_PACRB_SP6_SHIFT 6
616 #define AIPS_PACRB_TP5_MASK 0x100u
617 #define AIPS_PACRB_TP5_SHIFT 8
618 #define AIPS_PACRB_WP5_MASK 0x200u
619 #define AIPS_PACRB_WP5_SHIFT 9
620 #define AIPS_PACRB_SP5_MASK 0x400u
621 #define AIPS_PACRB_SP5_SHIFT 10
622 #define AIPS_PACRB_TP4_MASK 0x1000u
623 #define AIPS_PACRB_TP4_SHIFT 12
624 #define AIPS_PACRB_WP4_MASK 0x2000u
625 #define AIPS_PACRB_WP4_SHIFT 13
626 #define AIPS_PACRB_SP4_MASK 0x4000u
627 #define AIPS_PACRB_SP4_SHIFT 14
628 #define AIPS_PACRB_TP3_MASK 0x10000u
629 #define AIPS_PACRB_TP3_SHIFT 16
630 #define AIPS_PACRB_WP3_MASK 0x20000u
631 #define AIPS_PACRB_WP3_SHIFT 17
632 #define AIPS_PACRB_SP3_MASK 0x40000u
633 #define AIPS_PACRB_SP3_SHIFT 18
634 #define AIPS_PACRB_TP2_MASK 0x100000u
635 #define AIPS_PACRB_TP2_SHIFT 20
636 #define AIPS_PACRB_WP2_MASK 0x200000u
637 #define AIPS_PACRB_WP2_SHIFT 21
638 #define AIPS_PACRB_SP2_MASK 0x400000u
639 #define AIPS_PACRB_SP2_SHIFT 22
640 #define AIPS_PACRB_TP1_MASK 0x1000000u
641 #define AIPS_PACRB_TP1_SHIFT 24
642 #define AIPS_PACRB_WP1_MASK 0x2000000u
643 #define AIPS_PACRB_WP1_SHIFT 25
644 #define AIPS_PACRB_SP1_MASK 0x4000000u
645 #define AIPS_PACRB_SP1_SHIFT 26
646 #define AIPS_PACRB_TP0_MASK 0x10000000u
647 #define AIPS_PACRB_TP0_SHIFT 28
648 #define AIPS_PACRB_WP0_MASK 0x20000000u
649 #define AIPS_PACRB_WP0_SHIFT 29
650 #define AIPS_PACRB_SP0_MASK 0x40000000u
651 #define AIPS_PACRB_SP0_SHIFT 30
652 /* PACRC Bit Fields */
653 #define AIPS_PACRC_TP7_MASK 0x1u
654 #define AIPS_PACRC_TP7_SHIFT 0
655 #define AIPS_PACRC_WP7_MASK 0x2u
656 #define AIPS_PACRC_WP7_SHIFT 1
657 #define AIPS_PACRC_SP7_MASK 0x4u
658 #define AIPS_PACRC_SP7_SHIFT 2
659 #define AIPS_PACRC_TP6_MASK 0x10u
660 #define AIPS_PACRC_TP6_SHIFT 4
661 #define AIPS_PACRC_WP6_MASK 0x20u
662 #define AIPS_PACRC_WP6_SHIFT 5
663 #define AIPS_PACRC_SP6_MASK 0x40u
664 #define AIPS_PACRC_SP6_SHIFT 6
665 #define AIPS_PACRC_TP5_MASK 0x100u
666 #define AIPS_PACRC_TP5_SHIFT 8
667 #define AIPS_PACRC_WP5_MASK 0x200u
668 #define AIPS_PACRC_WP5_SHIFT 9
669 #define AIPS_PACRC_SP5_MASK 0x400u
670 #define AIPS_PACRC_SP5_SHIFT 10
671 #define AIPS_PACRC_TP4_MASK 0x1000u
672 #define AIPS_PACRC_TP4_SHIFT 12
673 #define AIPS_PACRC_WP4_MASK 0x2000u
674 #define AIPS_PACRC_WP4_SHIFT 13
675 #define AIPS_PACRC_SP4_MASK 0x4000u
676 #define AIPS_PACRC_SP4_SHIFT 14
677 #define AIPS_PACRC_TP3_MASK 0x10000u
678 #define AIPS_PACRC_TP3_SHIFT 16
679 #define AIPS_PACRC_WP3_MASK 0x20000u
680 #define AIPS_PACRC_WP3_SHIFT 17
681 #define AIPS_PACRC_SP3_MASK 0x40000u
682 #define AIPS_PACRC_SP3_SHIFT 18
683 #define AIPS_PACRC_TP2_MASK 0x100000u
684 #define AIPS_PACRC_TP2_SHIFT 20
685 #define AIPS_PACRC_WP2_MASK 0x200000u
686 #define AIPS_PACRC_WP2_SHIFT 21
687 #define AIPS_PACRC_SP2_MASK 0x400000u
688 #define AIPS_PACRC_SP2_SHIFT 22
689 #define AIPS_PACRC_TP1_MASK 0x1000000u
690 #define AIPS_PACRC_TP1_SHIFT 24
691 #define AIPS_PACRC_WP1_MASK 0x2000000u
692 #define AIPS_PACRC_WP1_SHIFT 25
693 #define AIPS_PACRC_SP1_MASK 0x4000000u
694 #define AIPS_PACRC_SP1_SHIFT 26
695 #define AIPS_PACRC_TP0_MASK 0x10000000u
696 #define AIPS_PACRC_TP0_SHIFT 28
697 #define AIPS_PACRC_WP0_MASK 0x20000000u
698 #define AIPS_PACRC_WP0_SHIFT 29
699 #define AIPS_PACRC_SP0_MASK 0x40000000u
700 #define AIPS_PACRC_SP0_SHIFT 30
701 /* PACRD Bit Fields */
702 #define AIPS_PACRD_TP7_MASK 0x1u
703 #define AIPS_PACRD_TP7_SHIFT 0
704 #define AIPS_PACRD_WP7_MASK 0x2u
705 #define AIPS_PACRD_WP7_SHIFT 1
706 #define AIPS_PACRD_SP7_MASK 0x4u
707 #define AIPS_PACRD_SP7_SHIFT 2
708 #define AIPS_PACRD_TP6_MASK 0x10u
709 #define AIPS_PACRD_TP6_SHIFT 4
710 #define AIPS_PACRD_WP6_MASK 0x20u
711 #define AIPS_PACRD_WP6_SHIFT 5
712 #define AIPS_PACRD_SP6_MASK 0x40u
713 #define AIPS_PACRD_SP6_SHIFT 6
714 #define AIPS_PACRD_TP5_MASK 0x100u
715 #define AIPS_PACRD_TP5_SHIFT 8
716 #define AIPS_PACRD_WP5_MASK 0x200u
717 #define AIPS_PACRD_WP5_SHIFT 9
718 #define AIPS_PACRD_SP5_MASK 0x400u
719 #define AIPS_PACRD_SP5_SHIFT 10
720 #define AIPS_PACRD_TP4_MASK 0x1000u
721 #define AIPS_PACRD_TP4_SHIFT 12
722 #define AIPS_PACRD_WP4_MASK 0x2000u
723 #define AIPS_PACRD_WP4_SHIFT 13
724 #define AIPS_PACRD_SP4_MASK 0x4000u
725 #define AIPS_PACRD_SP4_SHIFT 14
726 #define AIPS_PACRD_TP3_MASK 0x10000u
727 #define AIPS_PACRD_TP3_SHIFT 16
728 #define AIPS_PACRD_WP3_MASK 0x20000u
729 #define AIPS_PACRD_WP3_SHIFT 17
730 #define AIPS_PACRD_SP3_MASK 0x40000u
731 #define AIPS_PACRD_SP3_SHIFT 18
732 #define AIPS_PACRD_TP2_MASK 0x100000u
733 #define AIPS_PACRD_TP2_SHIFT 20
734 #define AIPS_PACRD_WP2_MASK 0x200000u
735 #define AIPS_PACRD_WP2_SHIFT 21
736 #define AIPS_PACRD_SP2_MASK 0x400000u
737 #define AIPS_PACRD_SP2_SHIFT 22
738 #define AIPS_PACRD_TP1_MASK 0x1000000u
739 #define AIPS_PACRD_TP1_SHIFT 24
740 #define AIPS_PACRD_WP1_MASK 0x2000000u
741 #define AIPS_PACRD_WP1_SHIFT 25
742 #define AIPS_PACRD_SP1_MASK 0x4000000u
743 #define AIPS_PACRD_SP1_SHIFT 26
744 #define AIPS_PACRD_TP0_MASK 0x10000000u
745 #define AIPS_PACRD_TP0_SHIFT 28
746 #define AIPS_PACRD_WP0_MASK 0x20000000u
747 #define AIPS_PACRD_WP0_SHIFT 29
748 #define AIPS_PACRD_SP0_MASK 0x40000000u
749 #define AIPS_PACRD_SP0_SHIFT 30
750 /* PACRE Bit Fields */
751 #define AIPS_PACRE_TP7_MASK 0x1u
752 #define AIPS_PACRE_TP7_SHIFT 0
753 #define AIPS_PACRE_WP7_MASK 0x2u
754 #define AIPS_PACRE_WP7_SHIFT 1
755 #define AIPS_PACRE_SP7_MASK 0x4u
756 #define AIPS_PACRE_SP7_SHIFT 2
757 #define AIPS_PACRE_TP6_MASK 0x10u
758 #define AIPS_PACRE_TP6_SHIFT 4
759 #define AIPS_PACRE_WP6_MASK 0x20u
760 #define AIPS_PACRE_WP6_SHIFT 5
761 #define AIPS_PACRE_SP6_MASK 0x40u
762 #define AIPS_PACRE_SP6_SHIFT 6
763 #define AIPS_PACRE_TP5_MASK 0x100u
764 #define AIPS_PACRE_TP5_SHIFT 8
765 #define AIPS_PACRE_WP5_MASK 0x200u
766 #define AIPS_PACRE_WP5_SHIFT 9
767 #define AIPS_PACRE_SP5_MASK 0x400u
768 #define AIPS_PACRE_SP5_SHIFT 10
769 #define AIPS_PACRE_TP4_MASK 0x1000u
770 #define AIPS_PACRE_TP4_SHIFT 12
771 #define AIPS_PACRE_WP4_MASK 0x2000u
772 #define AIPS_PACRE_WP4_SHIFT 13
773 #define AIPS_PACRE_SP4_MASK 0x4000u
774 #define AIPS_PACRE_SP4_SHIFT 14
775 #define AIPS_PACRE_TP3_MASK 0x10000u
776 #define AIPS_PACRE_TP3_SHIFT 16
777 #define AIPS_PACRE_WP3_MASK 0x20000u
778 #define AIPS_PACRE_WP3_SHIFT 17
779 #define AIPS_PACRE_SP3_MASK 0x40000u
780 #define AIPS_PACRE_SP3_SHIFT 18
781 #define AIPS_PACRE_TP2_MASK 0x100000u
782 #define AIPS_PACRE_TP2_SHIFT 20
783 #define AIPS_PACRE_WP2_MASK 0x200000u
784 #define AIPS_PACRE_WP2_SHIFT 21
785 #define AIPS_PACRE_SP2_MASK 0x400000u
786 #define AIPS_PACRE_SP2_SHIFT 22
787 #define AIPS_PACRE_TP1_MASK 0x1000000u
788 #define AIPS_PACRE_TP1_SHIFT 24
789 #define AIPS_PACRE_WP1_MASK 0x2000000u
790 #define AIPS_PACRE_WP1_SHIFT 25
791 #define AIPS_PACRE_SP1_MASK 0x4000000u
792 #define AIPS_PACRE_SP1_SHIFT 26
793 #define AIPS_PACRE_TP0_MASK 0x10000000u
794 #define AIPS_PACRE_TP0_SHIFT 28
795 #define AIPS_PACRE_WP0_MASK 0x20000000u
796 #define AIPS_PACRE_WP0_SHIFT 29
797 #define AIPS_PACRE_SP0_MASK 0x40000000u
798 #define AIPS_PACRE_SP0_SHIFT 30
799 /* PACRF Bit Fields */
800 #define AIPS_PACRF_TP7_MASK 0x1u
801 #define AIPS_PACRF_TP7_SHIFT 0
802 #define AIPS_PACRF_WP7_MASK 0x2u
803 #define AIPS_PACRF_WP7_SHIFT 1
804 #define AIPS_PACRF_SP7_MASK 0x4u
805 #define AIPS_PACRF_SP7_SHIFT 2
806 #define AIPS_PACRF_TP6_MASK 0x10u
807 #define AIPS_PACRF_TP6_SHIFT 4
808 #define AIPS_PACRF_WP6_MASK 0x20u
809 #define AIPS_PACRF_WP6_SHIFT 5
810 #define AIPS_PACRF_SP6_MASK 0x40u
811 #define AIPS_PACRF_SP6_SHIFT 6
812 #define AIPS_PACRF_TP5_MASK 0x100u
813 #define AIPS_PACRF_TP5_SHIFT 8
814 #define AIPS_PACRF_WP5_MASK 0x200u
815 #define AIPS_PACRF_WP5_SHIFT 9
816 #define AIPS_PACRF_SP5_MASK 0x400u
817 #define AIPS_PACRF_SP5_SHIFT 10
818 #define AIPS_PACRF_TP4_MASK 0x1000u
819 #define AIPS_PACRF_TP4_SHIFT 12
820 #define AIPS_PACRF_WP4_MASK 0x2000u
821 #define AIPS_PACRF_WP4_SHIFT 13
822 #define AIPS_PACRF_SP4_MASK 0x4000u
823 #define AIPS_PACRF_SP4_SHIFT 14
824 #define AIPS_PACRF_TP3_MASK 0x10000u
825 #define AIPS_PACRF_TP3_SHIFT 16
826 #define AIPS_PACRF_WP3_MASK 0x20000u
827 #define AIPS_PACRF_WP3_SHIFT 17
828 #define AIPS_PACRF_SP3_MASK 0x40000u
829 #define AIPS_PACRF_SP3_SHIFT 18
830 #define AIPS_PACRF_TP2_MASK 0x100000u
831 #define AIPS_PACRF_TP2_SHIFT 20
832 #define AIPS_PACRF_WP2_MASK 0x200000u
833 #define AIPS_PACRF_WP2_SHIFT 21
834 #define AIPS_PACRF_SP2_MASK 0x400000u
835 #define AIPS_PACRF_SP2_SHIFT 22
836 #define AIPS_PACRF_TP1_MASK 0x1000000u
837 #define AIPS_PACRF_TP1_SHIFT 24
838 #define AIPS_PACRF_WP1_MASK 0x2000000u
839 #define AIPS_PACRF_WP1_SHIFT 25
840 #define AIPS_PACRF_SP1_MASK 0x4000000u
841 #define AIPS_PACRF_SP1_SHIFT 26
842 #define AIPS_PACRF_TP0_MASK 0x10000000u
843 #define AIPS_PACRF_TP0_SHIFT 28
844 #define AIPS_PACRF_WP0_MASK 0x20000000u
845 #define AIPS_PACRF_WP0_SHIFT 29
846 #define AIPS_PACRF_SP0_MASK 0x40000000u
847 #define AIPS_PACRF_SP0_SHIFT 30
848 /* PACRG Bit Fields */
849 #define AIPS_PACRG_TP7_MASK 0x1u
850 #define AIPS_PACRG_TP7_SHIFT 0
851 #define AIPS_PACRG_WP7_MASK 0x2u
852 #define AIPS_PACRG_WP7_SHIFT 1
853 #define AIPS_PACRG_SP7_MASK 0x4u
854 #define AIPS_PACRG_SP7_SHIFT 2
855 #define AIPS_PACRG_TP6_MASK 0x10u
856 #define AIPS_PACRG_TP6_SHIFT 4
857 #define AIPS_PACRG_WP6_MASK 0x20u
858 #define AIPS_PACRG_WP6_SHIFT 5
859 #define AIPS_PACRG_SP6_MASK 0x40u
860 #define AIPS_PACRG_SP6_SHIFT 6
861 #define AIPS_PACRG_TP5_MASK 0x100u
862 #define AIPS_PACRG_TP5_SHIFT 8
863 #define AIPS_PACRG_WP5_MASK 0x200u
864 #define AIPS_PACRG_WP5_SHIFT 9
865 #define AIPS_PACRG_SP5_MASK 0x400u
866 #define AIPS_PACRG_SP5_SHIFT 10
867 #define AIPS_PACRG_TP4_MASK 0x1000u
868 #define AIPS_PACRG_TP4_SHIFT 12
869 #define AIPS_PACRG_WP4_MASK 0x2000u
870 #define AIPS_PACRG_WP4_SHIFT 13
871 #define AIPS_PACRG_SP4_MASK 0x4000u
872 #define AIPS_PACRG_SP4_SHIFT 14
873 #define AIPS_PACRG_TP3_MASK 0x10000u
874 #define AIPS_PACRG_TP3_SHIFT 16
875 #define AIPS_PACRG_WP3_MASK 0x20000u
876 #define AIPS_PACRG_WP3_SHIFT 17
877 #define AIPS_PACRG_SP3_MASK 0x40000u
878 #define AIPS_PACRG_SP3_SHIFT 18
879 #define AIPS_PACRG_TP2_MASK 0x100000u
880 #define AIPS_PACRG_TP2_SHIFT 20
881 #define AIPS_PACRG_WP2_MASK 0x200000u
882 #define AIPS_PACRG_WP2_SHIFT 21
883 #define AIPS_PACRG_SP2_MASK 0x400000u
884 #define AIPS_PACRG_SP2_SHIFT 22
885 #define AIPS_PACRG_TP1_MASK 0x1000000u
886 #define AIPS_PACRG_TP1_SHIFT 24
887 #define AIPS_PACRG_WP1_MASK 0x2000000u
888 #define AIPS_PACRG_WP1_SHIFT 25
889 #define AIPS_PACRG_SP1_MASK 0x4000000u
890 #define AIPS_PACRG_SP1_SHIFT 26
891 #define AIPS_PACRG_TP0_MASK 0x10000000u
892 #define AIPS_PACRG_TP0_SHIFT 28
893 #define AIPS_PACRG_WP0_MASK 0x20000000u
894 #define AIPS_PACRG_WP0_SHIFT 29
895 #define AIPS_PACRG_SP0_MASK 0x40000000u
896 #define AIPS_PACRG_SP0_SHIFT 30
897 /* PACRH Bit Fields */
898 #define AIPS_PACRH_TP7_MASK 0x1u
899 #define AIPS_PACRH_TP7_SHIFT 0
900 #define AIPS_PACRH_WP7_MASK 0x2u
901 #define AIPS_PACRH_WP7_SHIFT 1
902 #define AIPS_PACRH_SP7_MASK 0x4u
903 #define AIPS_PACRH_SP7_SHIFT 2
904 #define AIPS_PACRH_TP6_MASK 0x10u
905 #define AIPS_PACRH_TP6_SHIFT 4
906 #define AIPS_PACRH_WP6_MASK 0x20u
907 #define AIPS_PACRH_WP6_SHIFT 5
908 #define AIPS_PACRH_SP6_MASK 0x40u
909 #define AIPS_PACRH_SP6_SHIFT 6
910 #define AIPS_PACRH_TP5_MASK 0x100u
911 #define AIPS_PACRH_TP5_SHIFT 8
912 #define AIPS_PACRH_WP5_MASK 0x200u
913 #define AIPS_PACRH_WP5_SHIFT 9
914 #define AIPS_PACRH_SP5_MASK 0x400u
915 #define AIPS_PACRH_SP5_SHIFT 10
916 #define AIPS_PACRH_TP4_MASK 0x1000u
917 #define AIPS_PACRH_TP4_SHIFT 12
918 #define AIPS_PACRH_WP4_MASK 0x2000u
919 #define AIPS_PACRH_WP4_SHIFT 13
920 #define AIPS_PACRH_SP4_MASK 0x4000u
921 #define AIPS_PACRH_SP4_SHIFT 14
922 #define AIPS_PACRH_TP3_MASK 0x10000u
923 #define AIPS_PACRH_TP3_SHIFT 16
924 #define AIPS_PACRH_WP3_MASK 0x20000u
925 #define AIPS_PACRH_WP3_SHIFT 17
926 #define AIPS_PACRH_SP3_MASK 0x40000u
927 #define AIPS_PACRH_SP3_SHIFT 18
928 #define AIPS_PACRH_TP2_MASK 0x100000u
929 #define AIPS_PACRH_TP2_SHIFT 20
930 #define AIPS_PACRH_WP2_MASK 0x200000u
931 #define AIPS_PACRH_WP2_SHIFT 21
932 #define AIPS_PACRH_SP2_MASK 0x400000u
933 #define AIPS_PACRH_SP2_SHIFT 22
934 #define AIPS_PACRH_TP1_MASK 0x1000000u
935 #define AIPS_PACRH_TP1_SHIFT 24
936 #define AIPS_PACRH_WP1_MASK 0x2000000u
937 #define AIPS_PACRH_WP1_SHIFT 25
938 #define AIPS_PACRH_SP1_MASK 0x4000000u
939 #define AIPS_PACRH_SP1_SHIFT 26
940 #define AIPS_PACRH_TP0_MASK 0x10000000u
941 #define AIPS_PACRH_TP0_SHIFT 28
942 #define AIPS_PACRH_WP0_MASK 0x20000000u
943 #define AIPS_PACRH_WP0_SHIFT 29
944 #define AIPS_PACRH_SP0_MASK 0x40000000u
945 #define AIPS_PACRH_SP0_SHIFT 30
946 /* PACRI Bit Fields */
947 #define AIPS_PACRI_TP7_MASK 0x1u
948 #define AIPS_PACRI_TP7_SHIFT 0
949 #define AIPS_PACRI_WP7_MASK 0x2u
950 #define AIPS_PACRI_WP7_SHIFT 1
951 #define AIPS_PACRI_SP7_MASK 0x4u
952 #define AIPS_PACRI_SP7_SHIFT 2
953 #define AIPS_PACRI_TP6_MASK 0x10u
954 #define AIPS_PACRI_TP6_SHIFT 4
955 #define AIPS_PACRI_WP6_MASK 0x20u
956 #define AIPS_PACRI_WP6_SHIFT 5
957 #define AIPS_PACRI_SP6_MASK 0x40u
958 #define AIPS_PACRI_SP6_SHIFT 6
959 #define AIPS_PACRI_TP5_MASK 0x100u
960 #define AIPS_PACRI_TP5_SHIFT 8
961 #define AIPS_PACRI_WP5_MASK 0x200u
962 #define AIPS_PACRI_WP5_SHIFT 9
963 #define AIPS_PACRI_SP5_MASK 0x400u
964 #define AIPS_PACRI_SP5_SHIFT 10
965 #define AIPS_PACRI_TP4_MASK 0x1000u
966 #define AIPS_PACRI_TP4_SHIFT 12
967 #define AIPS_PACRI_WP4_MASK 0x2000u
968 #define AIPS_PACRI_WP4_SHIFT 13
969 #define AIPS_PACRI_SP4_MASK 0x4000u
970 #define AIPS_PACRI_SP4_SHIFT 14
971 #define AIPS_PACRI_TP3_MASK 0x10000u
972 #define AIPS_PACRI_TP3_SHIFT 16
973 #define AIPS_PACRI_WP3_MASK 0x20000u
974 #define AIPS_PACRI_WP3_SHIFT 17
975 #define AIPS_PACRI_SP3_MASK 0x40000u
976 #define AIPS_PACRI_SP3_SHIFT 18
977 #define AIPS_PACRI_TP2_MASK 0x100000u
978 #define AIPS_PACRI_TP2_SHIFT 20
979 #define AIPS_PACRI_WP2_MASK 0x200000u
980 #define AIPS_PACRI_WP2_SHIFT 21
981 #define AIPS_PACRI_SP2_MASK 0x400000u
982 #define AIPS_PACRI_SP2_SHIFT 22
983 #define AIPS_PACRI_TP1_MASK 0x1000000u
984 #define AIPS_PACRI_TP1_SHIFT 24
985 #define AIPS_PACRI_WP1_MASK 0x2000000u
986 #define AIPS_PACRI_WP1_SHIFT 25
987 #define AIPS_PACRI_SP1_MASK 0x4000000u
988 #define AIPS_PACRI_SP1_SHIFT 26
989 #define AIPS_PACRI_TP0_MASK 0x10000000u
990 #define AIPS_PACRI_TP0_SHIFT 28
991 #define AIPS_PACRI_WP0_MASK 0x20000000u
992 #define AIPS_PACRI_WP0_SHIFT 29
993 #define AIPS_PACRI_SP0_MASK 0x40000000u
994 #define AIPS_PACRI_SP0_SHIFT 30
995 /* PACRJ Bit Fields */
996 #define AIPS_PACRJ_TP7_MASK 0x1u
997 #define AIPS_PACRJ_TP7_SHIFT 0
998 #define AIPS_PACRJ_WP7_MASK 0x2u
999 #define AIPS_PACRJ_WP7_SHIFT 1
1000 #define AIPS_PACRJ_SP7_MASK 0x4u
1001 #define AIPS_PACRJ_SP7_SHIFT 2
1002 #define AIPS_PACRJ_TP6_MASK 0x10u
1003 #define AIPS_PACRJ_TP6_SHIFT 4
1004 #define AIPS_PACRJ_WP6_MASK 0x20u
1005 #define AIPS_PACRJ_WP6_SHIFT 5
1006 #define AIPS_PACRJ_SP6_MASK 0x40u
1007 #define AIPS_PACRJ_SP6_SHIFT 6
1008 #define AIPS_PACRJ_TP5_MASK 0x100u
1009 #define AIPS_PACRJ_TP5_SHIFT 8
1010 #define AIPS_PACRJ_WP5_MASK 0x200u
1011 #define AIPS_PACRJ_WP5_SHIFT 9
1012 #define AIPS_PACRJ_SP5_MASK 0x400u
1013 #define AIPS_PACRJ_SP5_SHIFT 10
1014 #define AIPS_PACRJ_TP4_MASK 0x1000u
1015 #define AIPS_PACRJ_TP4_SHIFT 12
1016 #define AIPS_PACRJ_WP4_MASK 0x2000u
1017 #define AIPS_PACRJ_WP4_SHIFT 13
1018 #define AIPS_PACRJ_SP4_MASK 0x4000u
1019 #define AIPS_PACRJ_SP4_SHIFT 14
1020 #define AIPS_PACRJ_TP3_MASK 0x10000u
1021 #define AIPS_PACRJ_TP3_SHIFT 16
1022 #define AIPS_PACRJ_WP3_MASK 0x20000u
1023 #define AIPS_PACRJ_WP3_SHIFT 17
1024 #define AIPS_PACRJ_SP3_MASK 0x40000u
1025 #define AIPS_PACRJ_SP3_SHIFT 18
1026 #define AIPS_PACRJ_TP2_MASK 0x100000u
1027 #define AIPS_PACRJ_TP2_SHIFT 20
1028 #define AIPS_PACRJ_WP2_MASK 0x200000u
1029 #define AIPS_PACRJ_WP2_SHIFT 21
1030 #define AIPS_PACRJ_SP2_MASK 0x400000u
1031 #define AIPS_PACRJ_SP2_SHIFT 22
1032 #define AIPS_PACRJ_TP1_MASK 0x1000000u
1033 #define AIPS_PACRJ_TP1_SHIFT 24
1034 #define AIPS_PACRJ_WP1_MASK 0x2000000u
1035 #define AIPS_PACRJ_WP1_SHIFT 25
1036 #define AIPS_PACRJ_SP1_MASK 0x4000000u
1037 #define AIPS_PACRJ_SP1_SHIFT 26
1038 #define AIPS_PACRJ_TP0_MASK 0x10000000u
1039 #define AIPS_PACRJ_TP0_SHIFT 28
1040 #define AIPS_PACRJ_WP0_MASK 0x20000000u
1041 #define AIPS_PACRJ_WP0_SHIFT 29
1042 #define AIPS_PACRJ_SP0_MASK 0x40000000u
1043 #define AIPS_PACRJ_SP0_SHIFT 30
1044 /* PACRK Bit Fields */
1045 #define AIPS_PACRK_TP7_MASK 0x1u
1046 #define AIPS_PACRK_TP7_SHIFT 0
1047 #define AIPS_PACRK_WP7_MASK 0x2u
1048 #define AIPS_PACRK_WP7_SHIFT 1
1049 #define AIPS_PACRK_SP7_MASK 0x4u
1050 #define AIPS_PACRK_SP7_SHIFT 2
1051 #define AIPS_PACRK_TP6_MASK 0x10u
1052 #define AIPS_PACRK_TP6_SHIFT 4
1053 #define AIPS_PACRK_WP6_MASK 0x20u
1054 #define AIPS_PACRK_WP6_SHIFT 5
1055 #define AIPS_PACRK_SP6_MASK 0x40u
1056 #define AIPS_PACRK_SP6_SHIFT 6
1057 #define AIPS_PACRK_TP5_MASK 0x100u
1058 #define AIPS_PACRK_TP5_SHIFT 8
1059 #define AIPS_PACRK_WP5_MASK 0x200u
1060 #define AIPS_PACRK_WP5_SHIFT 9
1061 #define AIPS_PACRK_SP5_MASK 0x400u
1062 #define AIPS_PACRK_SP5_SHIFT 10
1063 #define AIPS_PACRK_TP4_MASK 0x1000u
1064 #define AIPS_PACRK_TP4_SHIFT 12
1065 #define AIPS_PACRK_WP4_MASK 0x2000u
1066 #define AIPS_PACRK_WP4_SHIFT 13
1067 #define AIPS_PACRK_SP4_MASK 0x4000u
1068 #define AIPS_PACRK_SP4_SHIFT 14
1069 #define AIPS_PACRK_TP3_MASK 0x10000u
1070 #define AIPS_PACRK_TP3_SHIFT 16
1071 #define AIPS_PACRK_WP3_MASK 0x20000u
1072 #define AIPS_PACRK_WP3_SHIFT 17
1073 #define AIPS_PACRK_SP3_MASK 0x40000u
1074 #define AIPS_PACRK_SP3_SHIFT 18
1075 #define AIPS_PACRK_TP2_MASK 0x100000u
1076 #define AIPS_PACRK_TP2_SHIFT 20
1077 #define AIPS_PACRK_WP2_MASK 0x200000u
1078 #define AIPS_PACRK_WP2_SHIFT 21
1079 #define AIPS_PACRK_SP2_MASK 0x400000u
1080 #define AIPS_PACRK_SP2_SHIFT 22
1081 #define AIPS_PACRK_TP1_MASK 0x1000000u
1082 #define AIPS_PACRK_TP1_SHIFT 24
1083 #define AIPS_PACRK_WP1_MASK 0x2000000u
1084 #define AIPS_PACRK_WP1_SHIFT 25
1085 #define AIPS_PACRK_SP1_MASK 0x4000000u
1086 #define AIPS_PACRK_SP1_SHIFT 26
1087 #define AIPS_PACRK_TP0_MASK 0x10000000u
1088 #define AIPS_PACRK_TP0_SHIFT 28
1089 #define AIPS_PACRK_WP0_MASK 0x20000000u
1090 #define AIPS_PACRK_WP0_SHIFT 29
1091 #define AIPS_PACRK_SP0_MASK 0x40000000u
1092 #define AIPS_PACRK_SP0_SHIFT 30
1093 /* PACRL Bit Fields */
1094 #define AIPS_PACRL_TP7_MASK 0x1u
1095 #define AIPS_PACRL_TP7_SHIFT 0
1096 #define AIPS_PACRL_WP7_MASK 0x2u
1097 #define AIPS_PACRL_WP7_SHIFT 1
1098 #define AIPS_PACRL_SP7_MASK 0x4u
1099 #define AIPS_PACRL_SP7_SHIFT 2
1100 #define AIPS_PACRL_TP6_MASK 0x10u
1101 #define AIPS_PACRL_TP6_SHIFT 4
1102 #define AIPS_PACRL_WP6_MASK 0x20u
1103 #define AIPS_PACRL_WP6_SHIFT 5
1104 #define AIPS_PACRL_SP6_MASK 0x40u
1105 #define AIPS_PACRL_SP6_SHIFT 6
1106 #define AIPS_PACRL_TP5_MASK 0x100u
1107 #define AIPS_PACRL_TP5_SHIFT 8
1108 #define AIPS_PACRL_WP5_MASK 0x200u
1109 #define AIPS_PACRL_WP5_SHIFT 9
1110 #define AIPS_PACRL_SP5_MASK 0x400u
1111 #define AIPS_PACRL_SP5_SHIFT 10
1112 #define AIPS_PACRL_TP4_MASK 0x1000u
1113 #define AIPS_PACRL_TP4_SHIFT 12
1114 #define AIPS_PACRL_WP4_MASK 0x2000u
1115 #define AIPS_PACRL_WP4_SHIFT 13
1116 #define AIPS_PACRL_SP4_MASK 0x4000u
1117 #define AIPS_PACRL_SP4_SHIFT 14
1118 #define AIPS_PACRL_TP3_MASK 0x10000u
1119 #define AIPS_PACRL_TP3_SHIFT 16
1120 #define AIPS_PACRL_WP3_MASK 0x20000u
1121 #define AIPS_PACRL_WP3_SHIFT 17
1122 #define AIPS_PACRL_SP3_MASK 0x40000u
1123 #define AIPS_PACRL_SP3_SHIFT 18
1124 #define AIPS_PACRL_TP2_MASK 0x100000u
1125 #define AIPS_PACRL_TP2_SHIFT 20
1126 #define AIPS_PACRL_WP2_MASK 0x200000u
1127 #define AIPS_PACRL_WP2_SHIFT 21
1128 #define AIPS_PACRL_SP2_MASK 0x400000u
1129 #define AIPS_PACRL_SP2_SHIFT 22
1130 #define AIPS_PACRL_TP1_MASK 0x1000000u
1131 #define AIPS_PACRL_TP1_SHIFT 24
1132 #define AIPS_PACRL_WP1_MASK 0x2000000u
1133 #define AIPS_PACRL_WP1_SHIFT 25
1134 #define AIPS_PACRL_SP1_MASK 0x4000000u
1135 #define AIPS_PACRL_SP1_SHIFT 26
1136 #define AIPS_PACRL_TP0_MASK 0x10000000u
1137 #define AIPS_PACRL_TP0_SHIFT 28
1138 #define AIPS_PACRL_WP0_MASK 0x20000000u
1139 #define AIPS_PACRL_WP0_SHIFT 29
1140 #define AIPS_PACRL_SP0_MASK 0x40000000u
1141 #define AIPS_PACRL_SP0_SHIFT 30
1142 /* PACRM Bit Fields */
1143 #define AIPS_PACRM_TP7_MASK 0x1u
1144 #define AIPS_PACRM_TP7_SHIFT 0
1145 #define AIPS_PACRM_WP7_MASK 0x2u
1146 #define AIPS_PACRM_WP7_SHIFT 1
1147 #define AIPS_PACRM_SP7_MASK 0x4u
1148 #define AIPS_PACRM_SP7_SHIFT 2
1149 #define AIPS_PACRM_TP6_MASK 0x10u
1150 #define AIPS_PACRM_TP6_SHIFT 4
1151 #define AIPS_PACRM_WP6_MASK 0x20u
1152 #define AIPS_PACRM_WP6_SHIFT 5
1153 #define AIPS_PACRM_SP6_MASK 0x40u
1154 #define AIPS_PACRM_SP6_SHIFT 6
1155 #define AIPS_PACRM_TP5_MASK 0x100u
1156 #define AIPS_PACRM_TP5_SHIFT 8
1157 #define AIPS_PACRM_WP5_MASK 0x200u
1158 #define AIPS_PACRM_WP5_SHIFT 9
1159 #define AIPS_PACRM_SP5_MASK 0x400u
1160 #define AIPS_PACRM_SP5_SHIFT 10
1161 #define AIPS_PACRM_TP4_MASK 0x1000u
1162 #define AIPS_PACRM_TP4_SHIFT 12
1163 #define AIPS_PACRM_WP4_MASK 0x2000u
1164 #define AIPS_PACRM_WP4_SHIFT 13
1165 #define AIPS_PACRM_SP4_MASK 0x4000u
1166 #define AIPS_PACRM_SP4_SHIFT 14
1167 #define AIPS_PACRM_TP3_MASK 0x10000u
1168 #define AIPS_PACRM_TP3_SHIFT 16
1169 #define AIPS_PACRM_WP3_MASK 0x20000u
1170 #define AIPS_PACRM_WP3_SHIFT 17
1171 #define AIPS_PACRM_SP3_MASK 0x40000u
1172 #define AIPS_PACRM_SP3_SHIFT 18
1173 #define AIPS_PACRM_TP2_MASK 0x100000u
1174 #define AIPS_PACRM_TP2_SHIFT 20
1175 #define AIPS_PACRM_WP2_MASK 0x200000u
1176 #define AIPS_PACRM_WP2_SHIFT 21
1177 #define AIPS_PACRM_SP2_MASK 0x400000u
1178 #define AIPS_PACRM_SP2_SHIFT 22
1179 #define AIPS_PACRM_TP1_MASK 0x1000000u
1180 #define AIPS_PACRM_TP1_SHIFT 24
1181 #define AIPS_PACRM_WP1_MASK 0x2000000u
1182 #define AIPS_PACRM_WP1_SHIFT 25
1183 #define AIPS_PACRM_SP1_MASK 0x4000000u
1184 #define AIPS_PACRM_SP1_SHIFT 26
1185 #define AIPS_PACRM_TP0_MASK 0x10000000u
1186 #define AIPS_PACRM_TP0_SHIFT 28
1187 #define AIPS_PACRM_WP0_MASK 0x20000000u
1188 #define AIPS_PACRM_WP0_SHIFT 29
1189 #define AIPS_PACRM_SP0_MASK 0x40000000u
1190 #define AIPS_PACRM_SP0_SHIFT 30
1191 /* PACRN Bit Fields */
1192 #define AIPS_PACRN_TP7_MASK 0x1u
1193 #define AIPS_PACRN_TP7_SHIFT 0
1194 #define AIPS_PACRN_WP7_MASK 0x2u
1195 #define AIPS_PACRN_WP7_SHIFT 1
1196 #define AIPS_PACRN_SP7_MASK 0x4u
1197 #define AIPS_PACRN_SP7_SHIFT 2
1198 #define AIPS_PACRN_TP6_MASK 0x10u
1199 #define AIPS_PACRN_TP6_SHIFT 4
1200 #define AIPS_PACRN_WP6_MASK 0x20u
1201 #define AIPS_PACRN_WP6_SHIFT 5
1202 #define AIPS_PACRN_SP6_MASK 0x40u
1203 #define AIPS_PACRN_SP6_SHIFT 6
1204 #define AIPS_PACRN_TP5_MASK 0x100u
1205 #define AIPS_PACRN_TP5_SHIFT 8
1206 #define AIPS_PACRN_WP5_MASK 0x200u
1207 #define AIPS_PACRN_WP5_SHIFT 9
1208 #define AIPS_PACRN_SP5_MASK 0x400u
1209 #define AIPS_PACRN_SP5_SHIFT 10
1210 #define AIPS_PACRN_TP4_MASK 0x1000u
1211 #define AIPS_PACRN_TP4_SHIFT 12
1212 #define AIPS_PACRN_WP4_MASK 0x2000u
1213 #define AIPS_PACRN_WP4_SHIFT 13
1214 #define AIPS_PACRN_SP4_MASK 0x4000u
1215 #define AIPS_PACRN_SP4_SHIFT 14
1216 #define AIPS_PACRN_TP3_MASK 0x10000u
1217 #define AIPS_PACRN_TP3_SHIFT 16
1218 #define AIPS_PACRN_WP3_MASK 0x20000u
1219 #define AIPS_PACRN_WP3_SHIFT 17
1220 #define AIPS_PACRN_SP3_MASK 0x40000u
1221 #define AIPS_PACRN_SP3_SHIFT 18
1222 #define AIPS_PACRN_TP2_MASK 0x100000u
1223 #define AIPS_PACRN_TP2_SHIFT 20
1224 #define AIPS_PACRN_WP2_MASK 0x200000u
1225 #define AIPS_PACRN_WP2_SHIFT 21
1226 #define AIPS_PACRN_SP2_MASK 0x400000u
1227 #define AIPS_PACRN_SP2_SHIFT 22
1228 #define AIPS_PACRN_TP1_MASK 0x1000000u
1229 #define AIPS_PACRN_TP1_SHIFT 24
1230 #define AIPS_PACRN_WP1_MASK 0x2000000u
1231 #define AIPS_PACRN_WP1_SHIFT 25
1232 #define AIPS_PACRN_SP1_MASK 0x4000000u
1233 #define AIPS_PACRN_SP1_SHIFT 26
1234 #define AIPS_PACRN_TP0_MASK 0x10000000u
1235 #define AIPS_PACRN_TP0_SHIFT 28
1236 #define AIPS_PACRN_WP0_MASK 0x20000000u
1237 #define AIPS_PACRN_WP0_SHIFT 29
1238 #define AIPS_PACRN_SP0_MASK 0x40000000u
1239 #define AIPS_PACRN_SP0_SHIFT 30
1240 /* PACRO Bit Fields */
1241 #define AIPS_PACRO_TP7_MASK 0x1u
1242 #define AIPS_PACRO_TP7_SHIFT 0
1243 #define AIPS_PACRO_WP7_MASK 0x2u
1244 #define AIPS_PACRO_WP7_SHIFT 1
1245 #define AIPS_PACRO_SP7_MASK 0x4u
1246 #define AIPS_PACRO_SP7_SHIFT 2
1247 #define AIPS_PACRO_TP6_MASK 0x10u
1248 #define AIPS_PACRO_TP6_SHIFT 4
1249 #define AIPS_PACRO_WP6_MASK 0x20u
1250 #define AIPS_PACRO_WP6_SHIFT 5
1251 #define AIPS_PACRO_SP6_MASK 0x40u
1252 #define AIPS_PACRO_SP6_SHIFT 6
1253 #define AIPS_PACRO_TP5_MASK 0x100u
1254 #define AIPS_PACRO_TP5_SHIFT 8
1255 #define AIPS_PACRO_WP5_MASK 0x200u
1256 #define AIPS_PACRO_WP5_SHIFT 9
1257 #define AIPS_PACRO_SP5_MASK 0x400u
1258 #define AIPS_PACRO_SP5_SHIFT 10
1259 #define AIPS_PACRO_TP4_MASK 0x1000u
1260 #define AIPS_PACRO_TP4_SHIFT 12
1261 #define AIPS_PACRO_WP4_MASK 0x2000u
1262 #define AIPS_PACRO_WP4_SHIFT 13
1263 #define AIPS_PACRO_SP4_MASK 0x4000u
1264 #define AIPS_PACRO_SP4_SHIFT 14
1265 #define AIPS_PACRO_TP3_MASK 0x10000u
1266 #define AIPS_PACRO_TP3_SHIFT 16
1267 #define AIPS_PACRO_WP3_MASK 0x20000u
1268 #define AIPS_PACRO_WP3_SHIFT 17
1269 #define AIPS_PACRO_SP3_MASK 0x40000u
1270 #define AIPS_PACRO_SP3_SHIFT 18
1271 #define AIPS_PACRO_TP2_MASK 0x100000u
1272 #define AIPS_PACRO_TP2_SHIFT 20
1273 #define AIPS_PACRO_WP2_MASK 0x200000u
1274 #define AIPS_PACRO_WP2_SHIFT 21
1275 #define AIPS_PACRO_SP2_MASK 0x400000u
1276 #define AIPS_PACRO_SP2_SHIFT 22
1277 #define AIPS_PACRO_TP1_MASK 0x1000000u
1278 #define AIPS_PACRO_TP1_SHIFT 24
1279 #define AIPS_PACRO_WP1_MASK 0x2000000u
1280 #define AIPS_PACRO_WP1_SHIFT 25
1281 #define AIPS_PACRO_SP1_MASK 0x4000000u
1282 #define AIPS_PACRO_SP1_SHIFT 26
1283 #define AIPS_PACRO_TP0_MASK 0x10000000u
1284 #define AIPS_PACRO_TP0_SHIFT 28
1285 #define AIPS_PACRO_WP0_MASK 0x20000000u
1286 #define AIPS_PACRO_WP0_SHIFT 29
1287 #define AIPS_PACRO_SP0_MASK 0x40000000u
1288 #define AIPS_PACRO_SP0_SHIFT 30
1289 /* PACRP Bit Fields */
1290 #define AIPS_PACRP_TP7_MASK 0x1u
1291 #define AIPS_PACRP_TP7_SHIFT 0
1292 #define AIPS_PACRP_WP7_MASK 0x2u
1293 #define AIPS_PACRP_WP7_SHIFT 1
1294 #define AIPS_PACRP_SP7_MASK 0x4u
1295 #define AIPS_PACRP_SP7_SHIFT 2
1296 #define AIPS_PACRP_TP6_MASK 0x10u
1297 #define AIPS_PACRP_TP6_SHIFT 4
1298 #define AIPS_PACRP_WP6_MASK 0x20u
1299 #define AIPS_PACRP_WP6_SHIFT 5
1300 #define AIPS_PACRP_SP6_MASK 0x40u
1301 #define AIPS_PACRP_SP6_SHIFT 6
1302 #define AIPS_PACRP_TP5_MASK 0x100u
1303 #define AIPS_PACRP_TP5_SHIFT 8
1304 #define AIPS_PACRP_WP5_MASK 0x200u
1305 #define AIPS_PACRP_WP5_SHIFT 9
1306 #define AIPS_PACRP_SP5_MASK 0x400u
1307 #define AIPS_PACRP_SP5_SHIFT 10
1308 #define AIPS_PACRP_TP4_MASK 0x1000u
1309 #define AIPS_PACRP_TP4_SHIFT 12
1310 #define AIPS_PACRP_WP4_MASK 0x2000u
1311 #define AIPS_PACRP_WP4_SHIFT 13
1312 #define AIPS_PACRP_SP4_MASK 0x4000u
1313 #define AIPS_PACRP_SP4_SHIFT 14
1314 #define AIPS_PACRP_TP3_MASK 0x10000u
1315 #define AIPS_PACRP_TP3_SHIFT 16
1316 #define AIPS_PACRP_WP3_MASK 0x20000u
1317 #define AIPS_PACRP_WP3_SHIFT 17
1318 #define AIPS_PACRP_SP3_MASK 0x40000u
1319 #define AIPS_PACRP_SP3_SHIFT 18
1320 #define AIPS_PACRP_TP2_MASK 0x100000u
1321 #define AIPS_PACRP_TP2_SHIFT 20
1322 #define AIPS_PACRP_WP2_MASK 0x200000u
1323 #define AIPS_PACRP_WP2_SHIFT 21
1324 #define AIPS_PACRP_SP2_MASK 0x400000u
1325 #define AIPS_PACRP_SP2_SHIFT 22
1326 #define AIPS_PACRP_TP1_MASK 0x1000000u
1327 #define AIPS_PACRP_TP1_SHIFT 24
1328 #define AIPS_PACRP_WP1_MASK 0x2000000u
1329 #define AIPS_PACRP_WP1_SHIFT 25
1330 #define AIPS_PACRP_SP1_MASK 0x4000000u
1331 #define AIPS_PACRP_SP1_SHIFT 26
1332 #define AIPS_PACRP_TP0_MASK 0x10000000u
1333 #define AIPS_PACRP_TP0_SHIFT 28
1334 #define AIPS_PACRP_WP0_MASK 0x20000000u
1335 #define AIPS_PACRP_WP0_SHIFT 29
1336 #define AIPS_PACRP_SP0_MASK 0x40000000u
1337 #define AIPS_PACRP_SP0_SHIFT 30
1338 
1339 /**
1340  * @}
1341  */ /* end of group AIPS_Register_Masks */
1342 
1343 
1344 /* AIPS - Peripheral instance base addresses */
1345 /** Peripheral AIPS0 base address */
1346 #define AIPS0_BASE (0x40000000u)
1347 /** Peripheral AIPS0 base pointer */
1348 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
1349 /** Peripheral AIPS1 base address */
1350 #define AIPS1_BASE (0x40080000u)
1351 /** Peripheral AIPS1 base pointer */
1352 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
1353 
1354 /**
1355  * @}
1356  */ /* end of group AIPS_Peripheral_Access_Layer */
1357 
1358 
1359 /* ----------------------------------------------------------------------------
1360  -- AXBS Peripheral Access Layer
1361  ---------------------------------------------------------------------------- */
1362 
1363 /**
1364  * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
1365  * @{
1366  */
1367 
1368 /** AXBS - Register Layout Typedef */
1369 typedef struct {
1370  struct { /* offset: 0x0, array step: 0x100 */
1371  __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
1372  uint8_t RESERVED_0[12];
1373  __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
1374  uint8_t RESERVED_1[236];
1375  } SLAVE[5];
1376  uint8_t RESERVED_0[768];
1377  __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
1378  uint8_t RESERVED_1[252];
1379  __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
1380  uint8_t RESERVED_2[252];
1381  __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
1382  uint8_t RESERVED_3[252];
1383  __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
1384  uint8_t RESERVED_4[252];
1385  __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
1386  uint8_t RESERVED_5[252];
1387  __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
1388 } AXBS_Type;
1389 
1390 /* ----------------------------------------------------------------------------
1391  -- AXBS Register Masks
1392  ---------------------------------------------------------------------------- */
1393 
1394 /**
1395  * @addtogroup AXBS_Register_Masks AXBS Register Masks
1396  * @{
1397  */
1398 
1399 /* PRS Bit Fields */
1400 #define AXBS_PRS_M0_MASK 0x7u
1401 #define AXBS_PRS_M0_SHIFT 0
1402 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
1403 #define AXBS_PRS_M1_MASK 0x70u
1404 #define AXBS_PRS_M1_SHIFT 4
1405 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
1406 #define AXBS_PRS_M2_MASK 0x700u
1407 #define AXBS_PRS_M2_SHIFT 8
1408 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
1409 #define AXBS_PRS_M3_MASK 0x7000u
1410 #define AXBS_PRS_M3_SHIFT 12
1411 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
1412 #define AXBS_PRS_M4_MASK 0x70000u
1413 #define AXBS_PRS_M4_SHIFT 16
1414 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
1415 #define AXBS_PRS_M5_MASK 0x700000u
1416 #define AXBS_PRS_M5_SHIFT 20
1417 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
1418 /* CRS Bit Fields */
1419 #define AXBS_CRS_PARK_MASK 0x7u
1420 #define AXBS_CRS_PARK_SHIFT 0
1421 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
1422 #define AXBS_CRS_PCTL_MASK 0x30u
1423 #define AXBS_CRS_PCTL_SHIFT 4
1424 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
1425 #define AXBS_CRS_ARB_MASK 0x300u
1426 #define AXBS_CRS_ARB_SHIFT 8
1427 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
1428 #define AXBS_CRS_HLP_MASK 0x40000000u
1429 #define AXBS_CRS_HLP_SHIFT 30
1430 #define AXBS_CRS_RO_MASK 0x80000000u
1431 #define AXBS_CRS_RO_SHIFT 31
1432 /* MGPCR0 Bit Fields */
1433 #define AXBS_MGPCR0_AULB_MASK 0x7u
1434 #define AXBS_MGPCR0_AULB_SHIFT 0
1435 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
1436 /* MGPCR1 Bit Fields */
1437 #define AXBS_MGPCR1_AULB_MASK 0x7u
1438 #define AXBS_MGPCR1_AULB_SHIFT 0
1439 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
1440 /* MGPCR2 Bit Fields */
1441 #define AXBS_MGPCR2_AULB_MASK 0x7u
1442 #define AXBS_MGPCR2_AULB_SHIFT 0
1443 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
1444 /* MGPCR3 Bit Fields */
1445 #define AXBS_MGPCR3_AULB_MASK 0x7u
1446 #define AXBS_MGPCR3_AULB_SHIFT 0
1447 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
1448 /* MGPCR4 Bit Fields */
1449 #define AXBS_MGPCR4_AULB_MASK 0x7u
1450 #define AXBS_MGPCR4_AULB_SHIFT 0
1451 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
1452 /* MGPCR5 Bit Fields */
1453 #define AXBS_MGPCR5_AULB_MASK 0x7u
1454 #define AXBS_MGPCR5_AULB_SHIFT 0
1455 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
1456 
1457 /**
1458  * @}
1459  */ /* end of group AXBS_Register_Masks */
1460 
1461 
1462 /* AXBS - Peripheral instance base addresses */
1463 /** Peripheral AXBS base address */
1464 #define AXBS_BASE (0x40004000u)
1465 /** Peripheral AXBS base pointer */
1466 #define AXBS ((AXBS_Type *)AXBS_BASE)
1467 
1468 /**
1469  * @}
1470  */ /* end of group AXBS_Peripheral_Access_Layer */
1471 
1472 
1473 /* ----------------------------------------------------------------------------
1474  -- CAN Peripheral Access Layer
1475  ---------------------------------------------------------------------------- */
1476 
1477 /**
1478  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1479  * @{
1480  */
1481 
1482 /** CAN - Register Layout Typedef */
1483 typedef struct {
1484  __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
1485  __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
1486  __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
1487  uint8_t RESERVED_0[4];
1488  __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
1489  __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */
1490  __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */
1491  __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
1492  __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
1493  __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
1494  __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
1495  __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
1496  __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
1497  __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
1498  __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
1499  uint8_t RESERVED_1[8];
1500  __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
1501  __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
1502  __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
1503  uint8_t RESERVED_2[48];
1504  struct { /* offset: 0x80, array step: 0x10 */
1505  __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
1506  __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
1507  __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
1508  __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
1509  } MB[16];
1510  uint8_t RESERVED_3[1792];
1511  __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
1512 } CAN_Type;
1513 
1514 /* ----------------------------------------------------------------------------
1515  -- CAN Register Masks
1516  ---------------------------------------------------------------------------- */
1517 
1518 /**
1519  * @addtogroup CAN_Register_Masks CAN Register Masks
1520  * @{
1521  */
1522 
1523 /* MCR Bit Fields */
1524 #define CAN_MCR_MAXMB_MASK 0x7Fu
1525 #define CAN_MCR_MAXMB_SHIFT 0
1526 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
1527 #define CAN_MCR_IDAM_MASK 0x300u
1528 #define CAN_MCR_IDAM_SHIFT 8
1529 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
1530 #define CAN_MCR_AEN_MASK 0x1000u
1531 #define CAN_MCR_AEN_SHIFT 12
1532 #define CAN_MCR_LPRIOEN_MASK 0x2000u
1533 #define CAN_MCR_LPRIOEN_SHIFT 13
1534 #define CAN_MCR_IRMQ_MASK 0x10000u
1535 #define CAN_MCR_IRMQ_SHIFT 16
1536 #define CAN_MCR_SRXDIS_MASK 0x20000u
1537 #define CAN_MCR_SRXDIS_SHIFT 17
1538 #define CAN_MCR_DOZE_MASK 0x40000u
1539 #define CAN_MCR_DOZE_SHIFT 18
1540 #define CAN_MCR_LPMACK_MASK 0x100000u
1541 #define CAN_MCR_LPMACK_SHIFT 20
1542 #define CAN_MCR_WRNEN_MASK 0x200000u
1543 #define CAN_MCR_WRNEN_SHIFT 21
1544 #define CAN_MCR_SLFWAK_MASK 0x400000u
1545 #define CAN_MCR_SLFWAK_SHIFT 22
1546 #define CAN_MCR_SUPV_MASK 0x800000u
1547 #define CAN_MCR_SUPV_SHIFT 23
1548 #define CAN_MCR_FRZACK_MASK 0x1000000u
1549 #define CAN_MCR_FRZACK_SHIFT 24
1550 #define CAN_MCR_SOFTRST_MASK 0x2000000u
1551 #define CAN_MCR_SOFTRST_SHIFT 25
1552 #define CAN_MCR_WAKMSK_MASK 0x4000000u
1553 #define CAN_MCR_WAKMSK_SHIFT 26
1554 #define CAN_MCR_NOTRDY_MASK 0x8000000u
1555 #define CAN_MCR_NOTRDY_SHIFT 27
1556 #define CAN_MCR_HALT_MASK 0x10000000u
1557 #define CAN_MCR_HALT_SHIFT 28
1558 #define CAN_MCR_RFEN_MASK 0x20000000u
1559 #define CAN_MCR_RFEN_SHIFT 29
1560 #define CAN_MCR_FRZ_MASK 0x40000000u
1561 #define CAN_MCR_FRZ_SHIFT 30
1562 #define CAN_MCR_MDIS_MASK 0x80000000u
1563 #define CAN_MCR_MDIS_SHIFT 31
1564 /* CTRL1 Bit Fields */
1565 #define CAN_CTRL1_PROPSEG_MASK 0x7u
1566 #define CAN_CTRL1_PROPSEG_SHIFT 0
1567 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
1568 #define CAN_CTRL1_LOM_MASK 0x8u
1569 #define CAN_CTRL1_LOM_SHIFT 3
1570 #define CAN_CTRL1_LBUF_MASK 0x10u
1571 #define CAN_CTRL1_LBUF_SHIFT 4
1572 #define CAN_CTRL1_TSYN_MASK 0x20u
1573 #define CAN_CTRL1_TSYN_SHIFT 5
1574 #define CAN_CTRL1_BOFFREC_MASK 0x40u
1575 #define CAN_CTRL1_BOFFREC_SHIFT 6
1576 #define CAN_CTRL1_SMP_MASK 0x80u
1577 #define CAN_CTRL1_SMP_SHIFT 7
1578 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
1579 #define CAN_CTRL1_RWRNMSK_SHIFT 10
1580 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
1581 #define CAN_CTRL1_TWRNMSK_SHIFT 11
1582 #define CAN_CTRL1_LPB_MASK 0x1000u
1583 #define CAN_CTRL1_LPB_SHIFT 12
1584 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1585 #define CAN_CTRL1_CLKSRC_SHIFT 13
1586 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1587 #define CAN_CTRL1_ERRMSK_SHIFT 14
1588 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1589 #define CAN_CTRL1_BOFFMSK_SHIFT 15
1590 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1591 #define CAN_CTRL1_PSEG2_SHIFT 16
1592 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1593 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1594 #define CAN_CTRL1_PSEG1_SHIFT 19
1595 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1596 #define CAN_CTRL1_RJW_MASK 0xC00000u
1597 #define CAN_CTRL1_RJW_SHIFT 22
1598 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1599 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
1600 #define CAN_CTRL1_PRESDIV_SHIFT 24
1601 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
1602 /* TIMER Bit Fields */
1603 #define CAN_TIMER_TIMER_MASK 0xFFFFu
1604 #define CAN_TIMER_TIMER_SHIFT 0
1605 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
1606 /* RXMGMASK Bit Fields */
1607 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
1608 #define CAN_RXMGMASK_MG_SHIFT 0
1609 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
1610 /* RX14MASK Bit Fields */
1611 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
1612 #define CAN_RX14MASK_RX14M_SHIFT 0
1613 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
1614 /* RX15MASK Bit Fields */
1615 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
1616 #define CAN_RX15MASK_RX15M_SHIFT 0
1617 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
1618 /* ECR Bit Fields */
1619 #define CAN_ECR_TXERRCNT_MASK 0xFFu
1620 #define CAN_ECR_TXERRCNT_SHIFT 0
1621 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
1622 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
1623 #define CAN_ECR_RXERRCNT_SHIFT 8
1624 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
1625 /* ESR1 Bit Fields */
1626 #define CAN_ESR1_WAKINT_MASK 0x1u
1627 #define CAN_ESR1_WAKINT_SHIFT 0
1628 #define CAN_ESR1_ERRINT_MASK 0x2u
1629 #define CAN_ESR1_ERRINT_SHIFT 1
1630 #define CAN_ESR1_BOFFINT_MASK 0x4u
1631 #define CAN_ESR1_BOFFINT_SHIFT 2
1632 #define CAN_ESR1_RX_MASK 0x8u
1633 #define CAN_ESR1_RX_SHIFT 3
1634 #define CAN_ESR1_FLTCONF_MASK 0x30u
1635 #define CAN_ESR1_FLTCONF_SHIFT 4
1636 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
1637 #define CAN_ESR1_TX_MASK 0x40u
1638 #define CAN_ESR1_TX_SHIFT 6
1639 #define CAN_ESR1_IDLE_MASK 0x80u
1640 #define CAN_ESR1_IDLE_SHIFT 7
1641 #define CAN_ESR1_RXWRN_MASK 0x100u
1642 #define CAN_ESR1_RXWRN_SHIFT 8
1643 #define CAN_ESR1_TXWRN_MASK 0x200u
1644 #define CAN_ESR1_TXWRN_SHIFT 9
1645 #define CAN_ESR1_STFERR_MASK 0x400u
1646 #define CAN_ESR1_STFERR_SHIFT 10
1647 #define CAN_ESR1_FRMERR_MASK 0x800u
1648 #define CAN_ESR1_FRMERR_SHIFT 11
1649 #define CAN_ESR1_CRCERR_MASK 0x1000u
1650 #define CAN_ESR1_CRCERR_SHIFT 12
1651 #define CAN_ESR1_ACKERR_MASK 0x2000u
1652 #define CAN_ESR1_ACKERR_SHIFT 13
1653 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
1654 #define CAN_ESR1_BIT0ERR_SHIFT 14
1655 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
1656 #define CAN_ESR1_BIT1ERR_SHIFT 15
1657 #define CAN_ESR1_RWRNINT_MASK 0x10000u
1658 #define CAN_ESR1_RWRNINT_SHIFT 16
1659 #define CAN_ESR1_TWRNINT_MASK 0x20000u
1660 #define CAN_ESR1_TWRNINT_SHIFT 17
1661 #define CAN_ESR1_SYNCH_MASK 0x40000u
1662 #define CAN_ESR1_SYNCH_SHIFT 18
1663 /* IMASK2 Bit Fields */
1664 #define CAN_IMASK2_BUFHM_MASK 0xFFFFFFFFu
1665 #define CAN_IMASK2_BUFHM_SHIFT 0
1666 #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
1667 /* IMASK1 Bit Fields */
1668 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
1669 #define CAN_IMASK1_BUFLM_SHIFT 0
1670 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
1671 /* IFLAG2 Bit Fields */
1672 #define CAN_IFLAG2_BUFHI_MASK 0xFFFFFFFFu
1673 #define CAN_IFLAG2_BUFHI_SHIFT 0
1674 #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
1675 /* IFLAG1 Bit Fields */
1676 #define CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu
1677 #define CAN_IFLAG1_BUF4TO0I_SHIFT 0
1678 #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
1679 #define CAN_IFLAG1_BUF5I_MASK 0x20u
1680 #define CAN_IFLAG1_BUF5I_SHIFT 5
1681 #define CAN_IFLAG1_BUF6I_MASK 0x40u
1682 #define CAN_IFLAG1_BUF6I_SHIFT 6
1683 #define CAN_IFLAG1_BUF7I_MASK 0x80u
1684 #define CAN_IFLAG1_BUF7I_SHIFT 7
1685 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
1686 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
1687 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
1688 /* CTRL2 Bit Fields */
1689 #define CAN_CTRL2_EACEN_MASK 0x10000u
1690 #define CAN_CTRL2_EACEN_SHIFT 16
1691 #define CAN_CTRL2_RRS_MASK 0x20000u
1692 #define CAN_CTRL2_RRS_SHIFT 17
1693 #define CAN_CTRL2_MRP_MASK 0x40000u
1694 #define CAN_CTRL2_MRP_SHIFT 18
1695 #define CAN_CTRL2_TASD_MASK 0xF80000u
1696 #define CAN_CTRL2_TASD_SHIFT 19
1697 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
1698 #define CAN_CTRL2_RFFN_MASK 0xF000000u
1699 #define CAN_CTRL2_RFFN_SHIFT 24
1700 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
1701 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
1702 #define CAN_CTRL2_WRMFRZ_SHIFT 28
1703 /* ESR2 Bit Fields */
1704 #define CAN_ESR2_IMB_MASK 0x2000u
1705 #define CAN_ESR2_IMB_SHIFT 13
1706 #define CAN_ESR2_VPS_MASK 0x4000u
1707 #define CAN_ESR2_VPS_SHIFT 14
1708 #define CAN_ESR2_LPTM_MASK 0x7F0000u
1709 #define CAN_ESR2_LPTM_SHIFT 16
1710 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
1711 /* CRCR Bit Fields */
1712 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
1713 #define CAN_CRCR_TXCRC_SHIFT 0
1714 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
1715 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
1716 #define CAN_CRCR_MBCRC_SHIFT 16
1717 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
1718 /* RXFGMASK Bit Fields */
1719 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
1720 #define CAN_RXFGMASK_FGM_SHIFT 0
1721 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
1722 /* RXFIR Bit Fields */
1723 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
1724 #define CAN_RXFIR_IDHIT_SHIFT 0
1725 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
1726 /* CS Bit Fields */
1727 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
1728 #define CAN_CS_TIME_STAMP_SHIFT 0
1729 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
1730 #define CAN_CS_DLC_MASK 0xF0000u
1731 #define CAN_CS_DLC_SHIFT 16
1732 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
1733 #define CAN_CS_RTR_MASK 0x100000u
1734 #define CAN_CS_RTR_SHIFT 20
1735 #define CAN_CS_IDE_MASK 0x200000u
1736 #define CAN_CS_IDE_SHIFT 21
1737 #define CAN_CS_SRR_MASK 0x400000u
1738 #define CAN_CS_SRR_SHIFT 22
1739 #define CAN_CS_CODE_MASK 0xF000000u
1740 #define CAN_CS_CODE_SHIFT 24
1741 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
1742 /* ID Bit Fields */
1743 #define CAN_ID_EXT_MASK 0x3FFFFu
1744 #define CAN_ID_EXT_SHIFT 0
1745 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
1746 #define CAN_ID_STD_MASK 0x1FFC0000u
1747 #define CAN_ID_STD_SHIFT 18
1748 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
1749 #define CAN_ID_PRIO_MASK 0xE0000000u
1750 #define CAN_ID_PRIO_SHIFT 29
1751 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
1752 /* WORD0 Bit Fields */
1753 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
1754 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
1755 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
1756 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
1757 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
1758 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
1759 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
1760 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
1761 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
1762 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
1763 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
1764 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
1765 /* WORD1 Bit Fields */
1766 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
1767 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
1768 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
1769 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
1770 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
1771 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
1772 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
1773 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
1774 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
1775 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
1776 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
1777 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
1778 /* RXIMR Bit Fields */
1779 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
1780 #define CAN_RXIMR_MI_SHIFT 0
1781 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
1782 
1783 /**
1784  * @}
1785  */ /* end of group CAN_Register_Masks */
1786 
1787 
1788 /* CAN - Peripheral instance base addresses */
1789 /** Peripheral CAN0 base address */
1790 #define CAN0_BASE (0x40024000u)
1791 /** Peripheral CAN0 base pointer */
1792 #define CAN0 ((CAN_Type *)CAN0_BASE)
1793 /** Peripheral CAN1 base address */
1794 #define CAN1_BASE (0x400A4000u)
1795 /** Peripheral CAN1 base pointer */
1796 #define CAN1 ((CAN_Type *)CAN1_BASE)
1797 
1798 /**
1799  * @}
1800  */ /* end of group CAN_Peripheral_Access_Layer */
1801 
1802 
1803 /* ----------------------------------------------------------------------------
1804  -- CAU Peripheral Access Layer
1805  ---------------------------------------------------------------------------- */
1806 
1807 /**
1808  * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
1809  * @{
1810  */
1811 
1812 /** CAU - Register Layout Typedef */
1813 typedef struct {
1814  __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
1815  uint8_t RESERVED_0[2048];
1816  __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
1817  __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
1818  __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
1819  uint8_t RESERVED_1[20];
1820  __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
1821  __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
1822  __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
1823  uint8_t RESERVED_2[20];
1824  __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
1825  __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
1826  __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
1827  uint8_t RESERVED_3[20];
1828  __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
1829  __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
1830  __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
1831  uint8_t RESERVED_4[84];
1832  __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
1833  __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
1834  __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
1835  uint8_t RESERVED_5[20];
1836  __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
1837  __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
1838  __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
1839  uint8_t RESERVED_6[276];
1840  __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
1841  __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
1842  __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
1843  uint8_t RESERVED_7[20];
1844  __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
1845  __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
1846  __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
1847 } CAU_Type;
1848 
1849 /* ----------------------------------------------------------------------------
1850  -- CAU Register Masks
1851  ---------------------------------------------------------------------------- */
1852 
1853 /**
1854  * @addtogroup CAU_Register_Masks CAU Register Masks
1855  * @{
1856  */
1857 
1858 /* LDR_CASR Bit Fields */
1859 #define CAU_LDR_CASR_IC_MASK 0x1u
1860 #define CAU_LDR_CASR_IC_SHIFT 0
1861 #define CAU_LDR_CASR_DPE_MASK 0x2u
1862 #define CAU_LDR_CASR_DPE_SHIFT 1
1863 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
1864 #define CAU_LDR_CASR_VER_SHIFT 28
1865 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
1866 /* STR_CASR Bit Fields */
1867 #define CAU_STR_CASR_IC_MASK 0x1u
1868 #define CAU_STR_CASR_IC_SHIFT 0
1869 #define CAU_STR_CASR_DPE_MASK 0x2u
1870 #define CAU_STR_CASR_DPE_SHIFT 1
1871 #define CAU_STR_CASR_VER_MASK 0xF0000000u
1872 #define CAU_STR_CASR_VER_SHIFT 28
1873 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
1874 /* ADR_CASR Bit Fields */
1875 #define CAU_ADR_CASR_IC_MASK 0x1u
1876 #define CAU_ADR_CASR_IC_SHIFT 0
1877 #define CAU_ADR_CASR_DPE_MASK 0x2u
1878 #define CAU_ADR_CASR_DPE_SHIFT 1
1879 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
1880 #define CAU_ADR_CASR_VER_SHIFT 28
1881 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
1882 /* RADR_CASR Bit Fields */
1883 #define CAU_RADR_CASR_IC_MASK 0x1u
1884 #define CAU_RADR_CASR_IC_SHIFT 0
1885 #define CAU_RADR_CASR_DPE_MASK 0x2u
1886 #define CAU_RADR_CASR_DPE_SHIFT 1
1887 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
1888 #define CAU_RADR_CASR_VER_SHIFT 28
1889 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
1890 /* XOR_CASR Bit Fields */
1891 #define CAU_XOR_CASR_IC_MASK 0x1u
1892 #define CAU_XOR_CASR_IC_SHIFT 0
1893 #define CAU_XOR_CASR_DPE_MASK 0x2u
1894 #define CAU_XOR_CASR_DPE_SHIFT 1
1895 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
1896 #define CAU_XOR_CASR_VER_SHIFT 28
1897 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
1898 /* ROTL_CASR Bit Fields */
1899 #define CAU_ROTL_CASR_IC_MASK 0x1u
1900 #define CAU_ROTL_CASR_IC_SHIFT 0
1901 #define CAU_ROTL_CASR_DPE_MASK 0x2u
1902 #define CAU_ROTL_CASR_DPE_SHIFT 1
1903 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
1904 #define CAU_ROTL_CASR_VER_SHIFT 28
1905 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
1906 /* AESC_CASR Bit Fields */
1907 #define CAU_AESC_CASR_IC_MASK 0x1u
1908 #define CAU_AESC_CASR_IC_SHIFT 0
1909 #define CAU_AESC_CASR_DPE_MASK 0x2u
1910 #define CAU_AESC_CASR_DPE_SHIFT 1
1911 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
1912 #define CAU_AESC_CASR_VER_SHIFT 28
1913 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
1914 /* AESIC_CASR Bit Fields */
1915 #define CAU_AESIC_CASR_IC_MASK 0x1u
1916 #define CAU_AESIC_CASR_IC_SHIFT 0
1917 #define CAU_AESIC_CASR_DPE_MASK 0x2u
1918 #define CAU_AESIC_CASR_DPE_SHIFT 1
1919 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
1920 #define CAU_AESIC_CASR_VER_SHIFT 28
1921 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
1922 
1923 /**
1924  * @}
1925  */ /* end of group CAU_Register_Masks */
1926 
1927 
1928 /* CAU - Peripheral instance base addresses */
1929 /** Peripheral CAU base address */
1930 #define CAU_BASE (0xE0081000u)
1931 /** Peripheral CAU base pointer */
1932 #define CAU ((CAU_Type *)CAU_BASE)
1933 
1934 /**
1935  * @}
1936  */ /* end of group CAU_Peripheral_Access_Layer */
1937 
1938 
1939 /* ----------------------------------------------------------------------------
1940  -- CMP Peripheral Access Layer
1941  ---------------------------------------------------------------------------- */
1942 
1943 /**
1944  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
1945  * @{
1946  */
1947 
1948 /** CMP - Register Layout Typedef */
1949 typedef struct {
1950  __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
1951  __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
1952  __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
1953  __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
1954  __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
1955  __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
1956 } CMP_Type;
1957 
1958 /* ----------------------------------------------------------------------------
1959  -- CMP Register Masks
1960  ---------------------------------------------------------------------------- */
1961 
1962 /**
1963  * @addtogroup CMP_Register_Masks CMP Register Masks
1964  * @{
1965  */
1966 
1967 /* CR0 Bit Fields */
1968 #define CMP_CR0_HYSTCTR_MASK 0x3u
1969 #define CMP_CR0_HYSTCTR_SHIFT 0
1970 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
1971 #define CMP_CR0_FILTER_CNT_MASK 0x70u
1972 #define CMP_CR0_FILTER_CNT_SHIFT 4
1973 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
1974 /* CR1 Bit Fields */
1975 #define CMP_CR1_EN_MASK 0x1u
1976 #define CMP_CR1_EN_SHIFT 0
1977 #define CMP_CR1_OPE_MASK 0x2u
1978 #define CMP_CR1_OPE_SHIFT 1
1979 #define CMP_CR1_COS_MASK 0x4u
1980 #define CMP_CR1_COS_SHIFT 2
1981 #define CMP_CR1_INV_MASK 0x8u
1982 #define CMP_CR1_INV_SHIFT 3
1983 #define CMP_CR1_PMODE_MASK 0x10u
1984 #define CMP_CR1_PMODE_SHIFT 4
1985 #define CMP_CR1_WE_MASK 0x40u
1986 #define CMP_CR1_WE_SHIFT 6
1987 #define CMP_CR1_SE_MASK 0x80u
1988 #define CMP_CR1_SE_SHIFT 7
1989 /* FPR Bit Fields */
1990 #define CMP_FPR_FILT_PER_MASK 0xFFu
1991 #define CMP_FPR_FILT_PER_SHIFT 0
1992 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
1993 /* SCR Bit Fields */
1994 #define CMP_SCR_COUT_MASK 0x1u
1995 #define CMP_SCR_COUT_SHIFT 0
1996 #define CMP_SCR_CFF_MASK 0x2u
1997 #define CMP_SCR_CFF_SHIFT 1
1998 #define CMP_SCR_CFR_MASK 0x4u
1999 #define CMP_SCR_CFR_SHIFT 2
2000 #define CMP_SCR_IEF_MASK 0x8u
2001 #define CMP_SCR_IEF_SHIFT 3
2002 #define CMP_SCR_IER_MASK 0x10u
2003 #define CMP_SCR_IER_SHIFT 4
2004 #define CMP_SCR_SMELB_MASK 0x20u
2005 #define CMP_SCR_SMELB_SHIFT 5
2006 #define CMP_SCR_DMAEN_MASK 0x40u
2007 #define CMP_SCR_DMAEN_SHIFT 6
2008 /* DACCR Bit Fields */
2009 #define CMP_DACCR_VOSEL_MASK 0x3Fu
2010 #define CMP_DACCR_VOSEL_SHIFT 0
2011 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
2012 #define CMP_DACCR_VRSEL_MASK 0x40u
2013 #define CMP_DACCR_VRSEL_SHIFT 6
2014 #define CMP_DACCR_DACEN_MASK 0x80u
2015 #define CMP_DACCR_DACEN_SHIFT 7
2016 /* MUXCR Bit Fields */
2017 #define CMP_MUXCR_MSEL_MASK 0x7u
2018 #define CMP_MUXCR_MSEL_SHIFT 0
2019 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
2020 #define CMP_MUXCR_PSEL_MASK 0x38u
2021 #define CMP_MUXCR_PSEL_SHIFT 3
2022 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
2023 #define CMP_MUXCR_MEN_MASK 0x40u
2024 #define CMP_MUXCR_MEN_SHIFT 6
2025 #define CMP_MUXCR_PEN_MASK 0x80u
2026 #define CMP_MUXCR_PEN_SHIFT 7
2027 
2028 /**
2029  * @}
2030  */ /* end of group CMP_Register_Masks */
2031 
2032 
2033 /* CMP - Peripheral instance base addresses */
2034 /** Peripheral CMP0 base address */
2035 #define CMP0_BASE (0x40073000u)
2036 /** Peripheral CMP0 base pointer */
2037 #define CMP0 ((CMP_Type *)CMP0_BASE)
2038 /** Peripheral CMP1 base address */
2039 #define CMP1_BASE (0x40073008u)
2040 /** Peripheral CMP1 base pointer */
2041 #define CMP1 ((CMP_Type *)CMP1_BASE)
2042 /** Peripheral CMP2 base address */
2043 #define CMP2_BASE (0x40073010u)
2044 /** Peripheral CMP2 base pointer */
2045 #define CMP2 ((CMP_Type *)CMP2_BASE)
2046 
2047 /**
2048  * @}
2049  */ /* end of group CMP_Peripheral_Access_Layer */
2050 
2051 
2052 /* ----------------------------------------------------------------------------
2053  -- CMT Peripheral Access Layer
2054  ---------------------------------------------------------------------------- */
2055 
2056 /**
2057  * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
2058  * @{
2059  */
2060 
2061 /** CMT - Register Layout Typedef */
2062 typedef struct {
2063  __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
2064  __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
2065  __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
2066  __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
2067  __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
2068  __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
2069  __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
2070  __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
2071  __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
2072  __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
2073  __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
2074  __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
2075 } CMT_Type;
2076 
2077 /* ----------------------------------------------------------------------------
2078  -- CMT Register Masks
2079  ---------------------------------------------------------------------------- */
2080 
2081 /**
2082  * @addtogroup CMT_Register_Masks CMT Register Masks
2083  * @{
2084  */
2085 
2086 /* CGH1 Bit Fields */
2087 #define CMT_CGH1_PH_MASK 0xFFu
2088 #define CMT_CGH1_PH_SHIFT 0
2089 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
2090 /* CGL1 Bit Fields */
2091 #define CMT_CGL1_PL_MASK 0xFFu
2092 #define CMT_CGL1_PL_SHIFT 0
2093 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
2094 /* CGH2 Bit Fields */
2095 #define CMT_CGH2_SH_MASK 0xFFu
2096 #define CMT_CGH2_SH_SHIFT 0
2097 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
2098 /* CGL2 Bit Fields */
2099 #define CMT_CGL2_SL_MASK 0xFFu
2100 #define CMT_CGL2_SL_SHIFT 0
2101 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
2102 /* OC Bit Fields */
2103 #define CMT_OC_IROPEN_MASK 0x20u
2104 #define CMT_OC_IROPEN_SHIFT 5
2105 #define CMT_OC_CMTPOL_MASK 0x40u
2106 #define CMT_OC_CMTPOL_SHIFT 6
2107 #define CMT_OC_IROL_MASK 0x80u
2108 #define CMT_OC_IROL_SHIFT 7
2109 /* MSC Bit Fields */
2110 #define CMT_MSC_MCGEN_MASK 0x1u
2111 #define CMT_MSC_MCGEN_SHIFT 0
2112 #define CMT_MSC_EOCIE_MASK 0x2u
2113 #define CMT_MSC_EOCIE_SHIFT 1
2114 #define CMT_MSC_FSK_MASK 0x4u
2115 #define CMT_MSC_FSK_SHIFT 2
2116 #define CMT_MSC_BASE_MASK 0x8u
2117 #define CMT_MSC_BASE_SHIFT 3
2118 #define CMT_MSC_EXSPC_MASK 0x10u
2119 #define CMT_MSC_EXSPC_SHIFT 4
2120 #define CMT_MSC_CMTDIV_MASK 0x60u
2121 #define CMT_MSC_CMTDIV_SHIFT 5
2122 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
2123 #define CMT_MSC_EOCF_MASK 0x80u
2124 #define CMT_MSC_EOCF_SHIFT 7
2125 /* CMD1 Bit Fields */
2126 #define CMT_CMD1_MB_MASK 0xFFu
2127 #define CMT_CMD1_MB_SHIFT 0
2128 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
2129 /* CMD2 Bit Fields */
2130 #define CMT_CMD2_MB_MASK 0xFFu
2131 #define CMT_CMD2_MB_SHIFT 0
2132 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
2133 /* CMD3 Bit Fields */
2134 #define CMT_CMD3_SB_MASK 0xFFu
2135 #define CMT_CMD3_SB_SHIFT 0
2136 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
2137 /* CMD4 Bit Fields */
2138 #define CMT_CMD4_SB_MASK 0xFFu
2139 #define CMT_CMD4_SB_SHIFT 0
2140 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
2141 /* PPS Bit Fields */
2142 #define CMT_PPS_PPSDIV_MASK 0xFu
2143 #define CMT_PPS_PPSDIV_SHIFT 0
2144 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
2145 /* DMA Bit Fields */
2146 #define CMT_DMA_DMA_MASK 0x1u
2147 #define CMT_DMA_DMA_SHIFT 0
2148 
2149 /**
2150  * @}
2151  */ /* end of group CMT_Register_Masks */
2152 
2153 
2154 /* CMT - Peripheral instance base addresses */
2155 /** Peripheral CMT base address */
2156 #define CMT_BASE (0x40062000u)
2157 /** Peripheral CMT base pointer */
2158 #define CMT ((CMT_Type *)CMT_BASE)
2159 
2160 /**
2161  * @}
2162  */ /* end of group CMT_Peripheral_Access_Layer */
2163 
2164 
2165 /* ----------------------------------------------------------------------------
2166  -- CRC Peripheral Access Layer
2167  ---------------------------------------------------------------------------- */
2168 
2169 /**
2170  * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2171  * @{
2172  */
2173 
2174 /** CRC - Register Layout Typedef */
2175 typedef struct {
2176  union { /* offset: 0x0 */
2177  struct { /* offset: 0x0 */
2178  __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
2179  __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
2180  } ACCESS16BIT;
2181  __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
2182  struct { /* offset: 0x0 */
2183  __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
2184  __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
2185  __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
2186  __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
2187  } ACCESS8BIT;
2188  };
2189  union { /* offset: 0x4 */
2190  struct { /* offset: 0x4 */
2191  __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
2192  __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
2193  } GPOLY_ACCESS16BIT;
2194  __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
2195  struct { /* offset: 0x4 */
2196  __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
2197  __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
2198  __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
2199  __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
2200  } GPOLY_ACCESS8BIT;
2201  };
2202  union { /* offset: 0x8 */
2203  __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
2204  struct { /* offset: 0x8 */
2205  uint8_t RESERVED_0[3];
2206  __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
2207  } CTRL_ACCESS8BIT;
2208  };
2209 } CRC_Type;
2210 
2211 /* ----------------------------------------------------------------------------
2212  -- CRC Register Masks
2213  ---------------------------------------------------------------------------- */
2214 
2215 /**
2216  * @addtogroup CRC_Register_Masks CRC Register Masks
2217  * @{
2218  */
2219 
2220 /* CRCL Bit Fields */
2221 #define CRC_CRCL_CRCL_MASK 0xFFFFu
2222 #define CRC_CRCL_CRCL_SHIFT 0
2223 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
2224 /* CRCH Bit Fields */
2225 #define CRC_CRCH_CRCH_MASK 0xFFFFu
2226 #define CRC_CRCH_CRCH_SHIFT 0
2227 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
2228 /* CRC Bit Fields */
2229 #define CRC_CRC_LL_MASK 0xFFu
2230 #define CRC_CRC_LL_SHIFT 0
2231 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
2232 #define CRC_CRC_LU_MASK 0xFF00u
2233 #define CRC_CRC_LU_SHIFT 8
2234 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
2235 #define CRC_CRC_HL_MASK 0xFF0000u
2236 #define CRC_CRC_HL_SHIFT 16
2237 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
2238 #define CRC_CRC_HU_MASK 0xFF000000u
2239 #define CRC_CRC_HU_SHIFT 24
2240 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
2241 /* CRCLL Bit Fields */
2242 #define CRC_CRCLL_CRCLL_MASK 0xFFu
2243 #define CRC_CRCLL_CRCLL_SHIFT 0
2244 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
2245 /* CRCLU Bit Fields */
2246 #define CRC_CRCLU_CRCLU_MASK 0xFFu
2247 #define CRC_CRCLU_CRCLU_SHIFT 0
2248 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
2249 /* CRCHL Bit Fields */
2250 #define CRC_CRCHL_CRCHL_MASK 0xFFu
2251 #define CRC_CRCHL_CRCHL_SHIFT 0
2252 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
2253 /* CRCHU Bit Fields */
2254 #define CRC_CRCHU_CRCHU_MASK 0xFFu
2255 #define CRC_CRCHU_CRCHU_SHIFT 0
2256 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
2257 /* GPOLYL Bit Fields */
2258 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
2259 #define CRC_GPOLYL_GPOLYL_SHIFT 0
2260 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
2261 /* GPOLYH Bit Fields */
2262 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
2263 #define CRC_GPOLYH_GPOLYH_SHIFT 0
2264 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
2265 /* GPOLY Bit Fields */
2266 #define CRC_GPOLY_LOW_MASK 0xFFFFu
2267 #define CRC_GPOLY_LOW_SHIFT 0
2268 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
2269 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
2270 #define CRC_GPOLY_HIGH_SHIFT 16
2271 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
2272 /* GPOLYLL Bit Fields */
2273 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
2274 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
2275 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
2276 /* GPOLYLU Bit Fields */
2277 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
2278 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
2279 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
2280 /* GPOLYHL Bit Fields */
2281 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
2282 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
2283 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
2284 /* GPOLYHU Bit Fields */
2285 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
2286 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
2287 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
2288 /* CTRL Bit Fields */
2289 #define CRC_CTRL_TCRC_MASK 0x1000000u
2290 #define CRC_CTRL_TCRC_SHIFT 24
2291 #define CRC_CTRL_WAS_MASK 0x2000000u
2292 #define CRC_CTRL_WAS_SHIFT 25
2293 #define CRC_CTRL_FXOR_MASK 0x4000000u
2294 #define CRC_CTRL_FXOR_SHIFT 26
2295 #define CRC_CTRL_TOTR_MASK 0x30000000u
2296 #define CRC_CTRL_TOTR_SHIFT 28
2297 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
2298 #define CRC_CTRL_TOT_MASK 0xC0000000u
2299 #define CRC_CTRL_TOT_SHIFT 30
2300 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
2301 /* CTRLHU Bit Fields */
2302 #define CRC_CTRLHU_TCRC_MASK 0x1u
2303 #define CRC_CTRLHU_TCRC_SHIFT 0
2304 #define CRC_CTRLHU_WAS_MASK 0x2u
2305 #define CRC_CTRLHU_WAS_SHIFT 1
2306 #define CRC_CTRLHU_FXOR_MASK 0x4u
2307 #define CRC_CTRLHU_FXOR_SHIFT 2
2308 #define CRC_CTRLHU_TOTR_MASK 0x30u
2309 #define CRC_CTRLHU_TOTR_SHIFT 4
2310 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
2311 #define CRC_CTRLHU_TOT_MASK 0xC0u
2312 #define CRC_CTRLHU_TOT_SHIFT 6
2313 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
2314 
2315 /**
2316  * @}
2317  */ /* end of group CRC_Register_Masks */
2318 
2319 
2320 /* CRC - Peripheral instance base addresses */
2321 /** Peripheral CRC base address */
2322 #define CRC_BASE (0x40032000u)
2323 /** Peripheral CRC base pointer */
2324 #define CRC0 ((CRC_Type *)CRC_BASE)
2325 
2326 /**
2327  * @}
2328  */ /* end of group CRC_Peripheral_Access_Layer */
2329 
2330 
2331 /* ----------------------------------------------------------------------------
2332  -- DAC Peripheral Access Layer
2333  ---------------------------------------------------------------------------- */
2334 
2335 /**
2336  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2337  * @{
2338  */
2339 
2340 /** DAC - Register Layout Typedef */
2341 typedef struct {
2342  struct { /* offset: 0x0, array step: 0x2 */
2343  __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
2344  __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
2345  } DAT[16];
2346  __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
2347  __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
2348  __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
2349  __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
2350 } DAC_Type;
2351 
2352 /* ----------------------------------------------------------------------------
2353  -- DAC Register Masks
2354  ---------------------------------------------------------------------------- */
2355 
2356 /**
2357  * @addtogroup DAC_Register_Masks DAC Register Masks
2358  * @{
2359  */
2360 
2361 /* DATL Bit Fields */
2362 #define DAC_DATL_DATA_MASK 0xFFu
2363 #define DAC_DATL_DATA_SHIFT 0
2364 #define DAC_DATL_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA_SHIFT))&DAC_DATL_DATA_MASK)
2365 /* DATH Bit Fields */
2366 #define DAC_DATH_DATA_MASK 0xFu
2367 #define DAC_DATH_DATA_SHIFT 0
2368 #define DAC_DATH_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA_SHIFT))&DAC_DATH_DATA_MASK)
2369 /* SR Bit Fields */
2370 #define DAC_SR_DACBFRPBF_MASK 0x1u
2371 #define DAC_SR_DACBFRPBF_SHIFT 0
2372 #define DAC_SR_DACBFRPTF_MASK 0x2u
2373 #define DAC_SR_DACBFRPTF_SHIFT 1
2374 #define DAC_SR_DACBFWMF_MASK 0x4u
2375 #define DAC_SR_DACBFWMF_SHIFT 2
2376 /* C0 Bit Fields */
2377 #define DAC_C0_DACBBIEN_MASK 0x1u
2378 #define DAC_C0_DACBBIEN_SHIFT 0
2379 #define DAC_C0_DACBTIEN_MASK 0x2u
2380 #define DAC_C0_DACBTIEN_SHIFT 1
2381 #define DAC_C0_DACBWIEN_MASK 0x4u
2382 #define DAC_C0_DACBWIEN_SHIFT 2
2383 #define DAC_C0_LPEN_MASK 0x8u
2384 #define DAC_C0_LPEN_SHIFT 3
2385 #define DAC_C0_DACSWTRG_MASK 0x10u
2386 #define DAC_C0_DACSWTRG_SHIFT 4
2387 #define DAC_C0_DACTRGSEL_MASK 0x20u
2388 #define DAC_C0_DACTRGSEL_SHIFT 5
2389 #define DAC_C0_DACRFS_MASK 0x40u
2390 #define DAC_C0_DACRFS_SHIFT 6
2391 #define DAC_C0_DACEN_MASK 0x80u
2392 #define DAC_C0_DACEN_SHIFT 7
2393 /* C1 Bit Fields */
2394 #define DAC_C1_DACBFEN_MASK 0x1u
2395 #define DAC_C1_DACBFEN_SHIFT 0
2396 #define DAC_C1_DACBFMD_MASK 0x6u
2397 #define DAC_C1_DACBFMD_SHIFT 1
2398 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
2399 #define DAC_C1_DACBFWM_MASK 0x18u
2400 #define DAC_C1_DACBFWM_SHIFT 3
2401 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
2402 #define DAC_C1_DMAEN_MASK 0x80u
2403 #define DAC_C1_DMAEN_SHIFT 7
2404 /* C2 Bit Fields */
2405 #define DAC_C2_DACBFUP_MASK 0xFu
2406 #define DAC_C2_DACBFUP_SHIFT 0
2407 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
2408 #define DAC_C2_DACBFRP_MASK 0xF0u
2409 #define DAC_C2_DACBFRP_SHIFT 4
2410 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
2411 
2412 /**
2413  * @}
2414  */ /* end of group DAC_Register_Masks */
2415 
2416 
2417 /* DAC - Peripheral instance base addresses */
2418 /** Peripheral DAC0 base address */
2419 #define DAC0_BASE (0x400CC000u)
2420 /** Peripheral DAC0 base pointer */
2421 #define DAC0 ((DAC_Type *)DAC0_BASE)
2422 /** Peripheral DAC1 base address */
2423 #define DAC1_BASE (0x400CD000u)
2424 /** Peripheral DAC1 base pointer */
2425 #define DAC1 ((DAC_Type *)DAC1_BASE)
2426 
2427 /**
2428  * @}
2429  */ /* end of group DAC_Peripheral_Access_Layer */
2430 
2431 
2432 /* ----------------------------------------------------------------------------
2433  -- DMA Peripheral Access Layer
2434  ---------------------------------------------------------------------------- */
2435 
2436 /**
2437  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2438  * @{
2439  */
2440 
2441 /** DMA - Register Layout Typedef */
2442 typedef struct {
2443  __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2444  __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
2445  uint8_t RESERVED_0[4];
2446  __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2447  uint8_t RESERVED_1[4];
2448  __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2449  __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2450  __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
2451  __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
2452  __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2453  __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
2454  __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
2455  __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
2456  __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
2457  uint8_t RESERVED_2[4];
2458  __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2459  uint8_t RESERVED_3[4];
2460  __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2461  uint8_t RESERVED_4[4];
2462  __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2463  uint8_t RESERVED_5[200];
2464  __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
2465  __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
2466  __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
2467  __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
2468  __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
2469  __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
2470  __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
2471  __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
2472  __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
2473  __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
2474  __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
2475  __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
2476  __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
2477  __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
2478  __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
2479  __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
2480  uint8_t RESERVED_6[3824];
2481  struct { /* offset: 0x1000, array step: 0x20 */
2482  __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2483  __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2484  __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2485  union { /* offset: 0x1008, array step: 0x20 */
2486  __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
2487  __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
2488  __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
2489  };
2490  __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2491  __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2492  __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2493  union { /* offset: 0x1016, array step: 0x20 */
2494  __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
2495  __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
2496  };
2497  __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
2498  __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2499  union { /* offset: 0x101E, array step: 0x20 */
2500  __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
2501  __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
2502  };
2503  } TCD[16];
2504 } DMA_Type;
2505 
2506 /* ----------------------------------------------------------------------------
2507  -- DMA Register Masks
2508  ---------------------------------------------------------------------------- */
2509 
2510 /**
2511  * @addtogroup DMA_Register_Masks DMA Register Masks
2512  * @{
2513  */
2514 
2515 /* CR Bit Fields */
2516 #define DMA_CR_EDBG_MASK 0x2u
2517 #define DMA_CR_EDBG_SHIFT 1
2518 #define DMA_CR_ERCA_MASK 0x4u
2519 #define DMA_CR_ERCA_SHIFT 2
2520 #define DMA_CR_HOE_MASK 0x10u
2521 #define DMA_CR_HOE_SHIFT 4
2522 #define DMA_CR_HALT_MASK 0x20u
2523 #define DMA_CR_HALT_SHIFT 5
2524 #define DMA_CR_CLM_MASK 0x40u
2525 #define DMA_CR_CLM_SHIFT 6
2526 #define DMA_CR_EMLM_MASK 0x80u
2527 #define DMA_CR_EMLM_SHIFT 7
2528 #define DMA_CR_ECX_MASK 0x10000u
2529 #define DMA_CR_ECX_SHIFT 16
2530 #define DMA_CR_CX_MASK 0x20000u
2531 #define DMA_CR_CX_SHIFT 17
2532 /* ES Bit Fields */
2533 #define DMA_ES_DBE_MASK 0x1u
2534 #define DMA_ES_DBE_SHIFT 0
2535 #define DMA_ES_SBE_MASK 0x2u
2536 #define DMA_ES_SBE_SHIFT 1
2537 #define DMA_ES_SGE_MASK 0x4u
2538 #define DMA_ES_SGE_SHIFT 2
2539 #define DMA_ES_NCE_MASK 0x8u
2540 #define DMA_ES_NCE_SHIFT 3
2541 #define DMA_ES_DOE_MASK 0x10u
2542 #define DMA_ES_DOE_SHIFT 4
2543 #define DMA_ES_DAE_MASK 0x20u
2544 #define DMA_ES_DAE_SHIFT 5
2545 #define DMA_ES_SOE_MASK 0x40u
2546 #define DMA_ES_SOE_SHIFT 6
2547 #define DMA_ES_SAE_MASK 0x80u
2548 #define DMA_ES_SAE_SHIFT 7
2549 #define DMA_ES_ERRCHN_MASK 0xF00u
2550 #define DMA_ES_ERRCHN_SHIFT 8
2551 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
2552 #define DMA_ES_CPE_MASK 0x4000u
2553 #define DMA_ES_CPE_SHIFT 14
2554 #define DMA_ES_ECX_MASK 0x10000u
2555 #define DMA_ES_ECX_SHIFT 16
2556 #define DMA_ES_VLD_MASK 0x80000000u
2557 #define DMA_ES_VLD_SHIFT 31
2558 /* ERQ Bit Fields */
2559 #define DMA_ERQ_ERQ0_MASK 0x1u
2560 #define DMA_ERQ_ERQ0_SHIFT 0
2561 #define DMA_ERQ_ERQ1_MASK 0x2u
2562 #define DMA_ERQ_ERQ1_SHIFT 1
2563 #define DMA_ERQ_ERQ2_MASK 0x4u
2564 #define DMA_ERQ_ERQ2_SHIFT 2
2565 #define DMA_ERQ_ERQ3_MASK 0x8u
2566 #define DMA_ERQ_ERQ3_SHIFT 3
2567 #define DMA_ERQ_ERQ4_MASK 0x10u
2568 #define DMA_ERQ_ERQ4_SHIFT 4
2569 #define DMA_ERQ_ERQ5_MASK 0x20u
2570 #define DMA_ERQ_ERQ5_SHIFT 5
2571 #define DMA_ERQ_ERQ6_MASK 0x40u
2572 #define DMA_ERQ_ERQ6_SHIFT 6
2573 #define DMA_ERQ_ERQ7_MASK 0x80u
2574 #define DMA_ERQ_ERQ7_SHIFT 7
2575 #define DMA_ERQ_ERQ8_MASK 0x100u
2576 #define DMA_ERQ_ERQ8_SHIFT 8
2577 #define DMA_ERQ_ERQ9_MASK 0x200u
2578 #define DMA_ERQ_ERQ9_SHIFT 9
2579 #define DMA_ERQ_ERQ10_MASK 0x400u
2580 #define DMA_ERQ_ERQ10_SHIFT 10
2581 #define DMA_ERQ_ERQ11_MASK 0x800u
2582 #define DMA_ERQ_ERQ11_SHIFT 11
2583 #define DMA_ERQ_ERQ12_MASK 0x1000u
2584 #define DMA_ERQ_ERQ12_SHIFT 12
2585 #define DMA_ERQ_ERQ13_MASK 0x2000u
2586 #define DMA_ERQ_ERQ13_SHIFT 13
2587 #define DMA_ERQ_ERQ14_MASK 0x4000u
2588 #define DMA_ERQ_ERQ14_SHIFT 14
2589 #define DMA_ERQ_ERQ15_MASK 0x8000u
2590 #define DMA_ERQ_ERQ15_SHIFT 15
2591 /* EEI Bit Fields */
2592 #define DMA_EEI_EEI0_MASK 0x1u
2593 #define DMA_EEI_EEI0_SHIFT 0
2594 #define DMA_EEI_EEI1_MASK 0x2u
2595 #define DMA_EEI_EEI1_SHIFT 1
2596 #define DMA_EEI_EEI2_MASK 0x4u
2597 #define DMA_EEI_EEI2_SHIFT 2
2598 #define DMA_EEI_EEI3_MASK 0x8u
2599 #define DMA_EEI_EEI3_SHIFT 3
2600 #define DMA_EEI_EEI4_MASK 0x10u
2601 #define DMA_EEI_EEI4_SHIFT 4
2602 #define DMA_EEI_EEI5_MASK 0x20u
2603 #define DMA_EEI_EEI5_SHIFT 5
2604 #define DMA_EEI_EEI6_MASK 0x40u
2605 #define DMA_EEI_EEI6_SHIFT 6
2606 #define DMA_EEI_EEI7_MASK 0x80u
2607 #define DMA_EEI_EEI7_SHIFT 7
2608 #define DMA_EEI_EEI8_MASK 0x100u
2609 #define DMA_EEI_EEI8_SHIFT 8
2610 #define DMA_EEI_EEI9_MASK 0x200u
2611 #define DMA_EEI_EEI9_SHIFT 9
2612 #define DMA_EEI_EEI10_MASK 0x400u
2613 #define DMA_EEI_EEI10_SHIFT 10
2614 #define DMA_EEI_EEI11_MASK 0x800u
2615 #define DMA_EEI_EEI11_SHIFT 11
2616 #define DMA_EEI_EEI12_MASK 0x1000u
2617 #define DMA_EEI_EEI12_SHIFT 12
2618 #define DMA_EEI_EEI13_MASK 0x2000u
2619 #define DMA_EEI_EEI13_SHIFT 13
2620 #define DMA_EEI_EEI14_MASK 0x4000u
2621 #define DMA_EEI_EEI14_SHIFT 14
2622 #define DMA_EEI_EEI15_MASK 0x8000u
2623 #define DMA_EEI_EEI15_SHIFT 15
2624 /* CEEI Bit Fields */
2625 #define DMA_CEEI_CEEI_MASK 0xFu
2626 #define DMA_CEEI_CEEI_SHIFT 0
2627 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
2628 #define DMA_CEEI_CAEE_MASK 0x40u
2629 #define DMA_CEEI_CAEE_SHIFT 6
2630 #define DMA_CEEI_NOP_MASK 0x80u
2631 #define DMA_CEEI_NOP_SHIFT 7
2632 /* SEEI Bit Fields */
2633 #define DMA_SEEI_SEEI_MASK 0xFu
2634 #define DMA_SEEI_SEEI_SHIFT 0
2635 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
2636 #define DMA_SEEI_SAEE_MASK 0x40u
2637 #define DMA_SEEI_SAEE_SHIFT 6
2638 #define DMA_SEEI_NOP_MASK 0x80u
2639 #define DMA_SEEI_NOP_SHIFT 7
2640 /* CERQ Bit Fields */
2641 #define DMA_CERQ_CERQ_MASK 0xFu
2642 #define DMA_CERQ_CERQ_SHIFT 0
2643 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
2644 #define DMA_CERQ_CAER_MASK 0x40u
2645 #define DMA_CERQ_CAER_SHIFT 6
2646 #define DMA_CERQ_NOP_MASK 0x80u
2647 #define DMA_CERQ_NOP_SHIFT 7
2648 /* SERQ Bit Fields */
2649 #define DMA_SERQ_SERQ_MASK 0xFu
2650 #define DMA_SERQ_SERQ_SHIFT 0
2651 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
2652 #define DMA_SERQ_SAER_MASK 0x40u
2653 #define DMA_SERQ_SAER_SHIFT 6
2654 #define DMA_SERQ_NOP_MASK 0x80u
2655 #define DMA_SERQ_NOP_SHIFT 7
2656 /* CDNE Bit Fields */
2657 #define DMA_CDNE_CDNE_MASK 0xFu
2658 #define DMA_CDNE_CDNE_SHIFT 0
2659 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
2660 #define DMA_CDNE_CADN_MASK 0x40u
2661 #define DMA_CDNE_CADN_SHIFT 6
2662 #define DMA_CDNE_NOP_MASK 0x80u
2663 #define DMA_CDNE_NOP_SHIFT 7
2664 /* SSRT Bit Fields */
2665 #define DMA_SSRT_SSRT_MASK 0xFu
2666 #define DMA_SSRT_SSRT_SHIFT 0
2667 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
2668 #define DMA_SSRT_SAST_MASK 0x40u
2669 #define DMA_SSRT_SAST_SHIFT 6
2670 #define DMA_SSRT_NOP_MASK 0x80u
2671 #define DMA_SSRT_NOP_SHIFT 7
2672 /* CERR Bit Fields */
2673 #define DMA_CERR_CERR_MASK 0xFu
2674 #define DMA_CERR_CERR_SHIFT 0
2675 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
2676 #define DMA_CERR_CAEI_MASK 0x40u
2677 #define DMA_CERR_CAEI_SHIFT 6
2678 #define DMA_CERR_NOP_MASK 0x80u
2679 #define DMA_CERR_NOP_SHIFT 7
2680 /* CINT Bit Fields */
2681 #define DMA_CINT_CINT_MASK 0xFu
2682 #define DMA_CINT_CINT_SHIFT 0
2683 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
2684 #define DMA_CINT_CAIR_MASK 0x40u
2685 #define DMA_CINT_CAIR_SHIFT 6
2686 #define DMA_CINT_NOP_MASK 0x80u
2687 #define DMA_CINT_NOP_SHIFT 7
2688 /* INT Bit Fields */
2689 #define DMA_INT_INT0_MASK 0x1u
2690 #define DMA_INT_INT0_SHIFT 0
2691 #define DMA_INT_INT1_MASK 0x2u
2692 #define DMA_INT_INT1_SHIFT 1
2693 #define DMA_INT_INT2_MASK 0x4u
2694 #define DMA_INT_INT2_SHIFT 2
2695 #define DMA_INT_INT3_MASK 0x8u
2696 #define DMA_INT_INT3_SHIFT 3
2697 #define DMA_INT_INT4_MASK 0x10u
2698 #define DMA_INT_INT4_SHIFT 4
2699 #define DMA_INT_INT5_MASK 0x20u
2700 #define DMA_INT_INT5_SHIFT 5
2701 #define DMA_INT_INT6_MASK 0x40u
2702 #define DMA_INT_INT6_SHIFT 6
2703 #define DMA_INT_INT7_MASK 0x80u
2704 #define DMA_INT_INT7_SHIFT 7
2705 #define DMA_INT_INT8_MASK 0x100u
2706 #define DMA_INT_INT8_SHIFT 8
2707 #define DMA_INT_INT9_MASK 0x200u
2708 #define DMA_INT_INT9_SHIFT 9
2709 #define DMA_INT_INT10_MASK 0x400u
2710 #define DMA_INT_INT10_SHIFT 10
2711 #define DMA_INT_INT11_MASK 0x800u
2712 #define DMA_INT_INT11_SHIFT 11
2713 #define DMA_INT_INT12_MASK 0x1000u
2714 #define DMA_INT_INT12_SHIFT 12
2715 #define DMA_INT_INT13_MASK 0x2000u
2716 #define DMA_INT_INT13_SHIFT 13
2717 #define DMA_INT_INT14_MASK 0x4000u
2718 #define DMA_INT_INT14_SHIFT 14
2719 #define DMA_INT_INT15_MASK 0x8000u
2720 #define DMA_INT_INT15_SHIFT 15
2721 /* ERR Bit Fields */
2722 #define DMA_ERR_ERR0_MASK 0x1u
2723 #define DMA_ERR_ERR0_SHIFT 0
2724 #define DMA_ERR_ERR1_MASK 0x2u
2725 #define DMA_ERR_ERR1_SHIFT 1
2726 #define DMA_ERR_ERR2_MASK 0x4u
2727 #define DMA_ERR_ERR2_SHIFT 2
2728 #define DMA_ERR_ERR3_MASK 0x8u
2729 #define DMA_ERR_ERR3_SHIFT 3
2730 #define DMA_ERR_ERR4_MASK 0x10u
2731 #define DMA_ERR_ERR4_SHIFT 4
2732 #define DMA_ERR_ERR5_MASK 0x20u
2733 #define DMA_ERR_ERR5_SHIFT 5
2734 #define DMA_ERR_ERR6_MASK 0x40u
2735 #define DMA_ERR_ERR6_SHIFT 6
2736 #define DMA_ERR_ERR7_MASK 0x80u
2737 #define DMA_ERR_ERR7_SHIFT 7
2738 #define DMA_ERR_ERR8_MASK 0x100u
2739 #define DMA_ERR_ERR8_SHIFT 8
2740 #define DMA_ERR_ERR9_MASK 0x200u
2741 #define DMA_ERR_ERR9_SHIFT 9
2742 #define DMA_ERR_ERR10_MASK 0x400u
2743 #define DMA_ERR_ERR10_SHIFT 10
2744 #define DMA_ERR_ERR11_MASK 0x800u
2745 #define DMA_ERR_ERR11_SHIFT 11
2746 #define DMA_ERR_ERR12_MASK 0x1000u
2747 #define DMA_ERR_ERR12_SHIFT 12
2748 #define DMA_ERR_ERR13_MASK 0x2000u
2749 #define DMA_ERR_ERR13_SHIFT 13
2750 #define DMA_ERR_ERR14_MASK 0x4000u
2751 #define DMA_ERR_ERR14_SHIFT 14
2752 #define DMA_ERR_ERR15_MASK 0x8000u
2753 #define DMA_ERR_ERR15_SHIFT 15
2754 /* HRS Bit Fields */
2755 #define DMA_HRS_HRS0_MASK 0x1u
2756 #define DMA_HRS_HRS0_SHIFT 0
2757 #define DMA_HRS_HRS1_MASK 0x2u
2758 #define DMA_HRS_HRS1_SHIFT 1
2759 #define DMA_HRS_HRS2_MASK 0x4u
2760 #define DMA_HRS_HRS2_SHIFT 2
2761 #define DMA_HRS_HRS3_MASK 0x8u
2762 #define DMA_HRS_HRS3_SHIFT 3
2763 #define DMA_HRS_HRS4_MASK 0x10u
2764 #define DMA_HRS_HRS4_SHIFT 4
2765 #define DMA_HRS_HRS5_MASK 0x20u
2766 #define DMA_HRS_HRS5_SHIFT 5
2767 #define DMA_HRS_HRS6_MASK 0x40u
2768 #define DMA_HRS_HRS6_SHIFT 6
2769 #define DMA_HRS_HRS7_MASK 0x80u
2770 #define DMA_HRS_HRS7_SHIFT 7
2771 #define DMA_HRS_HRS8_MASK 0x100u
2772 #define DMA_HRS_HRS8_SHIFT 8
2773 #define DMA_HRS_HRS9_MASK 0x200u
2774 #define DMA_HRS_HRS9_SHIFT 9
2775 #define DMA_HRS_HRS10_MASK 0x400u
2776 #define DMA_HRS_HRS10_SHIFT 10
2777 #define DMA_HRS_HRS11_MASK 0x800u
2778 #define DMA_HRS_HRS11_SHIFT 11
2779 #define DMA_HRS_HRS12_MASK 0x1000u
2780 #define DMA_HRS_HRS12_SHIFT 12
2781 #define DMA_HRS_HRS13_MASK 0x2000u
2782 #define DMA_HRS_HRS13_SHIFT 13
2783 #define DMA_HRS_HRS14_MASK 0x4000u
2784 #define DMA_HRS_HRS14_SHIFT 14
2785 #define DMA_HRS_HRS15_MASK 0x8000u
2786 #define DMA_HRS_HRS15_SHIFT 15
2787 /* DCHPRI3 Bit Fields */
2788 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
2789 #define DMA_DCHPRI3_CHPRI_SHIFT 0
2790 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
2791 #define DMA_DCHPRI3_DPA_MASK 0x40u
2792 #define DMA_DCHPRI3_DPA_SHIFT 6
2793 #define DMA_DCHPRI3_ECP_MASK 0x80u
2794 #define DMA_DCHPRI3_ECP_SHIFT 7
2795 /* DCHPRI2 Bit Fields */
2796 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
2797 #define DMA_DCHPRI2_CHPRI_SHIFT 0
2798 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
2799 #define DMA_DCHPRI2_DPA_MASK 0x40u
2800 #define DMA_DCHPRI2_DPA_SHIFT 6
2801 #define DMA_DCHPRI2_ECP_MASK 0x80u
2802 #define DMA_DCHPRI2_ECP_SHIFT 7
2803 /* DCHPRI1 Bit Fields */
2804 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
2805 #define DMA_DCHPRI1_CHPRI_SHIFT 0
2806 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
2807 #define DMA_DCHPRI1_DPA_MASK 0x40u
2808 #define DMA_DCHPRI1_DPA_SHIFT 6
2809 #define DMA_DCHPRI1_ECP_MASK 0x80u
2810 #define DMA_DCHPRI1_ECP_SHIFT 7
2811 /* DCHPRI0 Bit Fields */
2812 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
2813 #define DMA_DCHPRI0_CHPRI_SHIFT 0
2814 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
2815 #define DMA_DCHPRI0_DPA_MASK 0x40u
2816 #define DMA_DCHPRI0_DPA_SHIFT 6
2817 #define DMA_DCHPRI0_ECP_MASK 0x80u
2818 #define DMA_DCHPRI0_ECP_SHIFT 7
2819 /* DCHPRI7 Bit Fields */
2820 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
2821 #define DMA_DCHPRI7_CHPRI_SHIFT 0
2822 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
2823 #define DMA_DCHPRI7_DPA_MASK 0x40u
2824 #define DMA_DCHPRI7_DPA_SHIFT 6
2825 #define DMA_DCHPRI7_ECP_MASK 0x80u
2826 #define DMA_DCHPRI7_ECP_SHIFT 7
2827 /* DCHPRI6 Bit Fields */
2828 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
2829 #define DMA_DCHPRI6_CHPRI_SHIFT 0
2830 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
2831 #define DMA_DCHPRI6_DPA_MASK 0x40u
2832 #define DMA_DCHPRI6_DPA_SHIFT 6
2833 #define DMA_DCHPRI6_ECP_MASK 0x80u
2834 #define DMA_DCHPRI6_ECP_SHIFT 7
2835 /* DCHPRI5 Bit Fields */
2836 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
2837 #define DMA_DCHPRI5_CHPRI_SHIFT 0
2838 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
2839 #define DMA_DCHPRI5_DPA_MASK 0x40u
2840 #define DMA_DCHPRI5_DPA_SHIFT 6
2841 #define DMA_DCHPRI5_ECP_MASK 0x80u
2842 #define DMA_DCHPRI5_ECP_SHIFT 7
2843 /* DCHPRI4 Bit Fields */
2844 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
2845 #define DMA_DCHPRI4_CHPRI_SHIFT 0
2846 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
2847 #define DMA_DCHPRI4_DPA_MASK 0x40u
2848 #define DMA_DCHPRI4_DPA_SHIFT 6
2849 #define DMA_DCHPRI4_ECP_MASK 0x80u
2850 #define DMA_DCHPRI4_ECP_SHIFT 7
2851 /* DCHPRI11 Bit Fields */
2852 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
2853 #define DMA_DCHPRI11_CHPRI_SHIFT 0
2854 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
2855 #define DMA_DCHPRI11_DPA_MASK 0x40u
2856 #define DMA_DCHPRI11_DPA_SHIFT 6
2857 #define DMA_DCHPRI11_ECP_MASK 0x80u
2858 #define DMA_DCHPRI11_ECP_SHIFT 7
2859 /* DCHPRI10 Bit Fields */
2860 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
2861 #define DMA_DCHPRI10_CHPRI_SHIFT 0
2862 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
2863 #define DMA_DCHPRI10_DPA_MASK 0x40u
2864 #define DMA_DCHPRI10_DPA_SHIFT 6
2865 #define DMA_DCHPRI10_ECP_MASK 0x80u
2866 #define DMA_DCHPRI10_ECP_SHIFT 7
2867 /* DCHPRI9 Bit Fields */
2868 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
2869 #define DMA_DCHPRI9_CHPRI_SHIFT 0
2870 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
2871 #define DMA_DCHPRI9_DPA_MASK 0x40u
2872 #define DMA_DCHPRI9_DPA_SHIFT 6
2873 #define DMA_DCHPRI9_ECP_MASK 0x80u
2874 #define DMA_DCHPRI9_ECP_SHIFT 7
2875 /* DCHPRI8 Bit Fields */
2876 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
2877 #define DMA_DCHPRI8_CHPRI_SHIFT 0
2878 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
2879 #define DMA_DCHPRI8_DPA_MASK 0x40u
2880 #define DMA_DCHPRI8_DPA_SHIFT 6
2881 #define DMA_DCHPRI8_ECP_MASK 0x80u
2882 #define DMA_DCHPRI8_ECP_SHIFT 7
2883 /* DCHPRI15 Bit Fields */
2884 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
2885 #define DMA_DCHPRI15_CHPRI_SHIFT 0
2886 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
2887 #define DMA_DCHPRI15_DPA_MASK 0x40u
2888 #define DMA_DCHPRI15_DPA_SHIFT 6
2889 #define DMA_DCHPRI15_ECP_MASK 0x80u
2890 #define DMA_DCHPRI15_ECP_SHIFT 7
2891 /* DCHPRI14 Bit Fields */
2892 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
2893 #define DMA_DCHPRI14_CHPRI_SHIFT 0
2894 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
2895 #define DMA_DCHPRI14_DPA_MASK 0x40u
2896 #define DMA_DCHPRI14_DPA_SHIFT 6
2897 #define DMA_DCHPRI14_ECP_MASK 0x80u
2898 #define DMA_DCHPRI14_ECP_SHIFT 7
2899 /* DCHPRI13 Bit Fields */
2900 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
2901 #define DMA_DCHPRI13_CHPRI_SHIFT 0
2902 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
2903 #define DMA_DCHPRI13_DPA_MASK 0x40u
2904 #define DMA_DCHPRI13_DPA_SHIFT 6
2905 #define DMA_DCHPRI13_ECP_MASK 0x80u
2906 #define DMA_DCHPRI13_ECP_SHIFT 7
2907 /* DCHPRI12 Bit Fields */
2908 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
2909 #define DMA_DCHPRI12_CHPRI_SHIFT 0
2910 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
2911 #define DMA_DCHPRI12_DPA_MASK 0x40u
2912 #define DMA_DCHPRI12_DPA_SHIFT 6
2913 #define DMA_DCHPRI12_ECP_MASK 0x80u
2914 #define DMA_DCHPRI12_ECP_SHIFT 7
2915 /* SADDR Bit Fields */
2916 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
2917 #define DMA_SADDR_SADDR_SHIFT 0
2918 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
2919 /* SOFF Bit Fields */
2920 #define DMA_SOFF_SOFF_MASK 0xFFFFu
2921 #define DMA_SOFF_SOFF_SHIFT 0
2922 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
2923 /* ATTR Bit Fields */
2924 #define DMA_ATTR_DSIZE_MASK 0x7u
2925 #define DMA_ATTR_DSIZE_SHIFT 0
2926 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
2927 #define DMA_ATTR_DMOD_MASK 0xF8u
2928 #define DMA_ATTR_DMOD_SHIFT 3
2929 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
2930 #define DMA_ATTR_SSIZE_MASK 0x700u
2931 #define DMA_ATTR_SSIZE_SHIFT 8
2932 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
2933 #define DMA_ATTR_SMOD_MASK 0xF800u
2934 #define DMA_ATTR_SMOD_SHIFT 11
2935 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
2936 /* NBYTES_MLNO Bit Fields */
2937 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
2938 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
2939 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
2940 /* NBYTES_MLOFFNO Bit Fields */
2941 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
2942 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
2943 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
2944 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
2945 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
2946 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
2947 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
2948 /* NBYTES_MLOFFYES Bit Fields */
2949 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
2950 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
2951 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
2952 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
2953 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
2954 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
2955 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
2956 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
2957 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
2958 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
2959 /* SLAST Bit Fields */
2960 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
2961 #define DMA_SLAST_SLAST_SHIFT 0
2962 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
2963 /* DADDR Bit Fields */
2964 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
2965 #define DMA_DADDR_DADDR_SHIFT 0
2966 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
2967 /* DOFF Bit Fields */
2968 #define DMA_DOFF_DOFF_MASK 0xFFFFu
2969 #define DMA_DOFF_DOFF_SHIFT 0
2970 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
2971 /* CITER_ELINKNO Bit Fields */
2972 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
2973 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
2974 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
2975 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
2976 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
2977 /* CITER_ELINKYES Bit Fields */
2978 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
2979 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
2980 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
2981 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
2982 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
2983 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
2984 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
2985 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
2986 /* DLAST_SGA Bit Fields */
2987 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
2988 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
2989 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
2990 /* CSR Bit Fields */
2991 #define DMA_CSR_START_MASK 0x1u
2992 #define DMA_CSR_START_SHIFT 0
2993 #define DMA_CSR_INTMAJOR_MASK 0x2u
2994 #define DMA_CSR_INTMAJOR_SHIFT 1
2995 #define DMA_CSR_INTHALF_MASK 0x4u
2996 #define DMA_CSR_INTHALF_SHIFT 2
2997 #define DMA_CSR_DREQ_MASK 0x8u
2998 #define DMA_CSR_DREQ_SHIFT 3
2999 #define DMA_CSR_ESG_MASK 0x10u
3000 #define DMA_CSR_ESG_SHIFT 4
3001 #define DMA_CSR_MAJORELINK_MASK 0x20u
3002 #define DMA_CSR_MAJORELINK_SHIFT 5
3003 #define DMA_CSR_ACTIVE_MASK 0x40u
3004 #define DMA_CSR_ACTIVE_SHIFT 6
3005 #define DMA_CSR_DONE_MASK 0x80u
3006 #define DMA_CSR_DONE_SHIFT 7
3007 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
3008 #define DMA_CSR_MAJORLINKCH_SHIFT 8
3009 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
3010 #define DMA_CSR_BWC_MASK 0xC000u
3011 #define DMA_CSR_BWC_SHIFT 14
3012 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
3013 /* BITER_ELINKNO Bit Fields */
3014 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
3015 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
3016 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
3017 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
3018 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
3019 /* BITER_ELINKYES Bit Fields */
3020 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
3021 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
3022 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
3023 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
3024 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
3025 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
3026 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
3027 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
3028 
3029 /**
3030  * @}
3031  */ /* end of group DMA_Register_Masks */
3032 
3033 
3034 /* DMA - Peripheral instance base addresses */
3035 /** Peripheral DMA base address */
3036 #define DMA_BASE (0x40008000u)
3037 /** Peripheral DMA base pointer */
3038 #define DMA0 ((DMA_Type *)DMA_BASE)
3039 
3040 /**
3041  * @}
3042  */ /* end of group DMA_Peripheral_Access_Layer */
3043 
3044 
3045 /* ----------------------------------------------------------------------------
3046  -- DMAMUX Peripheral Access Layer
3047  ---------------------------------------------------------------------------- */
3048 
3049 /**
3050  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
3051  * @{
3052  */
3053 
3054 /** DMAMUX - Register Layout Typedef */
3055 typedef struct {
3056  __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
3057 } DMAMUX_Type;
3058 
3059 /* ----------------------------------------------------------------------------
3060  -- DMAMUX Register Masks
3061  ---------------------------------------------------------------------------- */
3062 
3063 /**
3064  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
3065  * @{
3066  */
3067 
3068 /* CHCFG Bit Fields */
3069 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
3070 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
3071 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
3072 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
3073 #define DMAMUX_CHCFG_TRIG_SHIFT 6
3074 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
3075 #define DMAMUX_CHCFG_ENBL_SHIFT 7
3076 
3077 /**
3078  * @}
3079  */ /* end of group DMAMUX_Register_Masks */
3080 
3081 
3082 /* DMAMUX - Peripheral instance base addresses */
3083 /** Peripheral DMAMUX base address */
3084 #define DMAMUX_BASE (0x40021000u)
3085 /** Peripheral DMAMUX base pointer */
3086 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3087 
3088 /**
3089  * @}
3090  */ /* end of group DMAMUX_Peripheral_Access_Layer */
3091 
3092 
3093 /* ----------------------------------------------------------------------------
3094  -- ENET Peripheral Access Layer
3095  ---------------------------------------------------------------------------- */
3096 
3097 /**
3098  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
3099  * @{
3100  */
3101 
3102 /** ENET - Register Layout Typedef */
3103 typedef struct {
3104  uint8_t RESERVED_0[4];
3105  __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
3106  __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
3107  uint8_t RESERVED_1[4];
3108  __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
3109  __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
3110  uint8_t RESERVED_2[12];
3111  __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
3112  uint8_t RESERVED_3[24];
3113  __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
3114  __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
3115  uint8_t RESERVED_4[28];
3116  __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
3117  uint8_t RESERVED_5[28];
3118  __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
3119  uint8_t RESERVED_6[60];
3120  __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
3121  uint8_t RESERVED_7[28];
3122  __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
3123  __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
3124  __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
3125  uint8_t RESERVED_8[40];
3126  __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
3127  __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
3128  __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
3129  __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
3130  uint8_t RESERVED_9[28];
3131  __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
3132  uint8_t RESERVED_10[56];
3133  __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
3134  __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
3135  __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
3136  uint8_t RESERVED_11[4];
3137  __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
3138  __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
3139  __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
3140  __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
3141  __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
3142  __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
3143  __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
3144  __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
3145  __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
3146  uint8_t RESERVED_12[12];
3147  __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
3148  __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
3149  uint8_t RESERVED_13[56];
3150  __IO uint32_t RMON_T_DROP; /**< Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200 */
3151  __IO uint32_t RMON_T_PACKETS; /**< RMON Tx packet count (RMON_T_PACKETS), offset: 0x204 */
3152  __IO uint32_t RMON_T_BC_PKT; /**< RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208 */
3153  __IO uint32_t RMON_T_MC_PKT; /**< RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C */
3154  __IO uint32_t RMON_T_CRC_ALIGN; /**< RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210 */
3155  __IO uint32_t RMON_T_UNDERSIZE; /**< RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214 */
3156  __IO uint32_t RMON_T_OVERSIZE; /**< RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */
3157  __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */
3158  __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */
3159  __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */
3160  __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */
3161  __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */
3162  __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */
3163  __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */
3164  __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */
3165  __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */
3166  __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */
3167  __IO uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */
3168  __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */
3169  __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */
3170  __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */
3171  __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */
3172  __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */
3173  __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */
3174  __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */
3175  __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */
3176  __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */
3177  __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */
3178  __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */
3179  __IO uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */
3180  uint8_t RESERVED_14[12];
3181  __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */
3182  __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */
3183  __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */
3184  __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */
3185  __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */
3186  __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */
3187  __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */
3188  __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */
3189  __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */
3190  __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */
3191  __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */
3192  __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */
3193  __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */
3194  __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */
3195  __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */
3196  __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */
3197  __IO uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */
3198  __IO uint32_t RMON_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */
3199  __IO uint32_t RMON_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */
3200  __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */
3201  __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */
3202  __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */
3203  __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */
3204  __IO uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */
3205  uint8_t RESERVED_15[284];
3206  __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */
3207  __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
3208  __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
3209  __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
3210  __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
3211  __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
3212  __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
3213  uint8_t RESERVED_16[488];
3214  __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
3215  struct { /* offset: 0x608, array step: 0x8 */
3216  __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
3217  __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
3218  } CHANNEL[4];
3219 } ENET_Type;
3220 
3221 /* ----------------------------------------------------------------------------
3222  -- ENET Register Masks
3223  ---------------------------------------------------------------------------- */
3224 
3225 /**
3226  * @addtogroup ENET_Register_Masks ENET Register Masks
3227  * @{
3228  */
3229 
3230 /* EIR Bit Fields */
3231 #define ENET_EIR_TS_TIMER_MASK 0x8000u
3232 #define ENET_EIR_TS_TIMER_SHIFT 15
3233 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
3234 #define ENET_EIR_TS_AVAIL_SHIFT 16
3235 #define ENET_EIR_WAKEUP_MASK 0x20000u
3236 #define ENET_EIR_WAKEUP_SHIFT 17
3237 #define ENET_EIR_PLR_MASK 0x40000u
3238 #define ENET_EIR_PLR_SHIFT 18
3239 #define ENET_EIR_UN_MASK 0x80000u
3240 #define ENET_EIR_UN_SHIFT 19
3241 #define ENET_EIR_RL_MASK 0x100000u
3242 #define ENET_EIR_RL_SHIFT 20
3243 #define ENET_EIR_LC_MASK 0x200000u
3244 #define ENET_EIR_LC_SHIFT 21
3245 #define ENET_EIR_EBERR_MASK 0x400000u
3246 #define ENET_EIR_EBERR_SHIFT 22
3247 #define ENET_EIR_MII_MASK 0x800000u
3248 #define ENET_EIR_MII_SHIFT 23
3249 #define ENET_EIR_RXB_MASK 0x1000000u
3250 #define ENET_EIR_RXB_SHIFT 24
3251 #define ENET_EIR_RXF_MASK 0x2000000u
3252 #define ENET_EIR_RXF_SHIFT 25
3253 #define ENET_EIR_TXB_MASK 0x4000000u
3254 #define ENET_EIR_TXB_SHIFT 26
3255 #define ENET_EIR_TXF_MASK 0x8000000u
3256 #define ENET_EIR_TXF_SHIFT 27
3257 #define ENET_EIR_GRA_MASK 0x10000000u
3258 #define ENET_EIR_GRA_SHIFT 28
3259 #define ENET_EIR_BABT_MASK 0x20000000u
3260 #define ENET_EIR_BABT_SHIFT 29
3261 #define ENET_EIR_BABR_MASK 0x40000000u
3262 #define ENET_EIR_BABR_SHIFT 30
3263 /* EIMR Bit Fields */
3264 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
3265 #define ENET_EIMR_TS_TIMER_SHIFT 15
3266 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
3267 #define ENET_EIMR_TS_AVAIL_SHIFT 16
3268 #define ENET_EIMR_WAKEUP_MASK 0x20000u
3269 #define ENET_EIMR_WAKEUP_SHIFT 17
3270 #define ENET_EIMR_PLR_MASK 0x40000u
3271 #define ENET_EIMR_PLR_SHIFT 18
3272 #define ENET_EIMR_UN_MASK 0x80000u
3273 #define ENET_EIMR_UN_SHIFT 19
3274 #define ENET_EIMR_RL_MASK 0x100000u
3275 #define ENET_EIMR_RL_SHIFT 20
3276 #define ENET_EIMR_LC_MASK 0x200000u
3277 #define ENET_EIMR_LC_SHIFT 21
3278 #define ENET_EIMR_EBERR_MASK 0x400000u
3279 #define ENET_EIMR_EBERR_SHIFT 22
3280 #define ENET_EIMR_MII_MASK 0x800000u
3281 #define ENET_EIMR_MII_SHIFT 23
3282 #define ENET_EIMR_RXB_MASK 0x1000000u
3283 #define ENET_EIMR_RXB_SHIFT 24
3284 #define ENET_EIMR_RXF_MASK 0x2000000u
3285 #define ENET_EIMR_RXF_SHIFT 25
3286 #define ENET_EIMR_TXB_MASK 0x4000000u
3287 #define ENET_EIMR_TXB_SHIFT 26
3288 #define ENET_EIMR_TXF_MASK 0x8000000u
3289 #define ENET_EIMR_TXF_SHIFT 27
3290 #define ENET_EIMR_GRA_MASK 0x10000000u
3291 #define ENET_EIMR_GRA_SHIFT 28
3292 #define ENET_EIMR_BABT_MASK 0x20000000u
3293 #define ENET_EIMR_BABT_SHIFT 29
3294 #define ENET_EIMR_BABR_MASK 0x40000000u
3295 #define ENET_EIMR_BABR_SHIFT 30
3296 /* RDAR Bit Fields */
3297 #define ENET_RDAR_RDAR_MASK 0x1000000u
3298 #define ENET_RDAR_RDAR_SHIFT 24
3299 /* TDAR Bit Fields */
3300 #define ENET_TDAR_TDAR_MASK 0x1000000u
3301 #define ENET_TDAR_TDAR_SHIFT 24
3302 /* ECR Bit Fields */
3303 #define ENET_ECR_RESET_MASK 0x1u
3304 #define ENET_ECR_RESET_SHIFT 0
3305 #define ENET_ECR_ETHEREN_MASK 0x2u
3306 #define ENET_ECR_ETHEREN_SHIFT 1
3307 #define ENET_ECR_MAGICEN_MASK 0x4u
3308 #define ENET_ECR_MAGICEN_SHIFT 2
3309 #define ENET_ECR_SLEEP_MASK 0x8u
3310 #define ENET_ECR_SLEEP_SHIFT 3
3311 #define ENET_ECR_EN1588_MASK 0x10u
3312 #define ENET_ECR_EN1588_SHIFT 4
3313 #define ENET_ECR_DBGEN_MASK 0x40u
3314 #define ENET_ECR_DBGEN_SHIFT 6
3315 #define ENET_ECR_STOPEN_MASK 0x80u
3316 #define ENET_ECR_STOPEN_SHIFT 7
3317 /* MMFR Bit Fields */
3318 #define ENET_MMFR_DATA_MASK 0xFFFFu
3319 #define ENET_MMFR_DATA_SHIFT 0
3320 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
3321 #define ENET_MMFR_TA_MASK 0x30000u
3322 #define ENET_MMFR_TA_SHIFT 16
3323 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
3324 #define ENET_MMFR_RA_MASK 0x7C0000u
3325 #define ENET_MMFR_RA_SHIFT 18
3326 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
3327 #define ENET_MMFR_PA_MASK 0xF800000u
3328 #define ENET_MMFR_PA_SHIFT 23
3329 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
3330 #define ENET_MMFR_OP_MASK 0x30000000u
3331 #define ENET_MMFR_OP_SHIFT 28
3332 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
3333 #define ENET_MMFR_ST_MASK 0xC0000000u
3334 #define ENET_MMFR_ST_SHIFT 30
3335 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
3336 /* MSCR Bit Fields */
3337 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
3338 #define ENET_MSCR_MII_SPEED_SHIFT 1
3339 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
3340 #define ENET_MSCR_DIS_PRE_MASK 0x80u
3341 #define ENET_MSCR_DIS_PRE_SHIFT 7
3342 #define ENET_MSCR_HOLDTIME_MASK 0x700u
3343 #define ENET_MSCR_HOLDTIME_SHIFT 8
3344 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
3345 /* MIBC Bit Fields */
3346 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
3347 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
3348 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
3349 #define ENET_MIBC_MIB_IDLE_SHIFT 30
3350 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
3351 #define ENET_MIBC_MIB_DIS_SHIFT 31
3352 /* RCR Bit Fields */
3353 #define ENET_RCR_LOOP_MASK 0x1u
3354 #define ENET_RCR_LOOP_SHIFT 0
3355 #define ENET_RCR_DRT_MASK 0x2u
3356 #define ENET_RCR_DRT_SHIFT 1
3357 #define ENET_RCR_MII_MODE_MASK 0x4u
3358 #define ENET_RCR_MII_MODE_SHIFT 2
3359 #define ENET_RCR_PROM_MASK 0x8u
3360 #define ENET_RCR_PROM_SHIFT 3
3361 #define ENET_RCR_BC_REJ_MASK 0x10u
3362 #define ENET_RCR_BC_REJ_SHIFT 4
3363 #define ENET_RCR_FCE_MASK 0x20u
3364 #define ENET_RCR_FCE_SHIFT 5
3365 #define ENET_RCR_RMII_MODE_MASK 0x100u
3366 #define ENET_RCR_RMII_MODE_SHIFT 8
3367 #define ENET_RCR_RMII_10T_MASK 0x200u
3368 #define ENET_RCR_RMII_10T_SHIFT 9
3369 #define ENET_RCR_PADEN_MASK 0x1000u
3370 #define ENET_RCR_PADEN_SHIFT 12
3371 #define ENET_RCR_PAUFWD_MASK 0x2000u
3372 #define ENET_RCR_PAUFWD_SHIFT 13
3373 #define ENET_RCR_CRCFWD_MASK 0x4000u
3374 #define ENET_RCR_CRCFWD_SHIFT 14
3375 #define ENET_RCR_CFEN_MASK 0x8000u
3376 #define ENET_RCR_CFEN_SHIFT 15
3377 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
3378 #define ENET_RCR_MAX_FL_SHIFT 16
3379 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
3380 #define ENET_RCR_NLC_MASK 0x40000000u
3381 #define ENET_RCR_NLC_SHIFT 30
3382 #define ENET_RCR_GRS_MASK 0x80000000u
3383 #define ENET_RCR_GRS_SHIFT 31
3384 /* TCR Bit Fields */
3385 #define ENET_TCR_GTS_MASK 0x1u
3386 #define ENET_TCR_GTS_SHIFT 0
3387 #define ENET_TCR_FDEN_MASK 0x4u
3388 #define ENET_TCR_FDEN_SHIFT 2
3389 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
3390 #define ENET_TCR_TFC_PAUSE_SHIFT 3
3391 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
3392 #define ENET_TCR_RFC_PAUSE_SHIFT 4
3393 #define ENET_TCR_ADDSEL_MASK 0xE0u
3394 #define ENET_TCR_ADDSEL_SHIFT 5
3395 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
3396 #define ENET_TCR_ADDINS_MASK 0x100u
3397 #define ENET_TCR_ADDINS_SHIFT 8
3398 #define ENET_TCR_CRCFWD_MASK 0x200u
3399 #define ENET_TCR_CRCFWD_SHIFT 9
3400 /* PALR Bit Fields */
3401 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
3402 #define ENET_PALR_PADDR1_SHIFT 0
3403 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
3404 /* PAUR Bit Fields */
3405 #define ENET_PAUR_TYPE_MASK 0xFFFFu
3406 #define ENET_PAUR_TYPE_SHIFT 0
3407 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
3408 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
3409 #define ENET_PAUR_PADDR2_SHIFT 16
3410 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
3411 /* OPD Bit Fields */
3412 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
3413 #define ENET_OPD_PAUSE_DUR_SHIFT 0
3414 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
3415 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
3416 #define ENET_OPD_OPCODE_SHIFT 16
3417 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
3418 /* IAUR Bit Fields */
3419 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
3420 #define ENET_IAUR_IADDR1_SHIFT 0
3421 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
3422 /* IALR Bit Fields */
3423 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
3424 #define ENET_IALR_IADDR2_SHIFT 0
3425 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
3426 /* GAUR Bit Fields */
3427 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
3428 #define ENET_GAUR_GADDR1_SHIFT 0
3429 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
3430 /* GALR Bit Fields */
3431 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
3432 #define ENET_GALR_GADDR2_SHIFT 0
3433 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
3434 /* TFWR Bit Fields */
3435 #define ENET_TFWR_TFWR_MASK 0x3Fu
3436 #define ENET_TFWR_TFWR_SHIFT 0
3437 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
3438 #define ENET_TFWR_STRFWD_MASK 0x100u
3439 #define ENET_TFWR_STRFWD_SHIFT 8
3440 /* RDSR Bit Fields */
3441 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
3442 #define ENET_RDSR_R_DES_START_SHIFT 3
3443 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
3444 /* TDSR Bit Fields */
3445 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
3446 #define ENET_TDSR_X_DES_START_SHIFT 3
3447 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
3448 /* MRBR Bit Fields */
3449 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
3450 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
3451 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
3452 /* RSFL Bit Fields */
3453 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
3454 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
3455 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
3456 /* RSEM Bit Fields */
3457 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
3458 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
3459 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
3460 /* RAEM Bit Fields */
3461 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
3462 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
3463 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
3464 /* RAFL Bit Fields */
3465 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
3466 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
3467 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
3468 /* TSEM Bit Fields */
3469 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
3470 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
3471 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
3472 /* TAEM Bit Fields */
3473 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
3474 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
3475 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
3476 /* TAFL Bit Fields */
3477 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
3478 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
3479 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
3480 /* TIPG Bit Fields */
3481 #define ENET_TIPG_IPG_MASK 0x1Fu
3482 #define ENET_TIPG_IPG_SHIFT 0
3483 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
3484 /* FTRL Bit Fields */
3485 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
3486 #define ENET_FTRL_TRUNC_FL_SHIFT 0
3487 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
3488 /* TACC Bit Fields */
3489 #define ENET_TACC_SHIFT16_MASK 0x1u
3490 #define ENET_TACC_SHIFT16_SHIFT 0
3491 #define ENET_TACC_IPCHK_MASK 0x8u
3492 #define ENET_TACC_IPCHK_SHIFT 3
3493 #define ENET_TACC_PROCHK_MASK 0x10u
3494 #define ENET_TACC_PROCHK_SHIFT 4
3495 /* RACC Bit Fields */
3496 #define ENET_RACC_PADREM_MASK 0x1u
3497 #define ENET_RACC_PADREM_SHIFT 0
3498 #define ENET_RACC_IPDIS_MASK 0x2u
3499 #define ENET_RACC_IPDIS_SHIFT 1
3500 #define ENET_RACC_PRODIS_MASK 0x4u
3501 #define ENET_RACC_PRODIS_SHIFT 2
3502 #define ENET_RACC_LINEDIS_MASK 0x40u
3503 #define ENET_RACC_LINEDIS_SHIFT 6
3504 #define ENET_RACC_SHIFT16_MASK 0x80u
3505 #define ENET_RACC_SHIFT16_SHIFT 7
3506 /* ATCR Bit Fields */
3507 #define ENET_ATCR_EN_MASK 0x1u
3508 #define ENET_ATCR_EN_SHIFT 0
3509 #define ENET_ATCR_OFFEN_MASK 0x4u
3510 #define ENET_ATCR_OFFEN_SHIFT 2
3511 #define ENET_ATCR_OFFRST_MASK 0x8u
3512 #define ENET_ATCR_OFFRST_SHIFT 3
3513 #define ENET_ATCR_PEREN_MASK 0x10u
3514 #define ENET_ATCR_PEREN_SHIFT 4
3515 #define ENET_ATCR_PINPER_MASK 0x80u
3516 #define ENET_ATCR_PINPER_SHIFT 7
3517 #define ENET_ATCR_RESTART_MASK 0x200u
3518 #define ENET_ATCR_RESTART_SHIFT 9
3519 #define ENET_ATCR_CAPTURE_MASK 0x800u
3520 #define ENET_ATCR_CAPTURE_SHIFT 11
3521 #define ENET_ATCR_SLAVE_MASK 0x2000u
3522 #define ENET_ATCR_SLAVE_SHIFT 13
3523 /* ATVR Bit Fields */
3524 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
3525 #define ENET_ATVR_ATIME_SHIFT 0
3526 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
3527 /* ATOFF Bit Fields */
3528 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
3529 #define ENET_ATOFF_OFFSET_SHIFT 0
3530 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
3531 /* ATPER Bit Fields */
3532 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
3533 #define ENET_ATPER_PERIOD_SHIFT 0
3534 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
3535 /* ATCOR Bit Fields */
3536 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
3537 #define ENET_ATCOR_COR_SHIFT 0
3538 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
3539 /* ATINC Bit Fields */
3540 #define ENET_ATINC_INC_MASK 0x7Fu
3541 #define ENET_ATINC_INC_SHIFT 0
3542 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
3543 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
3544 #define ENET_ATINC_INC_CORR_SHIFT 8
3545 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
3546 /* ATSTMP Bit Fields */
3547 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
3548 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
3549 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
3550 /* TGSR Bit Fields */
3551 #define ENET_TGSR_TF0_MASK 0x1u
3552 #define ENET_TGSR_TF0_SHIFT 0
3553 #define ENET_TGSR_TF1_MASK 0x2u
3554 #define ENET_TGSR_TF1_SHIFT 1
3555 #define ENET_TGSR_TF2_MASK 0x4u
3556 #define ENET_TGSR_TF2_SHIFT 2
3557 #define ENET_TGSR_TF3_MASK 0x8u
3558 #define ENET_TGSR_TF3_SHIFT 3
3559 /* TCSR Bit Fields */
3560 #define ENET_TCSR_TDRE_MASK 0x1u
3561 #define ENET_TCSR_TDRE_SHIFT 0
3562 #define ENET_TCSR_TMODE_MASK 0x3Cu
3563 #define ENET_TCSR_TMODE_SHIFT 2
3564 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
3565 #define ENET_TCSR_TIE_MASK 0x40u
3566 #define ENET_TCSR_TIE_SHIFT 6
3567 #define ENET_TCSR_TF_MASK 0x80u
3568 #define ENET_TCSR_TF_SHIFT 7
3569 /* TCCR Bit Fields */
3570 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
3571 #define ENET_TCCR_TCC_SHIFT 0
3572 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
3573 
3574 /**
3575  * @}
3576  */ /* end of group ENET_Register_Masks */
3577 
3578 
3579 /* ENET - Peripheral instance base addresses */
3580 /** Peripheral ENET base address */
3581 #define ENET_BASE (0x400C0000u)
3582 /** Peripheral ENET base pointer */
3583 #define ENET ((ENET_Type *)ENET_BASE)
3584 
3585 /**
3586  * @}
3587  */ /* end of group ENET_Peripheral_Access_Layer */
3588 
3589 
3590 /* ----------------------------------------------------------------------------
3591  -- EWM Peripheral Access Layer
3592  ---------------------------------------------------------------------------- */
3593 
3594 /**
3595  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
3596  * @{
3597  */
3598 
3599 /** EWM - Register Layout Typedef */
3600 typedef struct {
3601  __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
3602  __O uint8_t SERV; /**< Service Register, offset: 0x1 */
3603  __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
3604  __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
3605 } EWM_Type;
3606 
3607 /* ----------------------------------------------------------------------------
3608  -- EWM Register Masks
3609  ---------------------------------------------------------------------------- */
3610 
3611 /**
3612  * @addtogroup EWM_Register_Masks EWM Register Masks
3613  * @{
3614  */
3615 
3616 /* CTRL Bit Fields */
3617 #define EWM_CTRL_EWMEN_MASK 0x1u
3618 #define EWM_CTRL_EWMEN_SHIFT 0
3619 #define EWM_CTRL_ASSIN_MASK 0x2u
3620 #define EWM_CTRL_ASSIN_SHIFT 1
3621 #define EWM_CTRL_INEN_MASK 0x4u
3622 #define EWM_CTRL_INEN_SHIFT 2
3623 /* SERV Bit Fields */
3624 #define EWM_SERV_SERVICE_MASK 0xFFu
3625 #define EWM_SERV_SERVICE_SHIFT 0
3626 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
3627 /* CMPL Bit Fields */
3628 #define EWM_CMPL_COMPAREL_MASK 0xFFu
3629 #define EWM_CMPL_COMPAREL_SHIFT 0
3630 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
3631 /* CMPH Bit Fields */
3632 #define EWM_CMPH_COMPAREH_MASK 0xFFu
3633 #define EWM_CMPH_COMPAREH_SHIFT 0
3634 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
3635 
3636 /**
3637  * @}
3638  */ /* end of group EWM_Register_Masks */
3639 
3640 
3641 /* EWM - Peripheral instance base addresses */
3642 /** Peripheral EWM base address */
3643 #define EWM_BASE (0x40061000u)
3644 /** Peripheral EWM base pointer */
3645 #define EWM ((EWM_Type *)EWM_BASE)
3646 
3647 /**
3648  * @}
3649  */ /* end of group EWM_Peripheral_Access_Layer */
3650 
3651 
3652 /* ----------------------------------------------------------------------------
3653  -- FB Peripheral Access Layer
3654  ---------------------------------------------------------------------------- */
3655 
3656 /**
3657  * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
3658  * @{
3659  */
3660 
3661 /** FB - Register Layout Typedef */
3662 typedef struct {
3663  struct { /* offset: 0x0, array step: 0xC */
3664  __IO uint32_t CSAR; /**< Chip select address register, array offset: 0x0, array step: 0xC */
3665  __IO uint32_t CSMR; /**< Chip select mask register, array offset: 0x4, array step: 0xC */
3666  __IO uint32_t CSCR; /**< Chip select control register, array offset: 0x8, array step: 0xC */
3667  } CS[6];
3668  uint8_t RESERVED_0[24];
3669  __IO uint32_t CSPMCR; /**< Chip select port multiplexing control register, offset: 0x60 */
3670 } FB_Type;
3671 
3672 /* ----------------------------------------------------------------------------
3673  -- FB Register Masks
3674  ---------------------------------------------------------------------------- */
3675 
3676 /**
3677  * @addtogroup FB_Register_Masks FB Register Masks
3678  * @{
3679  */
3680 
3681 /* CSAR Bit Fields */
3682 #define FB_CSAR_BA_MASK 0xFFFF0000u
3683 #define FB_CSAR_BA_SHIFT 16
3684 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
3685 /* CSMR Bit Fields */
3686 #define FB_CSMR_V_MASK 0x1u
3687 #define FB_CSMR_V_SHIFT 0
3688 #define FB_CSMR_WP_MASK 0x100u
3689 #define FB_CSMR_WP_SHIFT 8
3690 #define FB_CSMR_BAM_MASK 0xFFFF0000u
3691 #define FB_CSMR_BAM_SHIFT 16
3692 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
3693 /* CSCR Bit Fields */
3694 #define FB_CSCR_BSTW_MASK 0x8u
3695 #define FB_CSCR_BSTW_SHIFT 3
3696 #define FB_CSCR_BSTR_MASK 0x10u
3697 #define FB_CSCR_BSTR_SHIFT 4
3698 #define FB_CSCR_BEM_MASK 0x20u
3699 #define FB_CSCR_BEM_SHIFT 5
3700 #define FB_CSCR_PS_MASK 0xC0u
3701 #define FB_CSCR_PS_SHIFT 6
3702 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
3703 #define FB_CSCR_AA_MASK 0x100u
3704 #define FB_CSCR_AA_SHIFT 8
3705 #define FB_CSCR_BLS_MASK 0x200u
3706 #define FB_CSCR_BLS_SHIFT 9
3707 #define FB_CSCR_WS_MASK 0xFC00u
3708 #define FB_CSCR_WS_SHIFT 10
3709 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
3710 #define FB_CSCR_WRAH_MASK 0x30000u
3711 #define FB_CSCR_WRAH_SHIFT 16
3712 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
3713 #define FB_CSCR_RDAH_MASK 0xC0000u
3714 #define FB_CSCR_RDAH_SHIFT 18
3715 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
3716 #define FB_CSCR_ASET_MASK 0x300000u
3717 #define FB_CSCR_ASET_SHIFT 20
3718 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
3719 #define FB_CSCR_EXTS_MASK 0x400000u
3720 #define FB_CSCR_EXTS_SHIFT 22
3721 #define FB_CSCR_SWSEN_MASK 0x800000u
3722 #define FB_CSCR_SWSEN_SHIFT 23
3723 #define FB_CSCR_SWS_MASK 0xFC000000u
3724 #define FB_CSCR_SWS_SHIFT 26
3725 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
3726 /* CSPMCR Bit Fields */
3727 #define FB_CSPMCR_GROUP5_MASK 0xF000u
3728 #define FB_CSPMCR_GROUP5_SHIFT 12
3729 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
3730 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
3731 #define FB_CSPMCR_GROUP4_SHIFT 16
3732 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
3733 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
3734 #define FB_CSPMCR_GROUP3_SHIFT 20
3735 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
3736 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
3737 #define FB_CSPMCR_GROUP2_SHIFT 24
3738 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
3739 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
3740 #define FB_CSPMCR_GROUP1_SHIFT 28
3741 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
3742 
3743 /**
3744  * @}
3745  */ /* end of group FB_Register_Masks */
3746 
3747 
3748 /* FB - Peripheral instance base addresses */
3749 /** Peripheral FB base address */
3750 #define FB_BASE (0x4000C000u)
3751 /** Peripheral FB base pointer */
3752 #define FB ((FB_Type *)FB_BASE)
3753 
3754 /**
3755  * @}
3756  */ /* end of group FB_Peripheral_Access_Layer */
3757 
3758 
3759 /* ----------------------------------------------------------------------------
3760  -- FMC Peripheral Access Layer
3761  ---------------------------------------------------------------------------- */
3762 
3763 /**
3764  * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
3765  * @{
3766  */
3767 
3768 /** FMC - Register Layout Typedef */
3769 typedef struct {
3770  __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
3771  __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
3772  __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
3773  uint8_t RESERVED_0[244];
3774  __IO uint32_t TAGVD[4][8]; /**< Cache Directory Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
3775  uint8_t RESERVED_1[128];
3776  struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
3777  __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
3778  __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
3779  } SET[4][8];
3780 } FMC_Type;
3781 
3782 /* ----------------------------------------------------------------------------
3783  -- FMC Register Masks
3784  ---------------------------------------------------------------------------- */
3785 
3786 /**
3787  * @addtogroup FMC_Register_Masks FMC Register Masks
3788  * @{
3789  */
3790 
3791 /* PFAPR Bit Fields */
3792 #define FMC_PFAPR_M0AP_MASK 0x3u
3793 #define FMC_PFAPR_M0AP_SHIFT 0
3794 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
3795 #define FMC_PFAPR_M1AP_MASK 0xCu
3796 #define FMC_PFAPR_M1AP_SHIFT 2
3797 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
3798 #define FMC_PFAPR_M2AP_MASK 0x30u
3799 #define FMC_PFAPR_M2AP_SHIFT 4
3800 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
3801 #define FMC_PFAPR_M3AP_MASK 0xC0u
3802 #define FMC_PFAPR_M3AP_SHIFT 6
3803 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
3804 #define FMC_PFAPR_M4AP_MASK 0x300u
3805 #define FMC_PFAPR_M4AP_SHIFT 8
3806 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
3807 #define FMC_PFAPR_M5AP_MASK 0xC00u
3808 #define FMC_PFAPR_M5AP_SHIFT 10
3809 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
3810 #define FMC_PFAPR_M6AP_MASK 0x3000u
3811 #define FMC_PFAPR_M6AP_SHIFT 12
3812 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
3813 #define FMC_PFAPR_M7AP_MASK 0xC000u
3814 #define FMC_PFAPR_M7AP_SHIFT 14
3815 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
3816 #define FMC_PFAPR_M0PFD_MASK 0x10000u
3817 #define FMC_PFAPR_M0PFD_SHIFT 16
3818 #define FMC_PFAPR_M1PFD_MASK 0x20000u
3819 #define FMC_PFAPR_M1PFD_SHIFT 17
3820 #define FMC_PFAPR_M2PFD_MASK 0x40000u
3821 #define FMC_PFAPR_M2PFD_SHIFT 18
3822 #define FMC_PFAPR_M3PFD_MASK 0x80000u
3823 #define FMC_PFAPR_M3PFD_SHIFT 19
3824 #define FMC_PFAPR_M4PFD_MASK 0x100000u
3825 #define FMC_PFAPR_M4PFD_SHIFT 20
3826 #define FMC_PFAPR_M5PFD_MASK 0x200000u
3827 #define FMC_PFAPR_M5PFD_SHIFT 21
3828 #define FMC_PFAPR_M6PFD_MASK 0x400000u
3829 #define FMC_PFAPR_M6PFD_SHIFT 22
3830 #define FMC_PFAPR_M7PFD_MASK 0x800000u
3831 #define FMC_PFAPR_M7PFD_SHIFT 23
3832 /* PFB0CR Bit Fields */
3833 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
3834 #define FMC_PFB0CR_B0SEBE_SHIFT 0
3835 #define FMC_PFB0CR_B0IPE_MASK 0x2u
3836 #define FMC_PFB0CR_B0IPE_SHIFT 1
3837 #define FMC_PFB0CR_B0DPE_MASK 0x4u
3838 #define FMC_PFB0CR_B0DPE_SHIFT 2
3839 #define FMC_PFB0CR_B0ICE_MASK 0x8u
3840 #define FMC_PFB0CR_B0ICE_SHIFT 3
3841 #define FMC_PFB0CR_B0DCE_MASK 0x10u
3842 #define FMC_PFB0CR_B0DCE_SHIFT 4
3843 #define FMC_PFB0CR_CRC_MASK 0xE0u
3844 #define FMC_PFB0CR_CRC_SHIFT 5
3845 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
3846 #define FMC_PFB0CR_B0MW_MASK 0x60000u
3847 #define FMC_PFB0CR_B0MW_SHIFT 17
3848 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
3849 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
3850 #define FMC_PFB0CR_S_B_INV_SHIFT 19
3851 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
3852 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
3853 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
3854 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
3855 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
3856 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
3857 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
3858 #define FMC_PFB0CR_B0RWSC_SHIFT 28
3859 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
3860 /* PFB1CR Bit Fields */
3861 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
3862 #define FMC_PFB1CR_B1SEBE_SHIFT 0
3863 #define FMC_PFB1CR_B1IPE_MASK 0x2u
3864 #define FMC_PFB1CR_B1IPE_SHIFT 1
3865 #define FMC_PFB1CR_B1DPE_MASK 0x4u
3866 #define FMC_PFB1CR_B1DPE_SHIFT 2
3867 #define FMC_PFB1CR_B1ICE_MASK 0x8u
3868 #define FMC_PFB1CR_B1ICE_SHIFT 3
3869 #define FMC_PFB1CR_B1DCE_MASK 0x10u
3870 #define FMC_PFB1CR_B1DCE_SHIFT 4
3871 #define FMC_PFB1CR_B1MW_MASK 0x60000u
3872 #define FMC_PFB1CR_B1MW_SHIFT 17
3873 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
3874 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
3875 #define FMC_PFB1CR_B1RWSC_SHIFT 28
3876 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
3877 /* TAGVD Bit Fields */
3878 #define FMC_TAGVD_valid_MASK 0x1u
3879 #define FMC_TAGVD_valid_SHIFT 0
3880 #define FMC_TAGVD_tag_MASK 0x7FFC0u
3881 #define FMC_TAGVD_tag_SHIFT 6
3882 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
3883 /* DATA_U Bit Fields */
3884 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
3885 #define FMC_DATA_U_data_SHIFT 0
3886 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
3887 /* DATA_L Bit Fields */
3888 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
3889 #define FMC_DATA_L_data_SHIFT 0
3890 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
3891 
3892 /**
3893  * @}
3894  */ /* end of group FMC_Register_Masks */
3895 
3896 
3897 /* FMC - Peripheral instance base addresses */
3898 /** Peripheral FMC base address */
3899 #define FMC_BASE (0x4001F000u)
3900 /** Peripheral FMC base pointer */
3901 #define FMC ((FMC_Type *)FMC_BASE)
3902 
3903 /**
3904  * @}
3905  */ /* end of group FMC_Peripheral_Access_Layer */
3906 
3907 
3908 /* ----------------------------------------------------------------------------
3909  -- FTFL Peripheral Access Layer
3910  ---------------------------------------------------------------------------- */
3911 
3912 /**
3913  * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
3914  * @{
3915  */
3916 
3917 /** FTFL - Register Layout Typedef */
3918 typedef struct {
3919  __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3920  __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3921  __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3922  __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3923  __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3924  __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3925  __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3926  __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3927  __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3928  __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3929  __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3930  __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3931  __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3932  __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3933  __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3934  __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3935  __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3936  __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3937  __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3938  __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3939  uint8_t RESERVED_0[2];
3940  __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
3941  __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
3942 } FTFL_Type;
3943 
3944 /* ----------------------------------------------------------------------------
3945  -- FTFL Register Masks
3946  ---------------------------------------------------------------------------- */
3947 
3948 /**
3949  * @addtogroup FTFL_Register_Masks FTFL Register Masks
3950  * @{
3951  */
3952 
3953 /* FSTAT Bit Fields */
3954 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
3955 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
3956 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
3957 #define FTFL_FSTAT_FPVIOL_SHIFT 4
3958 #define FTFL_FSTAT_ACCERR_MASK 0x20u
3959 #define FTFL_FSTAT_ACCERR_SHIFT 5
3960 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
3961 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
3962 #define FTFL_FSTAT_CCIF_MASK 0x80u
3963 #define FTFL_FSTAT_CCIF_SHIFT 7
3964 /* FCNFG Bit Fields */
3965 #define FTFL_FCNFG_EEERDY_MASK 0x1u
3966 #define FTFL_FCNFG_EEERDY_SHIFT 0
3967 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
3968 #define FTFL_FCNFG_RAMRDY_SHIFT 1
3969 #define FTFL_FCNFG_PFLSH_MASK 0x4u
3970 #define FTFL_FCNFG_PFLSH_SHIFT 2
3971 #define FTFL_FCNFG_SWAP_MASK 0x8u
3972 #define FTFL_FCNFG_SWAP_SHIFT 3
3973 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
3974 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
3975 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
3976 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
3977 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
3978 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
3979 #define FTFL_FCNFG_CCIE_MASK 0x80u
3980 #define FTFL_FCNFG_CCIE_SHIFT 7
3981 /* FSEC Bit Fields */
3982 #define FTFL_FSEC_SEC_MASK 0x3u
3983 #define FTFL_FSEC_SEC_SHIFT 0
3984 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
3985 #define FTFL_FSEC_FSLACC_MASK 0xCu
3986 #define FTFL_FSEC_FSLACC_SHIFT 2
3987 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
3988 #define FTFL_FSEC_MEEN_MASK 0x30u
3989 #define FTFL_FSEC_MEEN_SHIFT 4
3990 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
3991 #define FTFL_FSEC_KEYEN_MASK 0xC0u
3992 #define FTFL_FSEC_KEYEN_SHIFT 6
3993 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
3994 /* FOPT Bit Fields */
3995 #define FTFL_FOPT_OPT_MASK 0xFFu
3996 #define FTFL_FOPT_OPT_SHIFT 0
3997 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
3998 /* FCCOB3 Bit Fields */
3999 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
4000 #define FTFL_FCCOB3_CCOBn_SHIFT 0
4001 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
4002 /* FCCOB2 Bit Fields */
4003 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
4004 #define FTFL_FCCOB2_CCOBn_SHIFT 0
4005 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
4006 /* FCCOB1 Bit Fields */
4007 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
4008 #define FTFL_FCCOB1_CCOBn_SHIFT 0
4009 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
4010 /* FCCOB0 Bit Fields */
4011 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
4012 #define FTFL_FCCOB0_CCOBn_SHIFT 0
4013 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
4014 /* FCCOB7 Bit Fields */
4015 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
4016 #define FTFL_FCCOB7_CCOBn_SHIFT 0
4017 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
4018 /* FCCOB6 Bit Fields */
4019 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
4020 #define FTFL_FCCOB6_CCOBn_SHIFT 0
4021 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
4022 /* FCCOB5 Bit Fields */
4023 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
4024 #define FTFL_FCCOB5_CCOBn_SHIFT 0
4025 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
4026 /* FCCOB4 Bit Fields */
4027 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
4028 #define FTFL_FCCOB4_CCOBn_SHIFT 0
4029 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
4030 /* FCCOBB Bit Fields */
4031 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
4032 #define FTFL_FCCOBB_CCOBn_SHIFT 0
4033 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
4034 /* FCCOBA Bit Fields */
4035 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
4036 #define FTFL_FCCOBA_CCOBn_SHIFT 0
4037 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
4038 /* FCCOB9 Bit Fields */
4039 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
4040 #define FTFL_FCCOB9_CCOBn_SHIFT 0
4041 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
4042 /* FCCOB8 Bit Fields */
4043 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
4044 #define FTFL_FCCOB8_CCOBn_SHIFT 0
4045 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
4046 /* FPROT3 Bit Fields */
4047 #define FTFL_FPROT3_PROT_MASK 0xFFu
4048 #define FTFL_FPROT3_PROT_SHIFT 0
4049 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
4050 /* FPROT2 Bit Fields */
4051 #define FTFL_FPROT2_PROT_MASK 0xFFu
4052 #define FTFL_FPROT2_PROT_SHIFT 0
4053 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
4054 /* FPROT1 Bit Fields */
4055 #define FTFL_FPROT1_PROT_MASK 0xFFu
4056 #define FTFL_FPROT1_PROT_SHIFT 0
4057 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
4058 /* FPROT0 Bit Fields */
4059 #define FTFL_FPROT0_PROT_MASK 0xFFu
4060 #define FTFL_FPROT0_PROT_SHIFT 0
4061 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
4062 /* FEPROT Bit Fields */
4063 #define FTFL_FEPROT_EPROT_MASK 0xFFu
4064 #define FTFL_FEPROT_EPROT_SHIFT 0
4065 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
4066 /* FDPROT Bit Fields */
4067 #define FTFL_FDPROT_DPROT_MASK 0xFFu
4068 #define FTFL_FDPROT_DPROT_SHIFT 0
4069 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
4070 
4071 /**
4072  * @}
4073  */ /* end of group FTFL_Register_Masks */
4074 
4075 
4076 /* FTFL - Peripheral instance base addresses */
4077 /** Peripheral FTFL base address */
4078 #define FTFL_BASE (0x40020000u)
4079 /** Peripheral FTFL base pointer */
4080 #define FTFL ((FTFL_Type *)FTFL_BASE)
4081 
4082 /**
4083  * @}
4084  */ /* end of group FTFL_Peripheral_Access_Layer */
4085 
4086 
4087 /* ----------------------------------------------------------------------------
4088  -- FTM Peripheral Access Layer
4089  ---------------------------------------------------------------------------- */
4090 
4091 /**
4092  * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
4093  * @{
4094  */
4095 
4096 /** FTM - Register Layout Typedef */
4097 typedef struct {
4098  __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
4099  __IO uint32_t CNT; /**< Counter, offset: 0x4 */
4100  __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
4101  struct { /* offset: 0xC, array step: 0x8 */
4102  __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
4103  __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
4104  } CONTROLS[8];
4105  __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
4106  __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
4107  __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
4108  __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
4109  __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
4110  __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
4111  __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
4112  __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
4113  __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
4114  __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
4115  __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
4116  __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
4117  __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
4118  __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
4119  __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
4120  __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
4121  __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
4122  __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
4123  __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
4124  __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
4125 } FTM_Type;
4126 
4127 /* ----------------------------------------------------------------------------
4128  -- FTM Register Masks
4129  ---------------------------------------------------------------------------- */
4130 
4131 /**
4132  * @addtogroup FTM_Register_Masks FTM Register Masks
4133  * @{
4134  */
4135 
4136 /* SC Bit Fields */
4137 #define FTM_SC_PS_MASK 0x7u
4138 #define FTM_SC_PS_SHIFT 0
4139 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
4140 #define FTM_SC_CLKS_MASK 0x18u
4141 #define FTM_SC_CLKS_SHIFT 3
4142 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
4143 #define FTM_SC_CPWMS_MASK 0x20u
4144 #define FTM_SC_CPWMS_SHIFT 5
4145 #define FTM_SC_TOIE_MASK 0x40u
4146 #define FTM_SC_TOIE_SHIFT 6
4147 #define FTM_SC_TOF_MASK 0x80u
4148 #define FTM_SC_TOF_SHIFT 7
4149 /* CNT Bit Fields */
4150 #define FTM_CNT_COUNT_MASK 0xFFFFu
4151 #define FTM_CNT_COUNT_SHIFT 0
4152 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
4153 /* MOD Bit Fields */
4154 #define FTM_MOD_MOD_MASK 0xFFFFu
4155 #define FTM_MOD_MOD_SHIFT 0
4156 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
4157 /* CnSC Bit Fields */
4158 #define FTM_CnSC_DMA_MASK 0x1u
4159 #define FTM_CnSC_DMA_SHIFT 0
4160 #define FTM_CnSC_ELSA_MASK 0x4u
4161 #define FTM_CnSC_ELSA_SHIFT 2
4162 #define FTM_CnSC_ELSB_MASK 0x8u
4163 #define FTM_CnSC_ELSB_SHIFT 3
4164 #define FTM_CnSC_MSA_MASK 0x10u
4165 #define FTM_CnSC_MSA_SHIFT 4
4166 #define FTM_CnSC_MSB_MASK 0x20u
4167 #define FTM_CnSC_MSB_SHIFT 5
4168 #define FTM_CnSC_CHIE_MASK 0x40u
4169 #define FTM_CnSC_CHIE_SHIFT 6
4170 #define FTM_CnSC_CHF_MASK 0x80u
4171 #define FTM_CnSC_CHF_SHIFT 7
4172 /* CnV Bit Fields */
4173 #define FTM_CnV_VAL_MASK 0xFFFFu
4174 #define FTM_CnV_VAL_SHIFT 0
4175 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
4176 /* CNTIN Bit Fields */
4177 #define FTM_CNTIN_INIT_MASK 0xFFFFu
4178 #define FTM_CNTIN_INIT_SHIFT 0
4179 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
4180 /* STATUS Bit Fields */
4181 #define FTM_STATUS_CH0F_MASK 0x1u
4182 #define FTM_STATUS_CH0F_SHIFT 0
4183 #define FTM_STATUS_CH1F_MASK 0x2u
4184 #define FTM_STATUS_CH1F_SHIFT 1
4185 #define FTM_STATUS_CH2F_MASK 0x4u
4186 #define FTM_STATUS_CH2F_SHIFT 2
4187 #define FTM_STATUS_CH3F_MASK 0x8u
4188 #define FTM_STATUS_CH3F_SHIFT 3
4189 #define FTM_STATUS_CH4F_MASK 0x10u
4190 #define FTM_STATUS_CH4F_SHIFT 4
4191 #define FTM_STATUS_CH5F_MASK 0x20u
4192 #define FTM_STATUS_CH5F_SHIFT 5
4193 #define FTM_STATUS_CH6F_MASK 0x40u
4194 #define FTM_STATUS_CH6F_SHIFT 6
4195 #define FTM_STATUS_CH7F_MASK 0x80u
4196 #define FTM_STATUS_CH7F_SHIFT 7
4197 /* MODE Bit Fields */
4198 #define FTM_MODE_FTMEN_MASK 0x1u
4199 #define FTM_MODE_FTMEN_SHIFT 0
4200 #define FTM_MODE_INIT_MASK 0x2u
4201 #define FTM_MODE_INIT_SHIFT 1
4202 #define FTM_MODE_WPDIS_MASK 0x4u
4203 #define FTM_MODE_WPDIS_SHIFT 2
4204 #define FTM_MODE_PWMSYNC_MASK 0x8u
4205 #define FTM_MODE_PWMSYNC_SHIFT 3
4206 #define FTM_MODE_CAPTEST_MASK 0x10u
4207 #define FTM_MODE_CAPTEST_SHIFT 4
4208 #define FTM_MODE_FAULTM_MASK 0x60u
4209 #define FTM_MODE_FAULTM_SHIFT 5
4210 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
4211 #define FTM_MODE_FAULTIE_MASK 0x80u
4212 #define FTM_MODE_FAULTIE_SHIFT 7
4213 /* SYNC Bit Fields */
4214 #define FTM_SYNC_CNTMIN_MASK 0x1u
4215 #define FTM_SYNC_CNTMIN_SHIFT 0
4216 #define FTM_SYNC_CNTMAX_MASK 0x2u
4217 #define FTM_SYNC_CNTMAX_SHIFT 1
4218 #define FTM_SYNC_REINIT_MASK 0x4u
4219 #define FTM_SYNC_REINIT_SHIFT 2
4220 #define FTM_SYNC_SYNCHOM_MASK 0x8u
4221 #define FTM_SYNC_SYNCHOM_SHIFT 3
4222 #define FTM_SYNC_TRIG0_MASK 0x10u
4223 #define FTM_SYNC_TRIG0_SHIFT 4
4224 #define FTM_SYNC_TRIG1_MASK 0x20u
4225 #define FTM_SYNC_TRIG1_SHIFT 5
4226 #define FTM_SYNC_TRIG2_MASK 0x40u
4227 #define FTM_SYNC_TRIG2_SHIFT 6
4228 #define FTM_SYNC_SWSYNC_MASK 0x80u
4229 #define FTM_SYNC_SWSYNC_SHIFT 7
4230 /* OUTINIT Bit Fields */
4231 #define FTM_OUTINIT_CH0OI_MASK 0x1u
4232 #define FTM_OUTINIT_CH0OI_SHIFT 0
4233 #define FTM_OUTINIT_CH1OI_MASK 0x2u
4234 #define FTM_OUTINIT_CH1OI_SHIFT 1
4235 #define FTM_OUTINIT_CH2OI_MASK 0x4u
4236 #define FTM_OUTINIT_CH2OI_SHIFT 2
4237 #define FTM_OUTINIT_CH3OI_MASK 0x8u
4238 #define FTM_OUTINIT_CH3OI_SHIFT 3
4239 #define FTM_OUTINIT_CH4OI_MASK 0x10u
4240 #define FTM_OUTINIT_CH4OI_SHIFT 4
4241 #define FTM_OUTINIT_CH5OI_MASK 0x20u
4242 #define FTM_OUTINIT_CH5OI_SHIFT 5
4243 #define FTM_OUTINIT_CH6OI_MASK 0x40u
4244 #define FTM_OUTINIT_CH6OI_SHIFT 6
4245 #define FTM_OUTINIT_CH7OI_MASK 0x80u
4246 #define FTM_OUTINIT_CH7OI_SHIFT 7
4247 /* OUTMASK Bit Fields */
4248 #define FTM_OUTMASK_CH0OM_MASK 0x1u
4249 #define FTM_OUTMASK_CH0OM_SHIFT 0
4250 #define FTM_OUTMASK_CH1OM_MASK 0x2u
4251 #define FTM_OUTMASK_CH1OM_SHIFT 1
4252 #define FTM_OUTMASK_CH2OM_MASK 0x4u
4253 #define FTM_OUTMASK_CH2OM_SHIFT 2
4254 #define FTM_OUTMASK_CH3OM_MASK 0x8u
4255 #define FTM_OUTMASK_CH3OM_SHIFT 3
4256 #define FTM_OUTMASK_CH4OM_MASK 0x10u
4257 #define FTM_OUTMASK_CH4OM_SHIFT 4
4258 #define FTM_OUTMASK_CH5OM_MASK 0x20u
4259 #define FTM_OUTMASK_CH5OM_SHIFT 5
4260 #define FTM_OUTMASK_CH6OM_MASK 0x40u
4261 #define FTM_OUTMASK_CH6OM_SHIFT 6
4262 #define FTM_OUTMASK_CH7OM_MASK 0x80u
4263 #define FTM_OUTMASK_CH7OM_SHIFT 7
4264 /* COMBINE Bit Fields */
4265 #define FTM_COMBINE_COMBINE0_MASK 0x1u
4266 #define FTM_COMBINE_COMBINE0_SHIFT 0
4267 #define FTM_COMBINE_COMP0_MASK 0x2u
4268 #define FTM_COMBINE_COMP0_SHIFT 1
4269 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
4270 #define FTM_COMBINE_DECAPEN0_SHIFT 2
4271 #define FTM_COMBINE_DECAP0_MASK 0x8u
4272 #define FTM_COMBINE_DECAP0_SHIFT 3
4273 #define FTM_COMBINE_DTEN0_MASK 0x10u
4274 #define FTM_COMBINE_DTEN0_SHIFT 4
4275 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
4276 #define FTM_COMBINE_SYNCEN0_SHIFT 5
4277 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
4278 #define FTM_COMBINE_FAULTEN0_SHIFT 6
4279 #define FTM_COMBINE_COMBINE1_MASK 0x100u
4280 #define FTM_COMBINE_COMBINE1_SHIFT 8
4281 #define FTM_COMBINE_COMP1_MASK 0x200u
4282 #define FTM_COMBINE_COMP1_SHIFT 9
4283 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
4284 #define FTM_COMBINE_DECAPEN1_SHIFT 10
4285 #define FTM_COMBINE_DECAP1_MASK 0x800u
4286 #define FTM_COMBINE_DECAP1_SHIFT 11
4287 #define FTM_COMBINE_DTEN1_MASK 0x1000u
4288 #define FTM_COMBINE_DTEN1_SHIFT 12
4289 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
4290 #define FTM_COMBINE_SYNCEN1_SHIFT 13
4291 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
4292 #define FTM_COMBINE_FAULTEN1_SHIFT 14
4293 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
4294 #define FTM_COMBINE_COMBINE2_SHIFT 16
4295 #define FTM_COMBINE_COMP2_MASK 0x20000u
4296 #define FTM_COMBINE_COMP2_SHIFT 17
4297 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
4298 #define FTM_COMBINE_DECAPEN2_SHIFT 18
4299 #define FTM_COMBINE_DECAP2_MASK 0x80000u
4300 #define FTM_COMBINE_DECAP2_SHIFT 19
4301 #define FTM_COMBINE_DTEN2_MASK 0x100000u
4302 #define FTM_COMBINE_DTEN2_SHIFT 20
4303 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
4304 #define FTM_COMBINE_SYNCEN2_SHIFT 21
4305 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
4306 #define FTM_COMBINE_FAULTEN2_SHIFT 22
4307 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
4308 #define FTM_COMBINE_COMBINE3_SHIFT 24
4309 #define FTM_COMBINE_COMP3_MASK 0x2000000u
4310 #define FTM_COMBINE_COMP3_SHIFT 25
4311 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
4312 #define FTM_COMBINE_DECAPEN3_SHIFT 26
4313 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
4314 #define FTM_COMBINE_DECAP3_SHIFT 27
4315 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
4316 #define FTM_COMBINE_DTEN3_SHIFT 28
4317 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
4318 #define FTM_COMBINE_SYNCEN3_SHIFT 29
4319 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
4320 #define FTM_COMBINE_FAULTEN3_SHIFT 30
4321 /* DEADTIME Bit Fields */
4322 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
4323 #define FTM_DEADTIME_DTVAL_SHIFT 0
4324 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
4325 #define FTM_DEADTIME_DTPS_MASK 0xC0u
4326 #define FTM_DEADTIME_DTPS_SHIFT 6
4327 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
4328 /* EXTTRIG Bit Fields */
4329 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
4330 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
4331 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
4332 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
4333 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
4334 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
4335 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
4336 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
4337 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
4338 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
4339 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
4340 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
4341 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
4342 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
4343 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
4344 #define FTM_EXTTRIG_TRIGF_SHIFT 7
4345 /* POL Bit Fields */
4346 #define FTM_POL_POL0_MASK 0x1u
4347 #define FTM_POL_POL0_SHIFT 0
4348 #define FTM_POL_POL1_MASK 0x2u
4349 #define FTM_POL_POL1_SHIFT 1
4350 #define FTM_POL_POL2_MASK 0x4u
4351 #define FTM_POL_POL2_SHIFT 2
4352 #define FTM_POL_POL3_MASK 0x8u
4353 #define FTM_POL_POL3_SHIFT 3
4354 #define FTM_POL_POL4_MASK 0x10u
4355 #define FTM_POL_POL4_SHIFT 4
4356 #define FTM_POL_POL5_MASK 0x20u
4357 #define FTM_POL_POL5_SHIFT 5
4358 #define FTM_POL_POL6_MASK 0x40u
4359 #define FTM_POL_POL6_SHIFT 6
4360 #define FTM_POL_POL7_MASK 0x80u
4361 #define FTM_POL_POL7_SHIFT 7
4362 /* FMS Bit Fields */
4363 #define FTM_FMS_FAULTF0_MASK 0x1u
4364 #define FTM_FMS_FAULTF0_SHIFT 0
4365 #define FTM_FMS_FAULTF1_MASK 0x2u
4366 #define FTM_FMS_FAULTF1_SHIFT 1
4367 #define FTM_FMS_FAULTF2_MASK 0x4u
4368 #define FTM_FMS_FAULTF2_SHIFT 2
4369 #define FTM_FMS_FAULTF3_MASK 0x8u
4370 #define FTM_FMS_FAULTF3_SHIFT 3
4371 #define FTM_FMS_FAULTIN_MASK 0x20u
4372 #define FTM_FMS_FAULTIN_SHIFT 5
4373 #define FTM_FMS_WPEN_MASK 0x40u
4374 #define FTM_FMS_WPEN_SHIFT 6
4375 #define FTM_FMS_FAULTF_MASK 0x80u
4376 #define FTM_FMS_FAULTF_SHIFT 7
4377 /* FILTER Bit Fields */
4378 #define FTM_FILTER_CH0FVAL_MASK 0xFu
4379 #define FTM_FILTER_CH0FVAL_SHIFT 0
4380 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
4381 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
4382 #define FTM_FILTER_CH1FVAL_SHIFT 4
4383 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
4384 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
4385 #define FTM_FILTER_CH2FVAL_SHIFT 8
4386 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
4387 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
4388 #define FTM_FILTER_CH3FVAL_SHIFT 12
4389 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
4390 /* FLTCTRL Bit Fields */
4391 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
4392 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
4393 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
4394 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
4395 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
4396 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
4397 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
4398 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
4399 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
4400 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
4401 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
4402 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
4403 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
4404 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
4405 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
4406 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
4407 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
4408 #define FTM_FLTCTRL_FFVAL_SHIFT 8
4409 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
4410 /* QDCTRL Bit Fields */
4411 #define FTM_QDCTRL_QUADEN_MASK 0x1u
4412 #define FTM_QDCTRL_QUADEN_SHIFT 0
4413 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
4414 #define FTM_QDCTRL_TOFDIR_SHIFT 1
4415 #define FTM_QDCTRL_QUADIR_MASK 0x4u
4416 #define FTM_QDCTRL_QUADIR_SHIFT 2
4417 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
4418 #define FTM_QDCTRL_QUADMODE_SHIFT 3
4419 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
4420 #define FTM_QDCTRL_PHBPOL_SHIFT 4
4421 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
4422 #define FTM_QDCTRL_PHAPOL_SHIFT 5
4423 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
4424 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
4425 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
4426 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
4427 /* CONF Bit Fields */
4428 #define FTM_CONF_NUMTOF_MASK 0x1Fu
4429 #define FTM_CONF_NUMTOF_SHIFT 0
4430 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
4431 #define FTM_CONF_BDMMODE_MASK 0xC0u
4432 #define FTM_CONF_BDMMODE_SHIFT 6
4433 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
4434 #define FTM_CONF_GTBEEN_MASK 0x200u
4435 #define FTM_CONF_GTBEEN_SHIFT 9
4436 #define FTM_CONF_GTBEOUT_MASK 0x400u
4437 #define FTM_CONF_GTBEOUT_SHIFT 10
4438 /* FLTPOL Bit Fields */
4439 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
4440 #define FTM_FLTPOL_FLT0POL_SHIFT 0
4441 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
4442 #define FTM_FLTPOL_FLT1POL_SHIFT 1
4443 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
4444 #define FTM_FLTPOL_FLT2POL_SHIFT 2
4445 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
4446 #define FTM_FLTPOL_FLT3POL_SHIFT 3
4447 /* SYNCONF Bit Fields */
4448 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
4449 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
4450 #define FTM_SYNCONF_CNTINC_MASK 0x4u
4451 #define FTM_SYNCONF_CNTINC_SHIFT 2
4452 #define FTM_SYNCONF_INVC_MASK 0x10u
4453 #define FTM_SYNCONF_INVC_SHIFT 4
4454 #define FTM_SYNCONF_SWOC_MASK 0x20u
4455 #define FTM_SYNCONF_SWOC_SHIFT 5
4456 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
4457 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
4458 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
4459 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
4460 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
4461 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
4462 #define FTM_SYNCONF_SWOM_MASK 0x400u
4463 #define FTM_SYNCONF_SWOM_SHIFT 10
4464 #define FTM_SYNCONF_SWINVC_MASK 0x800u
4465 #define FTM_SYNCONF_SWINVC_SHIFT 11
4466 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
4467 #define FTM_SYNCONF_SWSOC_SHIFT 12
4468 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
4469 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
4470 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
4471 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
4472 #define FTM_SYNCONF_HWOM_MASK 0x40000u
4473 #define FTM_SYNCONF_HWOM_SHIFT 18
4474 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
4475 #define FTM_SYNCONF_HWINVC_SHIFT 19
4476 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
4477 #define FTM_SYNCONF_HWSOC_SHIFT 20
4478 /* INVCTRL Bit Fields */
4479 #define FTM_INVCTRL_INV0EN_MASK 0x1u
4480 #define FTM_INVCTRL_INV0EN_SHIFT 0
4481 #define FTM_INVCTRL_INV1EN_MASK 0x2u
4482 #define FTM_INVCTRL_INV1EN_SHIFT 1
4483 #define FTM_INVCTRL_INV2EN_MASK 0x4u
4484 #define FTM_INVCTRL_INV2EN_SHIFT 2
4485 #define FTM_INVCTRL_INV3EN_MASK 0x8u
4486 #define FTM_INVCTRL_INV3EN_SHIFT 3
4487 /* SWOCTRL Bit Fields */
4488 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
4489 #define FTM_SWOCTRL_CH0OC_SHIFT 0
4490 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
4491 #define FTM_SWOCTRL_CH1OC_SHIFT 1
4492 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
4493 #define FTM_SWOCTRL_CH2OC_SHIFT 2
4494 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
4495 #define FTM_SWOCTRL_CH3OC_SHIFT 3
4496 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
4497 #define FTM_SWOCTRL_CH4OC_SHIFT 4
4498 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
4499 #define FTM_SWOCTRL_CH5OC_SHIFT 5
4500 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
4501 #define FTM_SWOCTRL_CH6OC_SHIFT 6
4502 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
4503 #define FTM_SWOCTRL_CH7OC_SHIFT 7
4504 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
4505 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
4506 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
4507 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
4508 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
4509 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
4510 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
4511 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
4512 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
4513 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
4514 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
4515 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
4516 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
4517 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
4518 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
4519 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
4520 /* PWMLOAD Bit Fields */
4521 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
4522 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
4523 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
4524 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
4525 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
4526 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
4527 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
4528 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
4529 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
4530 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
4531 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
4532 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
4533 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
4534 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
4535 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
4536 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
4537 #define FTM_PWMLOAD_LDOK_MASK 0x200u
4538 #define FTM_PWMLOAD_LDOK_SHIFT 9
4539 
4540 /**
4541  * @}
4542  */ /* end of group FTM_Register_Masks */
4543 
4544 
4545 /* FTM - Peripheral instance base addresses */
4546 /** Peripheral FTM0 base address */
4547 #define FTM0_BASE (0x40038000u)
4548 /** Peripheral FTM0 base pointer */
4549 #define FTM0 ((FTM_Type *)FTM0_BASE)
4550 /** Peripheral FTM1 base address */
4551 #define FTM1_BASE (0x40039000u)
4552 /** Peripheral FTM1 base pointer */
4553 #define FTM1 ((FTM_Type *)FTM1_BASE)
4554 /** Peripheral FTM2 base address */
4555 #define FTM2_BASE (0x400B8000u)
4556 /** Peripheral FTM2 base pointer */
4557 #define FTM2 ((FTM_Type *)FTM2_BASE)
4558 
4559 /**
4560  * @}
4561  */ /* end of group FTM_Peripheral_Access_Layer */
4562 
4563 
4564 /* ----------------------------------------------------------------------------
4565  -- GPIO Peripheral Access Layer
4566  ---------------------------------------------------------------------------- */
4567 
4568 /**
4569  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
4570  * @{
4571  */
4572 
4573 /** GPIO - Register Layout Typedef */
4574 typedef struct {
4575  __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
4576  __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
4577  __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
4578  __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
4579  __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
4580  __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
4581 } GPIO_Type;
4582 
4583 /* ----------------------------------------------------------------------------
4584  -- GPIO Register Masks
4585  ---------------------------------------------------------------------------- */
4586 
4587 /**
4588  * @addtogroup GPIO_Register_Masks GPIO Register Masks
4589  * @{
4590  */
4591 
4592 /* PDOR Bit Fields */
4593 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
4594 #define GPIO_PDOR_PDO_SHIFT 0
4595 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
4596 /* PSOR Bit Fields */
4597 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
4598 #define GPIO_PSOR_PTSO_SHIFT 0
4599 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
4600 /* PCOR Bit Fields */
4601 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
4602 #define GPIO_PCOR_PTCO_SHIFT 0
4603 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
4604 /* PTOR Bit Fields */
4605 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
4606 #define GPIO_PTOR_PTTO_SHIFT 0
4607 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
4608 /* PDIR Bit Fields */
4609 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
4610 #define GPIO_PDIR_PDI_SHIFT 0
4611 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
4612 /* PDDR Bit Fields */
4613 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
4614 #define GPIO_PDDR_PDD_SHIFT 0
4615 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
4616 
4617 /**
4618  * @}
4619  */ /* end of group GPIO_Register_Masks */
4620 
4621 
4622 /* GPIO - Peripheral instance base addresses */
4623 /** Peripheral PTA base address */
4624 #define PTA_BASE (0x400FF000u)
4625 /** Peripheral PTA base pointer */
4626 #define PTA ((GPIO_Type *)PTA_BASE)
4627 /** Peripheral PTB base address */
4628 #define PTB_BASE (0x400FF040u)
4629 /** Peripheral PTB base pointer */
4630 #define PTB ((GPIO_Type *)PTB_BASE)
4631 /** Peripheral PTC base address */
4632 #define PTC_BASE (0x400FF080u)
4633 /** Peripheral PTC base pointer */
4634 #define PTC ((GPIO_Type *)PTC_BASE)
4635 /** Peripheral PTD base address */
4636 #define PTD_BASE (0x400FF0C0u)
4637 /** Peripheral PTD base pointer */
4638 #define PTD ((GPIO_Type *)PTD_BASE)
4639 /** Peripheral PTE base address */
4640 #define PTE_BASE (0x400FF100u)
4641 /** Peripheral PTE base pointer */
4642 #define PTE ((GPIO_Type *)PTE_BASE)
4643 
4644 /**
4645  * @}
4646  */ /* end of group GPIO_Peripheral_Access_Layer */
4647 
4648 
4649 /* ----------------------------------------------------------------------------
4650  -- I2C Peripheral Access Layer
4651  ---------------------------------------------------------------------------- */
4652 
4653 /**
4654  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
4655  * @{
4656  */
4657 
4658 /** I2C - Register Layout Typedef */
4659 typedef struct {
4660  __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
4661  __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
4662  __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
4663  __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
4664  __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
4665  __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
4666  __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
4667  __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
4668  __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
4669  __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
4670  __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
4671  __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
4672 } I2C_Type;
4673 
4674 /* ----------------------------------------------------------------------------
4675  -- I2C Register Masks
4676  ---------------------------------------------------------------------------- */
4677 
4678 /**
4679  * @addtogroup I2C_Register_Masks I2C Register Masks
4680  * @{
4681  */
4682 
4683 /* A1 Bit Fields */
4684 #define I2C_A1_AD_MASK 0xFEu
4685 #define I2C_A1_AD_SHIFT 1
4686 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
4687 /* F Bit Fields */
4688 #define I2C_F_ICR_MASK 0x3Fu
4689 #define I2C_F_ICR_SHIFT 0
4690 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
4691 #define I2C_F_MULT_MASK 0xC0u
4692 #define I2C_F_MULT_SHIFT 6
4693 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
4694 /* C1 Bit Fields */
4695 #define I2C_C1_DMAEN_MASK 0x1u
4696 #define I2C_C1_DMAEN_SHIFT 0
4697 #define I2C_C1_WUEN_MASK 0x2u
4698 #define I2C_C1_WUEN_SHIFT 1
4699 #define I2C_C1_RSTA_MASK 0x4u
4700 #define I2C_C1_RSTA_SHIFT 2
4701 #define I2C_C1_TXAK_MASK 0x8u
4702 #define I2C_C1_TXAK_SHIFT 3
4703 #define I2C_C1_TX_MASK 0x10u
4704 #define I2C_C1_TX_SHIFT 4
4705 #define I2C_C1_MST_MASK 0x20u
4706 #define I2C_C1_MST_SHIFT 5
4707 #define I2C_C1_IICIE_MASK 0x40u
4708 #define I2C_C1_IICIE_SHIFT 6
4709 #define I2C_C1_IICEN_MASK 0x80u
4710 #define I2C_C1_IICEN_SHIFT 7
4711 /* S Bit Fields */
4712 #define I2C_S_RXAK_MASK 0x1u
4713 #define I2C_S_RXAK_SHIFT 0
4714 #define I2C_S_IICIF_MASK 0x2u
4715 #define I2C_S_IICIF_SHIFT 1
4716 #define I2C_S_SRW_MASK 0x4u
4717 #define I2C_S_SRW_SHIFT 2
4718 #define I2C_S_RAM_MASK 0x8u
4719 #define I2C_S_RAM_SHIFT 3
4720 #define I2C_S_ARBL_MASK 0x10u
4721 #define I2C_S_ARBL_SHIFT 4
4722 #define I2C_S_BUSY_MASK 0x20u
4723 #define I2C_S_BUSY_SHIFT 5
4724 #define I2C_S_IAAS_MASK 0x40u
4725 #define I2C_S_IAAS_SHIFT 6
4726 #define I2C_S_TCF_MASK 0x80u
4727 #define I2C_S_TCF_SHIFT 7
4728 /* D Bit Fields */
4729 #define I2C_D_DATA_MASK 0xFFu
4730 #define I2C_D_DATA_SHIFT 0
4731 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
4732 /* C2 Bit Fields */
4733 #define I2C_C2_AD_MASK 0x7u
4734 #define I2C_C2_AD_SHIFT 0
4735 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
4736 #define I2C_C2_RMEN_MASK 0x8u
4737 #define I2C_C2_RMEN_SHIFT 3
4738 #define I2C_C2_SBRC_MASK 0x10u
4739 #define I2C_C2_SBRC_SHIFT 4
4740 #define I2C_C2_HDRS_MASK 0x20u
4741 #define I2C_C2_HDRS_SHIFT 5
4742 #define I2C_C2_ADEXT_MASK 0x40u
4743 #define I2C_C2_ADEXT_SHIFT 6
4744 #define I2C_C2_GCAEN_MASK 0x80u
4745 #define I2C_C2_GCAEN_SHIFT 7
4746 /* FLT Bit Fields */
4747 #define I2C_FLT_FLT_MASK 0x1Fu
4748 #define I2C_FLT_FLT_SHIFT 0
4749 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
4750 /* RA Bit Fields */
4751 #define I2C_RA_RAD_MASK 0xFEu
4752 #define I2C_RA_RAD_SHIFT 1
4753 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
4754 /* SMB Bit Fields */
4755 #define I2C_SMB_SHTF2IE_MASK 0x1u
4756 #define I2C_SMB_SHTF2IE_SHIFT 0
4757 #define I2C_SMB_SHTF2_MASK 0x2u
4758 #define I2C_SMB_SHTF2_SHIFT 1
4759 #define I2C_SMB_SHTF1_MASK 0x4u
4760 #define I2C_SMB_SHTF1_SHIFT 2
4761 #define I2C_SMB_SLTF_MASK 0x8u
4762 #define I2C_SMB_SLTF_SHIFT 3
4763 #define I2C_SMB_TCKSEL_MASK 0x10u
4764 #define I2C_SMB_TCKSEL_SHIFT 4
4765 #define I2C_SMB_SIICAEN_MASK 0x20u
4766 #define I2C_SMB_SIICAEN_SHIFT 5
4767 #define I2C_SMB_ALERTEN_MASK 0x40u
4768 #define I2C_SMB_ALERTEN_SHIFT 6
4769 #define I2C_SMB_FACK_MASK 0x80u
4770 #define I2C_SMB_FACK_SHIFT 7
4771 /* A2 Bit Fields */
4772 #define I2C_A2_SAD_MASK 0xFEu
4773 #define I2C_A2_SAD_SHIFT 1
4774 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
4775 /* SLTH Bit Fields */
4776 #define I2C_SLTH_SSLT_MASK 0xFFu
4777 #define I2C_SLTH_SSLT_SHIFT 0
4778 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
4779 /* SLTL Bit Fields */
4780 #define I2C_SLTL_SSLT_MASK 0xFFu
4781 #define I2C_SLTL_SSLT_SHIFT 0
4782 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
4783 
4784 /**
4785  * @}
4786  */ /* end of group I2C_Register_Masks */
4787 
4788 
4789 /* I2C - Peripheral instance base addresses */
4790 /** Peripheral I2C0 base address */
4791 #define I2C0_BASE (0x40066000u)
4792 /** Peripheral I2C0 base pointer */
4793 #define I2C0 ((I2C_Type *)I2C0_BASE)
4794 /** Peripheral I2C1 base address */
4795 #define I2C1_BASE (0x40067000u)
4796 /** Peripheral I2C1 base pointer */
4797 #define I2C1 ((I2C_Type *)I2C1_BASE)
4798 
4799 /**
4800  * @}
4801  */ /* end of group I2C_Peripheral_Access_Layer */
4802 
4803 
4804 /* ----------------------------------------------------------------------------
4805  -- I2S Peripheral Access Layer
4806  ---------------------------------------------------------------------------- */
4807 
4808 /**
4809  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
4810  * @{
4811  */
4812 
4813 /** I2S - Register Layout Typedef */
4814 typedef struct {
4815  __IO uint32_t TX0; /**< I2S Transmit Data Registers 0, offset: 0x0 */
4816  __IO uint32_t TX1; /**< I2S Transmit Data Registers 1, offset: 0x4 */
4817  __IO uint32_t RX0; /**< I2S Receive Data Registers 0, offset: 0x8 */
4818  __IO uint32_t RX1; /**< I2S Receive Data Registers 1, offset: 0xC */
4819  __IO uint32_t CR; /**< I2S Control Register, offset: 0x10 */
4820  __IO uint32_t ISR; /**< I2S Interrupt Status Register, offset: 0x14 */
4821  __IO uint32_t IER; /**< I2S Interrupt Enable Register, offset: 0x18 */
4822  __IO uint32_t TCR; /**< I2S Transmit Configuration Register, offset: 0x1C */
4823  __IO uint32_t RCR; /**< I2S Receive Configuration Register, offset: 0x20 */
4824  __IO uint32_t TCCR; /**< I2S Transmit Clock Control Registers, offset: 0x24 */
4825  __IO uint32_t RCCR; /**< I2S Receive Clock Control Registers, offset: 0x28 */
4826  __IO uint32_t FCSR; /**< I2S FIFO Control/Status Register, offset: 0x2C */
4827  uint8_t RESERVED_0[8];
4828  __IO uint32_t ACNT; /**< I2S AC97 Control Register, offset: 0x38 */
4829  __IO uint32_t ACADD; /**< I2S AC97 Command Address Register, offset: 0x3C */
4830  __IO uint32_t ACDAT; /**< I2S AC97 Command Data Register, offset: 0x40 */
4831  __IO uint32_t ATAG; /**< I2S AC97 Tag Register, offset: 0x44 */
4832  __IO uint32_t TMSK; /**< I2S Transmit Time Slot Mask Register, offset: 0x48 */
4833  __IO uint32_t RMSK; /**< I2S Receive Time Slot Mask Register, offset: 0x4C */
4834  __I uint32_t ACCST; /**< I2S AC97 Channel Status Register, offset: 0x50 */
4835  __IO uint32_t ACCEN; /**< I2S AC97 Channel Enable Register, offset: 0x54 */
4836  __IO uint32_t ACCDIS; /**< I2S AC97 Channel Disable Register, offset: 0x58 */
4837 } I2S_Type;
4838 
4839 /* ----------------------------------------------------------------------------
4840  -- I2S Register Masks
4841  ---------------------------------------------------------------------------- */
4842 
4843 /**
4844  * @addtogroup I2S_Register_Masks I2S Register Masks
4845  * @{
4846  */
4847 
4848 /* TX0 Bit Fields */
4849 #define I2S_TX0_TX0_MASK 0xFFFFFFFFu
4850 #define I2S_TX0_TX0_SHIFT 0
4851 #define I2S_TX0_TX0(x) (((uint32_t)(((uint32_t)(x))<<I2S_TX0_TX0_SHIFT))&I2S_TX0_TX0_MASK)
4852 /* TX1 Bit Fields */
4853 #define I2S_TX1_TX1_MASK 0xFFFFFFFFu
4854 #define I2S_TX1_TX1_SHIFT 0
4855 #define I2S_TX1_TX1(x) (((uint32_t)(((uint32_t)(x))<<I2S_TX1_TX1_SHIFT))&I2S_TX1_TX1_MASK)
4856 /* RX0 Bit Fields */
4857 #define I2S_RX0_RX0_MASK 0xFFFFFFFFu
4858 #define I2S_RX0_RX0_SHIFT 0
4859 #define I2S_RX0_RX0(x) (((uint32_t)(((uint32_t)(x))<<I2S_RX0_RX0_SHIFT))&I2S_RX0_RX0_MASK)
4860 /* RX1 Bit Fields */
4861 #define I2S_RX1_RX1_MASK 0xFFFFFFFFu
4862 #define I2S_RX1_RX1_SHIFT 0
4863 #define I2S_RX1_RX1(x) (((uint32_t)(((uint32_t)(x))<<I2S_RX1_RX1_SHIFT))&I2S_RX1_RX1_MASK)
4864 /* CR Bit Fields */
4865 #define I2S_CR_I2SEN_MASK 0x1u
4866 #define I2S_CR_I2SEN_SHIFT 0
4867 #define I2S_CR_TE_MASK 0x2u
4868 #define I2S_CR_TE_SHIFT 1
4869 #define I2S_CR_RE_MASK 0x4u
4870 #define I2S_CR_RE_SHIFT 2
4871 #define I2S_CR_NET_MASK 0x8u
4872 #define I2S_CR_NET_SHIFT 3
4873 #define I2S_CR_SYN_MASK 0x10u
4874 #define I2S_CR_SYN_SHIFT 4
4875 #define I2S_CR_I2SMODE_MASK 0x60u
4876 #define I2S_CR_I2SMODE_SHIFT 5
4877 #define I2S_CR_I2SMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_CR_I2SMODE_SHIFT))&I2S_CR_I2SMODE_MASK)
4878 #define I2S_CR_SYSCLKEN_MASK 0x80u
4879 #define I2S_CR_SYSCLKEN_SHIFT 7
4880 #define I2S_CR_TCHEN_MASK 0x100u
4881 #define I2S_CR_TCHEN_SHIFT 8
4882 #define I2S_CR_CLKIST_MASK 0x200u
4883 #define I2S_CR_CLKIST_SHIFT 9
4884 #define I2S_CR_TFRCLKDIS_MASK 0x400u
4885 #define I2S_CR_TFRCLKDIS_SHIFT 10
4886 #define I2S_CR_RFRCLKDIS_MASK 0x800u
4887 #define I2S_CR_RFRCLKDIS_SHIFT 11
4888 #define I2S_CR_SYNCTXFS_MASK 0x1000u
4889 #define I2S_CR_SYNCTXFS_SHIFT 12
4890 /* ISR Bit Fields */
4891 #define I2S_ISR_TFE0_MASK 0x1u
4892 #define I2S_ISR_TFE0_SHIFT 0
4893 #define I2S_ISR_TFE1_MASK 0x2u
4894 #define I2S_ISR_TFE1_SHIFT 1
4895 #define I2S_ISR_RFF0_MASK 0x4u
4896 #define I2S_ISR_RFF0_SHIFT 2
4897 #define I2S_ISR_RFF1_MASK 0x8u
4898 #define I2S_ISR_RFF1_SHIFT 3
4899 #define I2S_ISR_RLS_MASK 0x10u
4900 #define I2S_ISR_RLS_SHIFT 4
4901 #define I2S_ISR_TLS_MASK 0x20u
4902 #define I2S_ISR_TLS_SHIFT 5
4903 #define I2S_ISR_RFS_MASK 0x40u
4904 #define I2S_ISR_RFS_SHIFT 6
4905 #define I2S_ISR_TFS_MASK 0x80u
4906 #define I2S_ISR_TFS_SHIFT 7
4907 #define I2S_ISR_TUE0_MASK 0x100u
4908 #define I2S_ISR_TUE0_SHIFT 8
4909 #define I2S_ISR_TUE1_MASK 0x200u
4910 #define I2S_ISR_TUE1_SHIFT 9
4911 #define I2S_ISR_ROE0_MASK 0x400u
4912 #define I2S_ISR_ROE0_SHIFT 10
4913 #define I2S_ISR_ROE1_MASK 0x800u
4914 #define I2S_ISR_ROE1_SHIFT 11
4915 #define I2S_ISR_TDE0_MASK 0x1000u
4916 #define I2S_ISR_TDE0_SHIFT 12
4917 #define I2S_ISR_TDE1_MASK 0x2000u
4918 #define I2S_ISR_TDE1_SHIFT 13
4919 #define I2S_ISR_RDR0_MASK 0x4000u
4920 #define I2S_ISR_RDR0_SHIFT 14
4921 #define I2S_ISR_RDR1_MASK 0x8000u
4922 #define I2S_ISR_RDR1_SHIFT 15
4923 #define I2S_ISR_RXT_MASK 0x10000u
4924 #define I2S_ISR_RXT_SHIFT 16
4925 #define I2S_ISR_CMDDU_MASK 0x20000u
4926 #define I2S_ISR_CMDDU_SHIFT 17
4927 #define I2S_ISR_CMDAU_MASK 0x40000u
4928 #define I2S_ISR_CMDAU_SHIFT 18
4929 #define I2S_ISR_TRFC_MASK 0x800000u
4930 #define I2S_ISR_TRFC_SHIFT 23
4931 #define I2S_ISR_RFRC_MASK 0x1000000u
4932 #define I2S_ISR_RFRC_SHIFT 24
4933 /* IER Bit Fields */
4934 #define I2S_IER_TFE0EN_MASK 0x1u
4935 #define I2S_IER_TFE0EN_SHIFT 0
4936 #define I2S_IER_TFE1EN_MASK 0x2u
4937 #define I2S_IER_TFE1EN_SHIFT 1
4938 #define I2S_IER_RFF0EN_MASK 0x4u
4939 #define I2S_IER_RFF0EN_SHIFT 2
4940 #define I2S_IER_RFF1EN_MASK 0x8u
4941 #define I2S_IER_RFF1EN_SHIFT 3
4942 #define I2S_IER_RLSEN_MASK 0x10u
4943 #define I2S_IER_RLSEN_SHIFT 4
4944 #define I2S_IER_TLSEN_MASK 0x20u
4945 #define I2S_IER_TLSEN_SHIFT 5
4946 #define I2S_IER_RFSEN_MASK 0x40u
4947 #define I2S_IER_RFSEN_SHIFT 6
4948 #define I2S_IER_TFSEN_MASK 0x80u
4949 #define I2S_IER_TFSEN_SHIFT 7
4950 #define I2S_IER_TUE0EN_MASK 0x100u
4951 #define I2S_IER_TUE0EN_SHIFT 8
4952 #define I2S_IER_TUE1EN_MASK 0x200u
4953 #define I2S_IER_TUE1EN_SHIFT 9
4954 #define I2S_IER_ROE0EN_MASK 0x400u
4955 #define I2S_IER_ROE0EN_SHIFT 10
4956 #define I2S_IER_ROE1EN_MASK 0x800u
4957 #define I2S_IER_ROE1EN_SHIFT 11
4958 #define I2S_IER_TDE0EN_MASK 0x1000u
4959 #define I2S_IER_TDE0EN_SHIFT 12
4960 #define I2S_IER_TDE1EN_MASK 0x2000u
4961 #define I2S_IER_TDE1EN_SHIFT 13
4962 #define I2S_IER_RDR0EN_MASK 0x4000u
4963 #define I2S_IER_RDR0EN_SHIFT 14
4964 #define I2S_IER_RDR1EN_MASK 0x8000u
4965 #define I2S_IER_RDR1EN_SHIFT 15
4966 #define I2S_IER_RXTEN_MASK 0x10000u
4967 #define I2S_IER_RXTEN_SHIFT 16
4968 #define I2S_IER_CMDDUEN_MASK 0x20000u
4969 #define I2S_IER_CMDDUEN_SHIFT 17
4970 #define I2S_IER_CMDAUEN_MASK 0x40000u
4971 #define I2S_IER_CMDAUEN_SHIFT 18
4972 #define I2S_IER_TIE_MASK 0x80000u
4973 #define I2S_IER_TIE_SHIFT 19
4974 #define I2S_IER_TDMAE_MASK 0x100000u
4975 #define I2S_IER_TDMAE_SHIFT 20
4976 #define I2S_IER_RIE_MASK 0x200000u
4977 #define I2S_IER_RIE_SHIFT 21
4978 #define I2S_IER_RDMAE_MASK 0x400000u
4979 #define I2S_IER_RDMAE_SHIFT 22
4980 #define I2S_IER_TFRC_EN_MASK 0x800000u
4981 #define I2S_IER_TFRC_EN_SHIFT 23
4982 #define I2S_IER_RFRC_EN_MASK 0x1000000u
4983 #define I2S_IER_RFRC_EN_SHIFT 24
4984 /* TCR Bit Fields */
4985 #define I2S_TCR_TEFS_MASK 0x1u
4986 #define I2S_TCR_TEFS_SHIFT 0
4987 #define I2S_TCR_TFSL_MASK 0x2u
4988 #define I2S_TCR_TFSL_SHIFT 1
4989 #define I2S_TCR_TFSI_MASK 0x4u
4990 #define I2S_TCR_TFSI_SHIFT 2
4991 #define I2S_TCR_TSCKP_MASK 0x8u
4992 #define I2S_TCR_TSCKP_SHIFT 3
4993 #define I2S_TCR_TSHFD_MASK 0x10u
4994 #define I2S_TCR_TSHFD_SHIFT 4
4995 #define I2S_TCR_TXDIR_MASK 0x20u
4996 #define I2S_TCR_TXDIR_SHIFT 5
4997 #define I2S_TCR_TFDIR_MASK 0x40u
4998 #define I2S_TCR_TFDIR_SHIFT 6
4999 #define I2S_TCR_TFEN0_MASK 0x80u
5000 #define I2S_TCR_TFEN0_SHIFT 7
5001 #define I2S_TCR_TFEN1_MASK 0x100u
5002 #define I2S_TCR_TFEN1_SHIFT 8
5003 #define I2S_TCR_TXBIT0_MASK 0x200u
5004 #define I2S_TCR_TXBIT0_SHIFT 9
5005 /* RCR Bit Fields */
5006 #define I2S_RCR_REFS_MASK 0x1u
5007 #define I2S_RCR_REFS_SHIFT 0
5008 #define I2S_RCR_RFSL_MASK 0x2u
5009 #define I2S_RCR_RFSL_SHIFT 1
5010 #define I2S_RCR_RFSI_MASK 0x4u
5011 #define I2S_RCR_RFSI_SHIFT 2
5012 #define I2S_RCR_RSCKP_MASK 0x8u
5013 #define I2S_RCR_RSCKP_SHIFT 3
5014 #define I2S_RCR_RSHFD_MASK 0x10u
5015 #define I2S_RCR_RSHFD_SHIFT 4
5016 #define I2S_RCR_RXDIR_MASK 0x20u
5017 #define I2S_RCR_RXDIR_SHIFT 5
5018 #define I2S_RCR_RFDIR_MASK 0x40u
5019 #define I2S_RCR_RFDIR_SHIFT 6
5020 #define I2S_RCR_RFEN0_MASK 0x80u
5021 #define I2S_RCR_RFEN0_SHIFT 7
5022 #define I2S_RCR_RFEN1_MASK 0x100u
5023 #define I2S_RCR_RFEN1_SHIFT 8
5024 #define I2S_RCR_RXBIT0_MASK 0x200u
5025 #define I2S_RCR_RXBIT0_SHIFT 9
5026 #define I2S_RCR_RXEXT_MASK 0x400u
5027 #define I2S_RCR_RXEXT_SHIFT 10
5028 /* TCCR Bit Fields */
5029 #define I2S_TCCR_PM_MASK 0xFFu
5030 #define I2S_TCCR_PM_SHIFT 0
5031 #define I2S_TCCR_PM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_PM_SHIFT))&I2S_TCCR_PM_MASK)
5032 #define I2S_TCCR_DC_MASK 0x1F00u
5033 #define I2S_TCCR_DC_SHIFT 8
5034 #define I2S_TCCR_DC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_DC_SHIFT))&I2S_TCCR_DC_MASK)
5035 #define I2S_TCCR_WL_MASK 0x1E000u
5036 #define I2S_TCCR_WL_SHIFT 13
5037 #define I2S_TCCR_WL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_WL_SHIFT))&I2S_TCCR_WL_MASK)
5038 #define I2S_TCCR_PSR_MASK 0x20000u
5039 #define I2S_TCCR_PSR_SHIFT 17
5040 #define I2S_TCCR_DIV2_MASK 0x40000u
5041 #define I2S_TCCR_DIV2_SHIFT 18
5042 /* RCCR Bit Fields */
5043 #define I2S_RCCR_PM_MASK 0xFFu
5044 #define I2S_RCCR_PM_SHIFT 0
5045 #define I2S_RCCR_PM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_PM_SHIFT))&I2S_RCCR_PM_MASK)
5046 #define I2S_RCCR_DC_MASK 0x1F00u
5047 #define I2S_RCCR_DC_SHIFT 8
5048 #define I2S_RCCR_DC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_DC_SHIFT))&I2S_RCCR_DC_MASK)
5049 #define I2S_RCCR_WL_MASK 0x1E000u
5050 #define I2S_RCCR_WL_SHIFT 13
5051 #define I2S_RCCR_WL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_WL_SHIFT))&I2S_RCCR_WL_MASK)
5052 #define I2S_RCCR_PSR_MASK 0x20000u
5053 #define I2S_RCCR_PSR_SHIFT 17
5054 #define I2S_RCCR_DIV2_MASK 0x40000u
5055 #define I2S_RCCR_DIV2_SHIFT 18
5056 /* FCSR Bit Fields */
5057 #define I2S_FCSR_TFWM0_MASK 0xFu
5058 #define I2S_FCSR_TFWM0_SHIFT 0
5059 #define I2S_FCSR_TFWM0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM0_SHIFT))&I2S_FCSR_TFWM0_MASK)
5060 #define I2S_FCSR_RFWM0_MASK 0xF0u
5061 #define I2S_FCSR_RFWM0_SHIFT 4
5062 #define I2S_FCSR_RFWM0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM0_SHIFT))&I2S_FCSR_RFWM0_MASK)
5063 #define I2S_FCSR_TFCNT0_MASK 0xF00u
5064 #define I2S_FCSR_TFCNT0_SHIFT 8
5065 #define I2S_FCSR_TFCNT0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT0_SHIFT))&I2S_FCSR_TFCNT0_MASK)
5066 #define I2S_FCSR_RFCNT0_MASK 0xF000u
5067 #define I2S_FCSR_RFCNT0_SHIFT 12
5068 #define I2S_FCSR_RFCNT0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT0_SHIFT))&I2S_FCSR_RFCNT0_MASK)
5069 #define I2S_FCSR_TFWM1_MASK 0xF0000u
5070 #define I2S_FCSR_TFWM1_SHIFT 16
5071 #define I2S_FCSR_TFWM1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM1_SHIFT))&I2S_FCSR_TFWM1_MASK)
5072 #define I2S_FCSR_RFWM1_MASK 0xF00000u
5073 #define I2S_FCSR_RFWM1_SHIFT 20
5074 #define I2S_FCSR_RFWM1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM1_SHIFT))&I2S_FCSR_RFWM1_MASK)
5075 #define I2S_FCSR_TFCNT1_MASK 0xF000000u
5076 #define I2S_FCSR_TFCNT1_SHIFT 24
5077 #define I2S_FCSR_TFCNT1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT1_SHIFT))&I2S_FCSR_TFCNT1_MASK)
5078 #define I2S_FCSR_RFCNT1_MASK 0xF0000000u
5079 #define I2S_FCSR_RFCNT1_SHIFT 28
5080 #define I2S_FCSR_RFCNT1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT1_SHIFT))&I2S_FCSR_RFCNT1_MASK)
5081 /* ACNT Bit Fields */
5082 #define I2S_ACNT_AC97EN_MASK 0x1u
5083 #define I2S_ACNT_AC97EN_SHIFT 0
5084 #define I2S_ACNT_FV_MASK 0x2u
5085 #define I2S_ACNT_FV_SHIFT 1
5086 #define I2S_ACNT_TIF_MASK 0x4u
5087 #define I2S_ACNT_TIF_SHIFT 2
5088 #define I2S_ACNT_RD_MASK 0x8u
5089 #define I2S_ACNT_RD_SHIFT 3
5090 #define I2S_ACNT_WR_MASK 0x10u
5091 #define I2S_ACNT_WR_SHIFT 4
5092 #define I2S_ACNT_FRDIV_MASK 0x7E0u
5093 #define I2S_ACNT_FRDIV_SHIFT 5
5094 #define I2S_ACNT_FRDIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACNT_FRDIV_SHIFT))&I2S_ACNT_FRDIV_MASK)
5095 /* ACADD Bit Fields */
5096 #define I2S_ACADD_ACADD_MASK 0x7FFFFu
5097 #define I2S_ACADD_ACADD_SHIFT 0
5098 #define I2S_ACADD_ACADD(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACADD_ACADD_SHIFT))&I2S_ACADD_ACADD_MASK)
5099 /* ACDAT Bit Fields */
5100 #define I2S_ACDAT_ACDAT_MASK 0xFFFFFu
5101 #define I2S_ACDAT_ACDAT_SHIFT 0
5102 #define I2S_ACDAT_ACDAT(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACDAT_ACDAT_SHIFT))&I2S_ACDAT_ACDAT_MASK)
5103 /* ATAG Bit Fields */
5104 #define I2S_ATAG_ATAG_MASK 0xFFFFu
5105 #define I2S_ATAG_ATAG_SHIFT 0
5106 #define I2S_ATAG_ATAG(x) (((uint32_t)(((uint32_t)(x))<<I2S_ATAG_ATAG_SHIFT))&I2S_ATAG_ATAG_MASK)
5107 /* TMSK Bit Fields */
5108 #define I2S_TMSK_TMSK_MASK 0xFFFFFFFFu
5109 #define I2S_TMSK_TMSK_SHIFT 0
5110 #define I2S_TMSK_TMSK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMSK_TMSK_SHIFT))&I2S_TMSK_TMSK_MASK)
5111 /* RMSK Bit Fields */
5112 #define I2S_RMSK_RMSK_MASK 0xFFFFFFFFu
5113 #define I2S_RMSK_RMSK_SHIFT 0
5114 #define I2S_RMSK_RMSK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMSK_RMSK_SHIFT))&I2S_RMSK_RMSK_MASK)
5115 /* ACCST Bit Fields */
5116 #define I2S_ACCST_ACCST_MASK 0x3FFu
5117 #define I2S_ACCST_ACCST_SHIFT 0
5118 #define I2S_ACCST_ACCST(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACCST_ACCST_SHIFT))&I2S_ACCST_ACCST_MASK)
5119 /* ACCEN Bit Fields */
5120 #define I2S_ACCEN_ACCEN_MASK 0x3FFu
5121 #define I2S_ACCEN_ACCEN_SHIFT 0
5122 #define I2S_ACCEN_ACCEN(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACCEN_ACCEN_SHIFT))&I2S_ACCEN_ACCEN_MASK)
5123 /* ACCDIS Bit Fields */
5124 #define I2S_ACCDIS_ACCDIS_MASK 0x3FFu
5125 #define I2S_ACCDIS_ACCDIS_SHIFT 0
5126 #define I2S_ACCDIS_ACCDIS(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACCDIS_ACCDIS_SHIFT))&I2S_ACCDIS_ACCDIS_MASK)
5127 
5128 /**
5129  * @}
5130  */ /* end of group I2S_Register_Masks */
5131 
5132 
5133 /* I2S - Peripheral instance base addresses */
5134 /** Peripheral I2S0 base address */
5135 #define I2S0_BASE (0x4002F000u)
5136 /** Peripheral I2S0 base pointer */
5137 #define I2S0 ((I2S_Type *)I2S0_BASE)
5138 
5139 /**
5140  * @}
5141  */ /* end of group I2S_Peripheral_Access_Layer */
5142 
5143 
5144 /* ----------------------------------------------------------------------------
5145  -- LLWU Peripheral Access Layer
5146  ---------------------------------------------------------------------------- */
5147 
5148 /**
5149  * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
5150  * @{
5151  */
5152 
5153 /** LLWU - Register Layout Typedef */
5154 typedef struct {
5155  __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
5156  __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
5157  __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
5158  __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
5159  __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
5160  __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
5161  __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
5162  __IO uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
5163  __IO uint8_t CS; /**< LLWU Control and Status Register, offset: 0x8 */
5164 } LLWU_Type;
5165 
5166 /* ----------------------------------------------------------------------------
5167  -- LLWU Register Masks
5168  ---------------------------------------------------------------------------- */
5169 
5170 /**
5171  * @addtogroup LLWU_Register_Masks LLWU Register Masks
5172  * @{
5173  */
5174 
5175 /* PE1 Bit Fields */
5176 #define LLWU_PE1_WUPE0_MASK 0x3u
5177 #define LLWU_PE1_WUPE0_SHIFT 0
5178 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
5179 #define LLWU_PE1_WUPE1_MASK 0xCu
5180 #define LLWU_PE1_WUPE1_SHIFT 2
5181 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
5182 #define LLWU_PE1_WUPE2_MASK 0x30u
5183 #define LLWU_PE1_WUPE2_SHIFT 4
5184 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
5185 #define LLWU_PE1_WUPE3_MASK 0xC0u
5186 #define LLWU_PE1_WUPE3_SHIFT 6
5187 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
5188 /* PE2 Bit Fields */
5189 #define LLWU_PE2_WUPE4_MASK 0x3u
5190 #define LLWU_PE2_WUPE4_SHIFT 0
5191 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
5192 #define LLWU_PE2_WUPE5_MASK 0xCu
5193 #define LLWU_PE2_WUPE5_SHIFT 2
5194 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
5195 #define LLWU_PE2_WUPE6_MASK 0x30u
5196 #define LLWU_PE2_WUPE6_SHIFT 4
5197 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
5198 #define LLWU_PE2_WUPE7_MASK 0xC0u
5199 #define LLWU_PE2_WUPE7_SHIFT 6
5200 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
5201 /* PE3 Bit Fields */
5202 #define LLWU_PE3_WUPE8_MASK 0x3u
5203 #define LLWU_PE3_WUPE8_SHIFT 0
5204 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
5205 #define LLWU_PE3_WUPE9_MASK 0xCu
5206 #define LLWU_PE3_WUPE9_SHIFT 2
5207 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
5208 #define LLWU_PE3_WUPE10_MASK 0x30u
5209 #define LLWU_PE3_WUPE10_SHIFT 4
5210 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
5211 #define LLWU_PE3_WUPE11_MASK 0xC0u
5212 #define LLWU_PE3_WUPE11_SHIFT 6
5213 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
5214 /* PE4 Bit Fields */
5215 #define LLWU_PE4_WUPE12_MASK 0x3u
5216 #define LLWU_PE4_WUPE12_SHIFT 0
5217 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
5218 #define LLWU_PE4_WUPE13_MASK 0xCu
5219 #define LLWU_PE4_WUPE13_SHIFT 2
5220 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
5221 #define LLWU_PE4_WUPE14_MASK 0x30u
5222 #define LLWU_PE4_WUPE14_SHIFT 4
5223 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
5224 #define LLWU_PE4_WUPE15_MASK 0xC0u
5225 #define LLWU_PE4_WUPE15_SHIFT 6
5226 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
5227 /* ME Bit Fields */
5228 #define LLWU_ME_WUME0_MASK 0x1u
5229 #define LLWU_ME_WUME0_SHIFT 0
5230 #define LLWU_ME_WUME1_MASK 0x2u
5231 #define LLWU_ME_WUME1_SHIFT 1
5232 #define LLWU_ME_WUME2_MASK 0x4u
5233 #define LLWU_ME_WUME2_SHIFT 2
5234 #define LLWU_ME_WUME3_MASK 0x8u
5235 #define LLWU_ME_WUME3_SHIFT 3
5236 #define LLWU_ME_WUME4_MASK 0x10u
5237 #define LLWU_ME_WUME4_SHIFT 4
5238 #define LLWU_ME_WUME5_MASK 0x20u
5239 #define LLWU_ME_WUME5_SHIFT 5
5240 #define LLWU_ME_WUME6_MASK 0x40u
5241 #define LLWU_ME_WUME6_SHIFT 6
5242 #define LLWU_ME_WUME7_MASK 0x80u
5243 #define LLWU_ME_WUME7_SHIFT 7
5244 /* F1 Bit Fields */
5245 #define LLWU_F1_WUF0_MASK 0x1u
5246 #define LLWU_F1_WUF0_SHIFT 0
5247 #define LLWU_F1_WUF1_MASK 0x2u
5248 #define LLWU_F1_WUF1_SHIFT 1
5249 #define LLWU_F1_WUF2_MASK 0x4u
5250 #define LLWU_F1_WUF2_SHIFT 2
5251 #define LLWU_F1_WUF3_MASK 0x8u
5252 #define LLWU_F1_WUF3_SHIFT 3
5253 #define LLWU_F1_WUF4_MASK 0x10u
5254 #define LLWU_F1_WUF4_SHIFT 4
5255 #define LLWU_F1_WUF5_MASK 0x20u
5256 #define LLWU_F1_WUF5_SHIFT 5
5257 #define LLWU_F1_WUF6_MASK 0x40u
5258 #define LLWU_F1_WUF6_SHIFT 6
5259 #define LLWU_F1_WUF7_MASK 0x80u
5260 #define LLWU_F1_WUF7_SHIFT 7
5261 /* F2 Bit Fields */
5262 #define LLWU_F2_WUF8_MASK 0x1u
5263 #define LLWU_F2_WUF8_SHIFT 0
5264 #define LLWU_F2_WUF9_MASK 0x2u
5265 #define LLWU_F2_WUF9_SHIFT 1
5266 #define LLWU_F2_WUF10_MASK 0x4u
5267 #define LLWU_F2_WUF10_SHIFT 2
5268 #define LLWU_F2_WUF11_MASK 0x8u
5269 #define LLWU_F2_WUF11_SHIFT 3
5270 #define LLWU_F2_WUF12_MASK 0x10u
5271 #define LLWU_F2_WUF12_SHIFT 4
5272 #define LLWU_F2_WUF13_MASK 0x20u
5273 #define LLWU_F2_WUF13_SHIFT 5
5274 #define LLWU_F2_WUF14_MASK 0x40u
5275 #define LLWU_F2_WUF14_SHIFT 6
5276 #define LLWU_F2_WUF15_MASK 0x80u
5277 #define LLWU_F2_WUF15_SHIFT 7
5278 /* F3 Bit Fields */
5279 #define LLWU_F3_MWUF0_MASK 0x1u
5280 #define LLWU_F3_MWUF0_SHIFT 0
5281 #define LLWU_F3_MWUF1_MASK 0x2u
5282 #define LLWU_F3_MWUF1_SHIFT 1
5283 #define LLWU_F3_MWUF2_MASK 0x4u
5284 #define LLWU_F3_MWUF2_SHIFT 2
5285 #define LLWU_F3_MWUF3_MASK 0x8u
5286 #define LLWU_F3_MWUF3_SHIFT 3
5287 #define LLWU_F3_MWUF4_MASK 0x10u
5288 #define LLWU_F3_MWUF4_SHIFT 4
5289 #define LLWU_F3_MWUF5_MASK 0x20u
5290 #define LLWU_F3_MWUF5_SHIFT 5
5291 #define LLWU_F3_MWUF6_MASK 0x40u
5292 #define LLWU_F3_MWUF6_SHIFT 6
5293 #define LLWU_F3_MWUF7_MASK 0x80u
5294 #define LLWU_F3_MWUF7_SHIFT 7
5295 /* CS Bit Fields */
5296 #define LLWU_CS_FLTR_MASK 0x1u
5297 #define LLWU_CS_FLTR_SHIFT 0
5298 #define LLWU_CS_FLTEP_MASK 0x2u
5299 #define LLWU_CS_FLTEP_SHIFT 1
5300 #define LLWU_CS_ACKISO_MASK 0x80u
5301 #define LLWU_CS_ACKISO_SHIFT 7
5302 
5303 /**
5304  * @}
5305  */ /* end of group LLWU_Register_Masks */
5306 
5307 
5308 /* LLWU - Peripheral instance base addresses */
5309 /** Peripheral LLWU base address */
5310 #define LLWU_BASE (0x4007C000u)
5311 /** Peripheral LLWU base pointer */
5312 #define LLWU ((LLWU_Type *)LLWU_BASE)
5313 
5314 /**
5315  * @}
5316  */ /* end of group LLWU_Peripheral_Access_Layer */
5317 
5318 
5319 /* ----------------------------------------------------------------------------
5320  -- LPTMR Peripheral Access Layer
5321  ---------------------------------------------------------------------------- */
5322 
5323 /**
5324  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
5325  * @{
5326  */
5327 
5328 /** LPTMR - Register Layout Typedef */
5329 typedef struct {
5330  __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
5331  __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
5332  __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
5333  __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
5334 } LPTMR_Type;
5335 
5336 /* ----------------------------------------------------------------------------
5337  -- LPTMR Register Masks
5338  ---------------------------------------------------------------------------- */
5339 
5340 /**
5341  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
5342  * @{
5343  */
5344 
5345 /* CSR Bit Fields */
5346 #define LPTMR_CSR_TEN_MASK 0x1u
5347 #define LPTMR_CSR_TEN_SHIFT 0
5348 #define LPTMR_CSR_TMS_MASK 0x2u
5349 #define LPTMR_CSR_TMS_SHIFT 1
5350 #define LPTMR_CSR_TFC_MASK 0x4u
5351 #define LPTMR_CSR_TFC_SHIFT 2
5352 #define LPTMR_CSR_TPP_MASK 0x8u
5353 #define LPTMR_CSR_TPP_SHIFT 3
5354 #define LPTMR_CSR_TPS_MASK 0x30u
5355 #define LPTMR_CSR_TPS_SHIFT 4
5356 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
5357 #define LPTMR_CSR_TIE_MASK 0x40u
5358 #define LPTMR_CSR_TIE_SHIFT 6
5359 #define LPTMR_CSR_TCF_MASK 0x80u
5360 #define LPTMR_CSR_TCF_SHIFT 7
5361 /* PSR Bit Fields */
5362 #define LPTMR_PSR_PCS_MASK 0x3u
5363 #define LPTMR_PSR_PCS_SHIFT 0
5364 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
5365 #define LPTMR_PSR_PBYP_MASK 0x4u
5366 #define LPTMR_PSR_PBYP_SHIFT 2
5367 #define LPTMR_PSR_PRESCALE_MASK 0x78u
5368 #define LPTMR_PSR_PRESCALE_SHIFT 3
5369 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
5370 /* CMR Bit Fields */
5371 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
5372 #define LPTMR_CMR_COMPARE_SHIFT 0
5373 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
5374 /* CNR Bit Fields */
5375 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
5376 #define LPTMR_CNR_COUNTER_SHIFT 0
5377 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
5378 
5379 /**
5380  * @}
5381  */ /* end of group LPTMR_Register_Masks */
5382 
5383 
5384 /* LPTMR - Peripheral instance base addresses */
5385 /** Peripheral LPTMR0 base address */
5386 #define LPTMR0_BASE (0x40040000u)
5387 /** Peripheral LPTMR0 base pointer */
5388 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
5389 
5390 /**
5391  * @}
5392  */ /* end of group LPTMR_Peripheral_Access_Layer */
5393 
5394 
5395 /* ----------------------------------------------------------------------------
5396  -- MC Peripheral Access Layer
5397  ---------------------------------------------------------------------------- */
5398 
5399 /**
5400  * @addtogroup MC_Peripheral_Access_Layer MC Peripheral Access Layer
5401  * @{
5402  */
5403 
5404 /** MC - Register Layout Typedef */
5405 typedef struct {
5406  __I uint8_t SRSH; /**< System Reset Status Register High, offset: 0x0 */
5407  __I uint8_t SRSL; /**< System Reset Status Register Low, offset: 0x1 */
5408  __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x2 */
5409  __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x3 */
5410 } MC_Type;
5411 
5412 /* ----------------------------------------------------------------------------
5413  -- MC Register Masks
5414  ---------------------------------------------------------------------------- */
5415 
5416 /**
5417  * @addtogroup MC_Register_Masks MC Register Masks
5418  * @{
5419  */
5420 
5421 /* SRSH Bit Fields */
5422 #define MC_SRSH_JTAG_MASK 0x1u
5423 #define MC_SRSH_JTAG_SHIFT 0
5424 #define MC_SRSH_LOCKUP_MASK 0x2u
5425 #define MC_SRSH_LOCKUP_SHIFT 1
5426 #define MC_SRSH_SW_MASK 0x4u
5427 #define MC_SRSH_SW_SHIFT 2
5428 /* SRSL Bit Fields */
5429 #define MC_SRSL_WAKEUP_MASK 0x1u
5430 #define MC_SRSL_WAKEUP_SHIFT 0
5431 #define MC_SRSL_LVD_MASK 0x2u
5432 #define MC_SRSL_LVD_SHIFT 1
5433 #define MC_SRSL_LOC_MASK 0x4u
5434 #define MC_SRSL_LOC_SHIFT 2
5435 #define MC_SRSL_COP_MASK 0x20u
5436 #define MC_SRSL_COP_SHIFT 5
5437 #define MC_SRSL_PIN_MASK 0x40u
5438 #define MC_SRSL_PIN_SHIFT 6
5439 #define MC_SRSL_POR_MASK 0x80u
5440 #define MC_SRSL_POR_SHIFT 7
5441 /* PMPROT Bit Fields */
5442 #define MC_PMPROT_AVLLS1_MASK 0x1u
5443 #define MC_PMPROT_AVLLS1_SHIFT 0
5444 #define MC_PMPROT_AVLLS2_MASK 0x2u
5445 #define MC_PMPROT_AVLLS2_SHIFT 1
5446 #define MC_PMPROT_AVLLS3_MASK 0x4u
5447 #define MC_PMPROT_AVLLS3_SHIFT 2
5448 #define MC_PMPROT_ALLS_MASK 0x10u
5449 #define MC_PMPROT_ALLS_SHIFT 4
5450 #define MC_PMPROT_AVLP_MASK 0x20u
5451 #define MC_PMPROT_AVLP_SHIFT 5
5452 /* PMCTRL Bit Fields */
5453 #define MC_PMCTRL_LPLLSM_MASK 0x7u
5454 #define MC_PMCTRL_LPLLSM_SHIFT 0
5455 #define MC_PMCTRL_LPLLSM(x) (((uint8_t)(((uint8_t)(x))<<MC_PMCTRL_LPLLSM_SHIFT))&MC_PMCTRL_LPLLSM_MASK)
5456 #define MC_PMCTRL_RUNM_MASK 0x60u
5457 #define MC_PMCTRL_RUNM_SHIFT 5
5458 #define MC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<MC_PMCTRL_RUNM_SHIFT))&MC_PMCTRL_RUNM_MASK)
5459 #define MC_PMCTRL_LPWUI_MASK 0x80u
5460 #define MC_PMCTRL_LPWUI_SHIFT 7
5461 
5462 /**
5463  * @}
5464  */ /* end of group MC_Register_Masks */
5465 
5466 
5467 /* MC - Peripheral instance base addresses */
5468 /** Peripheral MC base address */
5469 #define MC_BASE (0x4007E000u)
5470 /** Peripheral MC base pointer */
5471 #define MC ((MC_Type *)MC_BASE)
5472 
5473 /**
5474  * @}
5475  */ /* end of group MC_Peripheral_Access_Layer */
5476 
5477 
5478 /* ----------------------------------------------------------------------------
5479  -- MCG Peripheral Access Layer
5480  ---------------------------------------------------------------------------- */
5481 
5482 /**
5483  * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
5484  * @{
5485  */
5486 
5487 /** MCG - Register Layout Typedef */
5488 typedef struct {
5489  __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
5490  __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
5491  __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
5492  __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
5493  __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
5494  __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
5495  __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
5496  uint8_t RESERVED_0[1];
5497  __IO uint8_t ATC; /**< MCG Auto Trim Control Register, offset: 0x8 */
5498  uint8_t RESERVED_1[1];
5499  __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
5500  __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
5501 } MCG_Type;
5502 
5503 /* ----------------------------------------------------------------------------
5504  -- MCG Register Masks
5505  ---------------------------------------------------------------------------- */
5506 
5507 /**
5508  * @addtogroup MCG_Register_Masks MCG Register Masks
5509  * @{
5510  */
5511 
5512 /* C1 Bit Fields */
5513 #define MCG_C1_IREFSTEN_MASK 0x1u
5514 #define MCG_C1_IREFSTEN_SHIFT 0
5515 #define MCG_C1_IRCLKEN_MASK 0x2u
5516 #define MCG_C1_IRCLKEN_SHIFT 1
5517 #define MCG_C1_IREFS_MASK 0x4u
5518 #define MCG_C1_IREFS_SHIFT 2
5519 #define MCG_C1_FRDIV_MASK 0x38u
5520 #define MCG_C1_FRDIV_SHIFT 3
5521 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
5522 #define MCG_C1_CLKS_MASK 0xC0u
5523 #define MCG_C1_CLKS_SHIFT 6
5524 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
5525 /* C2 Bit Fields */
5526 #define MCG_C2_IRCS_MASK 0x1u
5527 #define MCG_C2_IRCS_SHIFT 0
5528 #define MCG_C2_LP_MASK 0x2u
5529 #define MCG_C2_LP_SHIFT 1
5530 #define MCG_C2_EREFS_MASK 0x4u
5531 #define MCG_C2_EREFS_SHIFT 2
5532 #define MCG_C2_HGO_MASK 0x8u
5533 #define MCG_C2_HGO_SHIFT 3
5534 #define MCG_C2_RANGE_MASK 0x30u
5535 #define MCG_C2_RANGE_SHIFT 4
5536 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
5537 /* C3 Bit Fields */
5538 #define MCG_C3_SCTRIM_MASK 0xFFu
5539 #define MCG_C3_SCTRIM_SHIFT 0
5540 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
5541 /* C4 Bit Fields */
5542 #define MCG_C4_SCFTRIM_MASK 0x1u
5543 #define MCG_C4_SCFTRIM_SHIFT 0
5544 #define MCG_C4_FCTRIM_MASK 0x1Eu
5545 #define MCG_C4_FCTRIM_SHIFT 1
5546 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
5547 #define MCG_C4_DRST_DRS_MASK 0x60u
5548 #define MCG_C4_DRST_DRS_SHIFT 5
5549 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
5550 #define MCG_C4_DMX32_MASK 0x80u
5551 #define MCG_C4_DMX32_SHIFT 7
5552 /* C5 Bit Fields */
5553 #define MCG_C5_PRDIV_MASK 0x1Fu
5554 #define MCG_C5_PRDIV_SHIFT 0
5555 #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV_SHIFT))&MCG_C5_PRDIV_MASK)
5556 #define MCG_C5_PLLSTEN_MASK 0x20u
5557 #define MCG_C5_PLLSTEN_SHIFT 5
5558 #define MCG_C5_PLLCLKEN_MASK 0x40u
5559 #define MCG_C5_PLLCLKEN_SHIFT 6
5560 /* C6 Bit Fields */
5561 #define MCG_C6_VDIV_MASK 0x1Fu
5562 #define MCG_C6_VDIV_SHIFT 0
5563 #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV_SHIFT))&MCG_C6_VDIV_MASK)
5564 #define MCG_C6_CME_MASK 0x20u
5565 #define MCG_C6_CME_SHIFT 5
5566 #define MCG_C6_PLLS_MASK 0x40u
5567 #define MCG_C6_PLLS_SHIFT 6
5568 #define MCG_C6_LOLIE_MASK 0x80u
5569 #define MCG_C6_LOLIE_SHIFT 7
5570 /* S Bit Fields */
5571 #define MCG_S_IRCST_MASK 0x1u
5572 #define MCG_S_IRCST_SHIFT 0
5573 #define MCG_S_OSCINIT_MASK 0x2u
5574 #define MCG_S_OSCINIT_SHIFT 1
5575 #define MCG_S_CLKST_MASK 0xCu
5576 #define MCG_S_CLKST_SHIFT 2
5577 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
5578 #define MCG_S_IREFST_MASK 0x10u
5579 #define MCG_S_IREFST_SHIFT 4
5580 #define MCG_S_PLLST_MASK 0x20u
5581 #define MCG_S_PLLST_SHIFT 5
5582 #define MCG_S_LOCK_MASK 0x40u
5583 #define MCG_S_LOCK_SHIFT 6
5584 #define MCG_S_LOLS_MASK 0x80u
5585 #define MCG_S_LOLS_SHIFT 7
5586 /* ATC Bit Fields */
5587 #define MCG_ATC_ATMF_MASK 0x20u
5588 #define MCG_ATC_ATMF_SHIFT 5
5589 #define MCG_ATC_ATMS_MASK 0x40u
5590 #define MCG_ATC_ATMS_SHIFT 6
5591 #define MCG_ATC_ATME_MASK 0x80u
5592 #define MCG_ATC_ATME_SHIFT 7
5593 /* ATCVH Bit Fields */
5594 #define MCG_ATCVH_ATCVH_MASK 0xFFu
5595 #define MCG_ATCVH_ATCVH_SHIFT 0
5596 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
5597 /* ATCVL Bit Fields */
5598 #define MCG_ATCVL_ATCVL_MASK 0xFFu
5599 #define MCG_ATCVL_ATCVL_SHIFT 0
5600 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
5601 
5602 /**
5603  * @}
5604  */ /* end of group MCG_Register_Masks */
5605 
5606 
5607 /* MCG - Peripheral instance base addresses */
5608 /** Peripheral MCG base address */
5609 #define MCG_BASE (0x40064000u)
5610 /** Peripheral MCG base pointer */
5611 #define MCG ((MCG_Type *)MCG_BASE)
5612 
5613 /**
5614  * @}
5615  */ /* end of group MCG_Peripheral_Access_Layer */
5616 
5617 
5618 /* ----------------------------------------------------------------------------
5619  -- MCM Peripheral Access Layer
5620  ---------------------------------------------------------------------------- */
5621 
5622 /**
5623  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
5624  * @{
5625  */
5626 
5627 /** MCM - Register Layout Typedef */
5628 typedef struct {
5629  uint8_t RESERVED_0[8];
5630  __I uint16_t PLASC; /**< Crossbar switch (AXBS) slave configuration, offset: 0x8 */
5631  __I uint16_t PLAMC; /**< Crossbar switch (AXBS) master configuration, offset: 0xA */
5632  __IO uint32_t SRAMAP; /**< SRAM arbitration and protection, offset: 0xC */
5633  __IO uint32_t ISR; /**< Interrupt status register, offset: 0x10 */
5634  __IO uint32_t ETBCC; /**< ETB counter control register, offset: 0x14 */
5635  __IO uint32_t ETBRL; /**< ETB reload register, offset: 0x18 */
5636  __I uint32_t ETBCNT; /**< ETB counter value register, offset: 0x1C */
5637 } MCM_Type;
5638 
5639 /* ----------------------------------------------------------------------------
5640  -- MCM Register Masks
5641  ---------------------------------------------------------------------------- */
5642 
5643 /**
5644  * @addtogroup MCM_Register_Masks MCM Register Masks
5645  * @{
5646  */
5647 
5648 /* PLASC Bit Fields */
5649 #define MCM_PLASC_ASC_MASK 0xFFu
5650 #define MCM_PLASC_ASC_SHIFT 0
5651 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
5652 /* PLAMC Bit Fields */
5653 #define MCM_PLAMC_AMC_MASK 0xFFu
5654 #define MCM_PLAMC_AMC_SHIFT 0
5655 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
5656 /* SRAMAP Bit Fields */
5657 #define MCM_SRAMAP_SRAMUAP_MASK 0x3000000u
5658 #define MCM_SRAMAP_SRAMUAP_SHIFT 24
5659 #define MCM_SRAMAP_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMUAP_SHIFT))&MCM_SRAMAP_SRAMUAP_MASK)
5660 #define MCM_SRAMAP_SRAMUWP_MASK 0x4000000u
5661 #define MCM_SRAMAP_SRAMUWP_SHIFT 26
5662 #define MCM_SRAMAP_SRAMLAP_MASK 0x30000000u
5663 #define MCM_SRAMAP_SRAMLAP_SHIFT 28
5664 #define MCM_SRAMAP_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMLAP_SHIFT))&MCM_SRAMAP_SRAMLAP_MASK)
5665 #define MCM_SRAMAP_SRAMLWP_MASK 0x40000000u
5666 #define MCM_SRAMAP_SRAMLWP_SHIFT 30
5667 /* ISR Bit Fields */
5668 #define MCM_ISR_IRQ_MASK 0x2u
5669 #define MCM_ISR_IRQ_SHIFT 1
5670 #define MCM_ISR_NMI_MASK 0x4u
5671 #define MCM_ISR_NMI_SHIFT 2
5672 /* ETBCC Bit Fields */
5673 #define MCM_ETBCC_CNTEN_MASK 0x1u
5674 #define MCM_ETBCC_CNTEN_SHIFT 0
5675 #define MCM_ETBCC_RSPT_MASK 0x6u
5676 #define MCM_ETBCC_RSPT_SHIFT 1
5677 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
5678 #define MCM_ETBCC_RLRQ_MASK 0x8u
5679 #define MCM_ETBCC_RLRQ_SHIFT 3
5680 #define MCM_ETBCC_ETDIS_MASK 0x10u
5681 #define MCM_ETBCC_ETDIS_SHIFT 4
5682 #define MCM_ETBCC_ITDIS_MASK 0x20u
5683 #define MCM_ETBCC_ITDIS_SHIFT 5
5684 /* ETBRL Bit Fields */
5685 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
5686 #define MCM_ETBRL_RELOAD_SHIFT 0
5687 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
5688 /* ETBCNT Bit Fields */
5689 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
5690 #define MCM_ETBCNT_COUNTER_SHIFT 0
5691 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
5692 
5693 /**
5694  * @}
5695  */ /* end of group MCM_Register_Masks */
5696 
5697 
5698 /* MCM - Peripheral instance base addresses */
5699 /** Peripheral MCM base address */
5700 #define MCM_BASE (0xE0080000u)
5701 /** Peripheral MCM base pointer */
5702 #define MCM ((MCM_Type *)MCM_BASE)
5703 
5704 /**
5705  * @}
5706  */ /* end of group MCM_Peripheral_Access_Layer */
5707 
5708 
5709 /* ----------------------------------------------------------------------------
5710  -- MPU Peripheral Access Layer
5711  ---------------------------------------------------------------------------- */
5712 
5713 /**
5714  * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
5715  * @{
5716  */
5717 
5718 /** MPU - Register Layout Typedef */
5719 typedef struct {
5720  __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
5721  uint8_t RESERVED_0[12];
5722  struct { /* offset: 0x10, array step: 0x8 */
5723  __I uint32_t EAR; /**< Error Address Register, Slave Port n, array offset: 0x10, array step: 0x8 */
5724  __I uint32_t EDR; /**< Error Detail Register, Slave Port n, array offset: 0x14, array step: 0x8 */
5725  } SP[5];
5726  uint8_t RESERVED_1[968];
5727  __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
5728  uint8_t RESERVED_2[832];
5729  __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
5730 } MPU_Type;
5731 
5732 /* ----------------------------------------------------------------------------
5733  -- MPU Register Masks
5734  ---------------------------------------------------------------------------- */
5735 
5736 /**
5737  * @addtogroup MPU_Register_Masks MPU Register Masks
5738  * @{
5739  */
5740 
5741 /* CESR Bit Fields */
5742 #define MPU_CESR_VLD_MASK 0x1u
5743 #define MPU_CESR_VLD_SHIFT 0
5744 #define MPU_CESR_NRGD_MASK 0xF00u
5745 #define MPU_CESR_NRGD_SHIFT 8
5746 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
5747 #define MPU_CESR_NSP_MASK 0xF000u
5748 #define MPU_CESR_NSP_SHIFT 12
5749 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
5750 #define MPU_CESR_HRL_MASK 0xF0000u
5751 #define MPU_CESR_HRL_SHIFT 16
5752 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
5753 #define MPU_CESR_SPERR_MASK 0xF8000000u
5754 #define MPU_CESR_SPERR_SHIFT 27
5755 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
5756 /* EAR Bit Fields */
5757 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
5758 #define MPU_EAR_EADDR_SHIFT 0
5759 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
5760 /* EDR Bit Fields */
5761 #define MPU_EDR_ERW_MASK 0x1u
5762 #define MPU_EDR_ERW_SHIFT 0
5763 #define MPU_EDR_EATTR_MASK 0xEu
5764 #define MPU_EDR_EATTR_SHIFT 1
5765 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
5766 #define MPU_EDR_EMN_MASK 0xF0u
5767 #define MPU_EDR_EMN_SHIFT 4
5768 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
5769 #define MPU_EDR_EACD_MASK 0xFFFF0000u
5770 #define MPU_EDR_EACD_SHIFT 16
5771 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
5772 /* WORD Bit Fields */
5773 #define MPU_WORD_M0UM_MASK 0x7u
5774 #define MPU_WORD_M0UM_SHIFT 0
5775 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
5776 #define MPU_WORD_VLD_MASK 0x1u
5777 #define MPU_WORD_VLD_SHIFT 0
5778 #define MPU_WORD_M0SM_MASK 0x18u
5779 #define MPU_WORD_M0SM_SHIFT 3
5780 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
5781 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
5782 #define MPU_WORD_ENDADDR_SHIFT 5
5783 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
5784 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
5785 #define MPU_WORD_SRTADDR_SHIFT 5
5786 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
5787 #define MPU_WORD_M1UM_MASK 0x1C0u
5788 #define MPU_WORD_M1UM_SHIFT 6
5789 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
5790 #define MPU_WORD_M1SM_MASK 0x600u
5791 #define MPU_WORD_M1SM_SHIFT 9
5792 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
5793 #define MPU_WORD_M2UM_MASK 0x7000u
5794 #define MPU_WORD_M2UM_SHIFT 12
5795 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
5796 #define MPU_WORD_M2SM_MASK 0x18000u
5797 #define MPU_WORD_M2SM_SHIFT 15
5798 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
5799 #define MPU_WORD_M3UM_MASK 0x1C0000u
5800 #define MPU_WORD_M3UM_SHIFT 18
5801 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
5802 #define MPU_WORD_M3SM_MASK 0x600000u
5803 #define MPU_WORD_M3SM_SHIFT 21
5804 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
5805 #define MPU_WORD_M4WE_MASK 0x1000000u
5806 #define MPU_WORD_M4WE_SHIFT 24
5807 #define MPU_WORD_M4RE_MASK 0x2000000u
5808 #define MPU_WORD_M4RE_SHIFT 25
5809 #define MPU_WORD_M5WE_MASK 0x4000000u
5810 #define MPU_WORD_M5WE_SHIFT 26
5811 #define MPU_WORD_M5RE_MASK 0x8000000u
5812 #define MPU_WORD_M5RE_SHIFT 27
5813 #define MPU_WORD_M6WE_MASK 0x10000000u
5814 #define MPU_WORD_M6WE_SHIFT 28
5815 #define MPU_WORD_M6RE_MASK 0x20000000u
5816 #define MPU_WORD_M6RE_SHIFT 29
5817 #define MPU_WORD_M7WE_MASK 0x40000000u
5818 #define MPU_WORD_M7WE_SHIFT 30
5819 #define MPU_WORD_M7RE_MASK 0x80000000u
5820 #define MPU_WORD_M7RE_SHIFT 31
5821 /* RGDAAC Bit Fields */
5822 #define MPU_RGDAAC_M0UM_MASK 0x7u
5823 #define MPU_RGDAAC_M0UM_SHIFT 0
5824 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
5825 #define MPU_RGDAAC_M0SM_MASK 0x18u
5826 #define MPU_RGDAAC_M0SM_SHIFT 3
5827 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
5828 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
5829 #define MPU_RGDAAC_M1UM_SHIFT 6
5830 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
5831 #define MPU_RGDAAC_M1SM_MASK 0x600u
5832 #define MPU_RGDAAC_M1SM_SHIFT 9
5833 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
5834 #define MPU_RGDAAC_M2UM_MASK 0x7000u
5835 #define MPU_RGDAAC_M2UM_SHIFT 12
5836 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
5837 #define MPU_RGDAAC_M2SM_MASK 0x18000u
5838 #define MPU_RGDAAC_M2SM_SHIFT 15
5839 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
5840 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
5841 #define MPU_RGDAAC_M3UM_SHIFT 18
5842 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
5843 #define MPU_RGDAAC_M3SM_MASK 0x600000u
5844 #define MPU_RGDAAC_M3SM_SHIFT 21
5845 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
5846 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
5847 #define MPU_RGDAAC_M4WE_SHIFT 24
5848 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
5849 #define MPU_RGDAAC_M4RE_SHIFT 25
5850 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
5851 #define MPU_RGDAAC_M5WE_SHIFT 26
5852 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
5853 #define MPU_RGDAAC_M5RE_SHIFT 27
5854 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
5855 #define MPU_RGDAAC_M6WE_SHIFT 28
5856 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
5857 #define MPU_RGDAAC_M6RE_SHIFT 29
5858 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
5859 #define MPU_RGDAAC_M7WE_SHIFT 30
5860 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
5861 #define MPU_RGDAAC_M7RE_SHIFT 31
5862 
5863 /**
5864  * @}
5865  */ /* end of group MPU_Register_Masks */
5866 
5867 
5868 /* MPU - Peripheral instance base addresses */
5869 /** Peripheral MPU base address */
5870 #define MPU_BASE (0x4000D000u)
5871 /** Peripheral MPU base pointer */
5872 #define MPU ((MPU_Type *)MPU_BASE)
5873 
5874 /**
5875  * @}
5876  */ /* end of group MPU_Peripheral_Access_Layer */
5877 
5878 
5879 /* ----------------------------------------------------------------------------
5880  -- NV Peripheral Access Layer
5881  ---------------------------------------------------------------------------- */
5882 
5883 /**
5884  * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
5885  * @{
5886  */
5887 
5888 /** NV - Register Layout Typedef */
5889 typedef struct {
5890  __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
5891  __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
5892  __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
5893  __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
5894  __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
5895  __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
5896  __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
5897  __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
5898  __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
5899  __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
5900  __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
5901  __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
5902  __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
5903  __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
5904  __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
5905  __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
5906 } NV_Type;
5907 
5908 /* ----------------------------------------------------------------------------
5909  -- NV Register Masks
5910  ---------------------------------------------------------------------------- */
5911 
5912 /**
5913  * @addtogroup NV_Register_Masks NV Register Masks
5914  * @{
5915  */
5916 
5917 /* BACKKEY3 Bit Fields */
5918 #define NV_BACKKEY3_KEY_MASK 0xFFu
5919 #define NV_BACKKEY3_KEY_SHIFT 0
5920 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
5921 /* BACKKEY2 Bit Fields */
5922 #define NV_BACKKEY2_KEY_MASK 0xFFu
5923 #define NV_BACKKEY2_KEY_SHIFT 0
5924 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
5925 /* BACKKEY1 Bit Fields */
5926 #define NV_BACKKEY1_KEY_MASK 0xFFu
5927 #define NV_BACKKEY1_KEY_SHIFT 0
5928 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
5929 /* BACKKEY0 Bit Fields */
5930 #define NV_BACKKEY0_KEY_MASK 0xFFu
5931 #define NV_BACKKEY0_KEY_SHIFT 0
5932 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
5933 /* BACKKEY7 Bit Fields */
5934 #define NV_BACKKEY7_KEY_MASK 0xFFu
5935 #define NV_BACKKEY7_KEY_SHIFT 0
5936 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
5937 /* BACKKEY6 Bit Fields */
5938 #define NV_BACKKEY6_KEY_MASK 0xFFu
5939 #define NV_BACKKEY6_KEY_SHIFT 0
5940 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
5941 /* BACKKEY5 Bit Fields */
5942 #define NV_BACKKEY5_KEY_MASK 0xFFu
5943 #define NV_BACKKEY5_KEY_SHIFT 0
5944 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
5945 /* BACKKEY4 Bit Fields */
5946 #define NV_BACKKEY4_KEY_MASK 0xFFu
5947 #define NV_BACKKEY4_KEY_SHIFT 0
5948 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
5949 /* FPROT3 Bit Fields */
5950 #define NV_FPROT3_PROT_MASK 0xFFu
5951 #define NV_FPROT3_PROT_SHIFT 0
5952 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
5953 /* FPROT2 Bit Fields */
5954 #define NV_FPROT2_PROT_MASK 0xFFu
5955 #define NV_FPROT2_PROT_SHIFT 0
5956 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
5957 /* FPROT1 Bit Fields */
5958 #define NV_FPROT1_PROT_MASK 0xFFu
5959 #define NV_FPROT1_PROT_SHIFT 0
5960 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
5961 /* FPROT0 Bit Fields */
5962 #define NV_FPROT0_PROT_MASK 0xFFu
5963 #define NV_FPROT0_PROT_SHIFT 0
5964 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
5965 /* FSEC Bit Fields */
5966 #define NV_FSEC_SEC_MASK 0x3u
5967 #define NV_FSEC_SEC_SHIFT 0
5968 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
5969 #define NV_FSEC_FSLACC_MASK 0xCu
5970 #define NV_FSEC_FSLACC_SHIFT 2
5971 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
5972 #define NV_FSEC_MEEN_MASK 0x30u
5973 #define NV_FSEC_MEEN_SHIFT 4
5974 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
5975 #define NV_FSEC_KEYEN_MASK 0xC0u
5976 #define NV_FSEC_KEYEN_SHIFT 6
5977 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
5978 /* FOPT Bit Fields */
5979 #define NV_FOPT_LPBOOT_MASK 0x1u
5980 #define NV_FOPT_LPBOOT_SHIFT 0
5981 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
5982 #define NV_FOPT_EZPORT_DIS_SHIFT 1
5983 /* FEPROT Bit Fields */
5984 #define NV_FEPROT_EPROT_MASK 0xFFu
5985 #define NV_FEPROT_EPROT_SHIFT 0
5986 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
5987 /* FDPROT Bit Fields */
5988 #define NV_FDPROT_DPROT_MASK 0xFFu
5989 #define NV_FDPROT_DPROT_SHIFT 0
5990 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
5991 
5992 /**
5993  * @}
5994  */ /* end of group NV_Register_Masks */
5995 
5996 
5997 /* NV - Peripheral instance base addresses */
5998 /** Peripheral FTFL_FlashConfig base address */
5999 #define FTFL_FlashConfig_BASE (0x400u)
6000 /** Peripheral FTFL_FlashConfig base pointer */
6001 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
6002 
6003 /**
6004  * @}
6005  */ /* end of group NV_Peripheral_Access_Layer */
6006 
6007 
6008 /* ----------------------------------------------------------------------------
6009  -- OSC Peripheral Access Layer
6010  ---------------------------------------------------------------------------- */
6011 
6012 /**
6013  * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
6014  * @{
6015  */
6016 
6017 /** OSC - Register Layout Typedef */
6018 typedef struct {
6019  __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
6020 } OSC_Type;
6021 
6022 /* ----------------------------------------------------------------------------
6023  -- OSC Register Masks
6024  ---------------------------------------------------------------------------- */
6025 
6026 /**
6027  * @addtogroup OSC_Register_Masks OSC Register Masks
6028  * @{
6029  */
6030 
6031 /* CR Bit Fields */
6032 #define OSC_CR_SC16P_MASK 0x1u
6033 #define OSC_CR_SC16P_SHIFT 0
6034 #define OSC_CR_SC8P_MASK 0x2u
6035 #define OSC_CR_SC8P_SHIFT 1
6036 #define OSC_CR_SC4P_MASK 0x4u
6037 #define OSC_CR_SC4P_SHIFT 2
6038 #define OSC_CR_SC2P_MASK 0x8u
6039 #define OSC_CR_SC2P_SHIFT 3
6040 #define OSC_CR_EREFSTEN_MASK 0x20u
6041 #define OSC_CR_EREFSTEN_SHIFT 5
6042 #define OSC_CR_ERCLKEN_MASK 0x80u
6043 #define OSC_CR_ERCLKEN_SHIFT 7
6044 
6045 /**
6046  * @}
6047  */ /* end of group OSC_Register_Masks */
6048 
6049 
6050 /* OSC - Peripheral instance base addresses */
6051 /** Peripheral OSC base address */
6052 #define OSC_BASE (0x40065000u)
6053 /** Peripheral OSC base pointer */
6054 #define OSC ((OSC_Type *)OSC_BASE)
6055 
6056 /**
6057  * @}
6058  */ /* end of group OSC_Peripheral_Access_Layer */
6059 
6060 
6061 /* ----------------------------------------------------------------------------
6062  -- PDB Peripheral Access Layer
6063  ---------------------------------------------------------------------------- */
6064 
6065 /**
6066  * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
6067  * @{
6068  */
6069 
6070 /** PDB - Register Layout Typedef */
6071 typedef struct {
6072  __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
6073  __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
6074  __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
6075  __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
6076  struct { /* offset: 0x10, array step: 0x28 */
6077  __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
6078  __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */
6079  __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
6080  uint8_t RESERVED_0[24];
6081  } CH[2];
6082  uint8_t RESERVED_0[240];
6083  struct { /* offset: 0x150, array step: 0x8 */
6084  __IO uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */
6085  __IO uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */
6086  } DAC[2];
6087  uint8_t RESERVED_1[48];
6088  __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
6089  __IO uint32_t PODLY; /**< Pulse-Out n Delay Register, offset: 0x194 */
6090 } PDB_Type;
6091 
6092 /* ----------------------------------------------------------------------------
6093  -- PDB Register Masks
6094  ---------------------------------------------------------------------------- */
6095 
6096 /**
6097  * @addtogroup PDB_Register_Masks PDB Register Masks
6098  * @{
6099  */
6100 
6101 /* SC Bit Fields */
6102 #define PDB_SC_LDOK_MASK 0x1u
6103 #define PDB_SC_LDOK_SHIFT 0
6104 #define PDB_SC_CONT_MASK 0x2u
6105 #define PDB_SC_CONT_SHIFT 1
6106 #define PDB_SC_MULT_MASK 0xCu
6107 #define PDB_SC_MULT_SHIFT 2
6108 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
6109 #define PDB_SC_PDBIE_MASK 0x20u
6110 #define PDB_SC_PDBIE_SHIFT 5
6111 #define PDB_SC_PDBIF_MASK 0x40u
6112 #define PDB_SC_PDBIF_SHIFT 6
6113 #define PDB_SC_PDBEN_MASK 0x80u
6114 #define PDB_SC_PDBEN_SHIFT 7
6115 #define PDB_SC_TRGSEL_MASK 0xF00u
6116 #define PDB_SC_TRGSEL_SHIFT 8
6117 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
6118 #define PDB_SC_PRESCALER_MASK 0x7000u
6119 #define PDB_SC_PRESCALER_SHIFT 12
6120 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
6121 #define PDB_SC_DMAEN_MASK 0x8000u
6122 #define PDB_SC_DMAEN_SHIFT 15
6123 #define PDB_SC_SWTRIG_MASK 0x10000u
6124 #define PDB_SC_SWTRIG_SHIFT 16
6125 #define PDB_SC_PDBEIE_MASK 0x20000u
6126 #define PDB_SC_PDBEIE_SHIFT 17
6127 #define PDB_SC_LDMOD_MASK 0xC0000u
6128 #define PDB_SC_LDMOD_SHIFT 18
6129 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
6130 /* MOD Bit Fields */
6131 #define PDB_MOD_MOD_MASK 0xFFFFu
6132 #define PDB_MOD_MOD_SHIFT 0
6133 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
6134 /* CNT Bit Fields */
6135 #define PDB_CNT_CNT_MASK 0xFFFFu
6136 #define PDB_CNT_CNT_SHIFT 0
6137 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
6138 /* IDLY Bit Fields */
6139 #define PDB_IDLY_IDLY_MASK 0xFFFFu
6140 #define PDB_IDLY_IDLY_SHIFT 0
6141 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
6142 /* C1 Bit Fields */
6143 #define PDB_C1_EN_MASK 0xFFu
6144 #define PDB_C1_EN_SHIFT 0
6145 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
6146 #define PDB_C1_TOS_MASK 0xFF00u
6147 #define PDB_C1_TOS_SHIFT 8
6148 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
6149 #define PDB_C1_BB_MASK 0xFF0000u
6150 #define PDB_C1_BB_SHIFT 16
6151 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
6152 /* S Bit Fields */
6153 #define PDB_S_ERR_MASK 0xFFu
6154 #define PDB_S_ERR_SHIFT 0
6155 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
6156 #define PDB_S_CF_MASK 0xFF0000u
6157 #define PDB_S_CF_SHIFT 16
6158 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
6159 /* DLY Bit Fields */
6160 #define PDB_DLY_DLY_MASK 0xFFFFu
6161 #define PDB_DLY_DLY_SHIFT 0
6162 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
6163 /* INTC Bit Fields */
6164 #define PDB_INTC_TOE_MASK 0x1u
6165 #define PDB_INTC_TOE_SHIFT 0
6166 #define PDB_INTC_EXT_MASK 0x2u
6167 #define PDB_INTC_EXT_SHIFT 1
6168 /* INT Bit Fields */
6169 #define PDB_INT_INT_MASK 0xFFFFu
6170 #define PDB_INT_INT_SHIFT 0
6171 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
6172 /* POEN Bit Fields */
6173 #define PDB_POEN_POEN_MASK 0xFFu
6174 #define PDB_POEN_POEN_SHIFT 0
6175 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
6176 /* PODLY Bit Fields */
6177 #define PDB_PODLY_DLY2_MASK 0xFFFFu
6178 #define PDB_PODLY_DLY2_SHIFT 0
6179 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
6180 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
6181 #define PDB_PODLY_DLY1_SHIFT 16
6182 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
6183 
6184 /**
6185  * @}
6186  */ /* end of group PDB_Register_Masks */
6187 
6188 
6189 /* PDB - Peripheral instance base addresses */
6190 /** Peripheral PDB0 base address */
6191 #define PDB0_BASE (0x40036000u)
6192 /** Peripheral PDB0 base pointer */
6193 #define PDB0 ((PDB_Type *)PDB0_BASE)
6194 
6195 /**
6196  * @}
6197  */ /* end of group PDB_Peripheral_Access_Layer */
6198 
6199 
6200 /* ----------------------------------------------------------------------------
6201  -- PIT Peripheral Access Layer
6202  ---------------------------------------------------------------------------- */
6203 
6204 /**
6205  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
6206  * @{
6207  */
6208 
6209 /** PIT - Register Layout Typedef */
6210 typedef struct {
6211  __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
6212  uint8_t RESERVED_0[252];
6213  struct { /* offset: 0x100, array step: 0x10 */
6214  __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
6215  __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
6216  __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
6217  __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
6218  } CHANNEL[4];
6219 } PIT_Type;
6220 
6221 /* ----------------------------------------------------------------------------
6222  -- PIT Register Masks
6223  ---------------------------------------------------------------------------- */
6224 
6225 /**
6226  * @addtogroup PIT_Register_Masks PIT Register Masks
6227  * @{
6228  */
6229 
6230 /* MCR Bit Fields */
6231 #define PIT_MCR_FRZ_MASK 0x1u
6232 #define PIT_MCR_FRZ_SHIFT 0
6233 #define PIT_MCR_MDIS_MASK 0x2u
6234 #define PIT_MCR_MDIS_SHIFT 1
6235 /* LDVAL Bit Fields */
6236 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
6237 #define PIT_LDVAL_TSV_SHIFT 0
6238 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
6239 /* CVAL Bit Fields */
6240 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
6241 #define PIT_CVAL_TVL_SHIFT 0
6242 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
6243 /* TCTRL Bit Fields */
6244 #define PIT_TCTRL_TEN_MASK 0x1u
6245 #define PIT_TCTRL_TEN_SHIFT 0
6246 #define PIT_TCTRL_TIE_MASK 0x2u
6247 #define PIT_TCTRL_TIE_SHIFT 1
6248 /* TFLG Bit Fields */
6249 #define PIT_TFLG_TIF_MASK 0x1u
6250 #define PIT_TFLG_TIF_SHIFT 0
6251 
6252 /**
6253  * @}
6254  */ /* end of group PIT_Register_Masks */
6255 
6256 
6257 /* PIT - Peripheral instance base addresses */
6258 /** Peripheral PIT base address */
6259 #define PIT_BASE (0x40037000u)
6260 /** Peripheral PIT base pointer */
6261 #define PIT ((PIT_Type *)PIT_BASE)
6262 
6263 /**
6264  * @}
6265  */ /* end of group PIT_Peripheral_Access_Layer */
6266 
6267 
6268 /* ----------------------------------------------------------------------------
6269  -- PMC Peripheral Access Layer
6270  ---------------------------------------------------------------------------- */
6271 
6272 /**
6273  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
6274  * @{
6275  */
6276 
6277 /** PMC - Register Layout Typedef */
6278 typedef struct {
6279  __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
6280  __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
6281  __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
6282 } PMC_Type;
6283 
6284 /* ----------------------------------------------------------------------------
6285  -- PMC Register Masks
6286  ---------------------------------------------------------------------------- */
6287 
6288 /**
6289  * @addtogroup PMC_Register_Masks PMC Register Masks
6290  * @{
6291  */
6292 
6293 /* LVDSC1 Bit Fields */
6294 #define PMC_LVDSC1_LVDV_MASK 0x3u
6295 #define PMC_LVDSC1_LVDV_SHIFT 0
6296 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
6297 #define PMC_LVDSC1_LVDRE_MASK 0x10u
6298 #define PMC_LVDSC1_LVDRE_SHIFT 4
6299 #define PMC_LVDSC1_LVDIE_MASK 0x20u
6300 #define PMC_LVDSC1_LVDIE_SHIFT 5
6301 #define PMC_LVDSC1_LVDACK_MASK 0x40u
6302 #define PMC_LVDSC1_LVDACK_SHIFT 6
6303 #define PMC_LVDSC1_LVDF_MASK 0x80u
6304 #define PMC_LVDSC1_LVDF_SHIFT 7
6305 /* LVDSC2 Bit Fields */
6306 #define PMC_LVDSC2_LVWV_MASK 0x3u
6307 #define PMC_LVDSC2_LVWV_SHIFT 0
6308 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
6309 #define PMC_LVDSC2_LVWIE_MASK 0x20u
6310 #define PMC_LVDSC2_LVWIE_SHIFT 5
6311 #define PMC_LVDSC2_LVWACK_MASK 0x40u
6312 #define PMC_LVDSC2_LVWACK_SHIFT 6
6313 #define PMC_LVDSC2_LVWF_MASK 0x80u
6314 #define PMC_LVDSC2_LVWF_SHIFT 7
6315 /* REGSC Bit Fields */
6316 #define PMC_REGSC_BGBE_MASK 0x1u
6317 #define PMC_REGSC_BGBE_SHIFT 0
6318 #define PMC_REGSC_REGONS_MASK 0x4u
6319 #define PMC_REGSC_REGONS_SHIFT 2
6320 #define PMC_REGSC_VLPRS_MASK 0x8u
6321 #define PMC_REGSC_VLPRS_SHIFT 3
6322 #define PMC_REGSC_TRAMPO_MASK 0x10u
6323 #define PMC_REGSC_TRAMPO_SHIFT 4
6324 
6325 /**
6326  * @}
6327  */ /* end of group PMC_Register_Masks */
6328 
6329 
6330 /* PMC - Peripheral instance base addresses */
6331 /** Peripheral PMC base address */
6332 #define PMC_BASE (0x4007D000u)
6333 /** Peripheral PMC base pointer */
6334 #define PMC ((PMC_Type *)PMC_BASE)
6335 
6336 /**
6337  * @}
6338  */ /* end of group PMC_Peripheral_Access_Layer */
6339 
6340 
6341 /* ----------------------------------------------------------------------------
6342  -- PORT Peripheral Access Layer
6343  ---------------------------------------------------------------------------- */
6344 
6345 /**
6346  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
6347  * @{
6348  */
6349 
6350 /** PORT - Register Layout Typedef */
6351 typedef struct {
6352  __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
6353  __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
6354  __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
6355  uint8_t RESERVED_0[24];
6356  __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
6357  uint8_t RESERVED_1[28];
6358  __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
6359  __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
6360  __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
6361 } PORT_Type;
6362 
6363 /* ----------------------------------------------------------------------------
6364  -- PORT Register Masks
6365  ---------------------------------------------------------------------------- */
6366 
6367 /**
6368  * @addtogroup PORT_Register_Masks PORT Register Masks
6369  * @{
6370  */
6371 
6372 /* PCR Bit Fields */
6373 #define PORT_PCR_PS_MASK 0x1u
6374 #define PORT_PCR_PS_SHIFT 0
6375 #define PORT_PCR_PE_MASK 0x2u
6376 #define PORT_PCR_PE_SHIFT 1
6377 #define PORT_PCR_SRE_MASK 0x4u
6378 #define PORT_PCR_SRE_SHIFT 2
6379 #define PORT_PCR_PFE_MASK 0x10u
6380 #define PORT_PCR_PFE_SHIFT 4
6381 #define PORT_PCR_ODE_MASK 0x20u
6382 #define PORT_PCR_ODE_SHIFT 5
6383 #define PORT_PCR_DSE_MASK 0x40u
6384 #define PORT_PCR_DSE_SHIFT 6
6385 #define PORT_PCR_MUX_MASK 0x700u
6386 #define PORT_PCR_MUX_SHIFT 8
6387 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
6388 #define PORT_PCR_LK_MASK 0x8000u
6389 #define PORT_PCR_LK_SHIFT 15
6390 #define PORT_PCR_IRQC_MASK 0xF0000u
6391 #define PORT_PCR_IRQC_SHIFT 16
6392 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
6393 #define PORT_PCR_ISF_MASK 0x1000000u
6394 #define PORT_PCR_ISF_SHIFT 24
6395 /* GPCLR Bit Fields */
6396 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
6397 #define PORT_GPCLR_GPWD_SHIFT 0
6398 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
6399 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
6400 #define PORT_GPCLR_GPWE_SHIFT 16
6401 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
6402 /* GPCHR Bit Fields */
6403 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
6404 #define PORT_GPCHR_GPWD_SHIFT 0
6405 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
6406 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
6407 #define PORT_GPCHR_GPWE_SHIFT 16
6408 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
6409 /* ISFR Bit Fields */
6410 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
6411 #define PORT_ISFR_ISF_SHIFT 0
6412 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
6413 /* DFER Bit Fields */
6414 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
6415 #define PORT_DFER_DFE_SHIFT 0
6416 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
6417 /* DFCR Bit Fields */
6418 #define PORT_DFCR_CS_MASK 0x1u
6419 #define PORT_DFCR_CS_SHIFT 0
6420 /* DFWR Bit Fields */
6421 #define PORT_DFWR_FILT_MASK 0x1Fu
6422 #define PORT_DFWR_FILT_SHIFT 0
6423 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
6424 
6425 /**
6426  * @}
6427  */ /* end of group PORT_Register_Masks */
6428 
6429 
6430 /* PORT - Peripheral instance base addresses */
6431 /** Peripheral PORTA base address */
6432 #define PORTA_BASE (0x40049000u)
6433 /** Peripheral PORTA base pointer */
6434 #define PORTA ((PORT_Type *)PORTA_BASE)
6435 /** Peripheral PORTB base address */
6436 #define PORTB_BASE (0x4004A000u)
6437 /** Peripheral PORTB base pointer */
6438 #define PORTB ((PORT_Type *)PORTB_BASE)
6439 /** Peripheral PORTC base address */
6440 #define PORTC_BASE (0x4004B000u)
6441 /** Peripheral PORTC base pointer */
6442 #define PORTC ((PORT_Type *)PORTC_BASE)
6443 /** Peripheral PORTD base address */
6444 #define PORTD_BASE (0x4004C000u)
6445 /** Peripheral PORTD base pointer */
6446 #define PORTD ((PORT_Type *)PORTD_BASE)
6447 /** Peripheral PORTE base address */
6448 #define PORTE_BASE (0x4004D000u)
6449 /** Peripheral PORTE base pointer */
6450 #define PORTE ((PORT_Type *)PORTE_BASE)
6451 
6452 /**
6453  * @}
6454  */ /* end of group PORT_Peripheral_Access_Layer */
6455 
6456 
6457 /* ----------------------------------------------------------------------------
6458  -- RFSYS Peripheral Access Layer
6459  ---------------------------------------------------------------------------- */
6460 
6461 /**
6462  * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
6463  * @{
6464  */
6465 
6466 /** RFSYS - Register Layout Typedef */
6467 typedef struct {
6468  __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
6469 } RFSYS_Type;
6470 
6471 /* ----------------------------------------------------------------------------
6472  -- RFSYS Register Masks
6473  ---------------------------------------------------------------------------- */
6474 
6475 /**
6476  * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
6477  * @{
6478  */
6479 
6480 /* REG Bit Fields */
6481 #define RFSYS_REG_LL_MASK 0xFFu
6482 #define RFSYS_REG_LL_SHIFT 0
6483 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
6484 #define RFSYS_REG_LH_MASK 0xFF00u
6485 #define RFSYS_REG_LH_SHIFT 8
6486 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
6487 #define RFSYS_REG_HL_MASK 0xFF0000u
6488 #define RFSYS_REG_HL_SHIFT 16
6489 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
6490 #define RFSYS_REG_HH_MASK 0xFF000000u
6491 #define RFSYS_REG_HH_SHIFT 24
6492 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
6493 
6494 /**
6495  * @}
6496  */ /* end of group RFSYS_Register_Masks */
6497 
6498 
6499 /* RFSYS - Peripheral instance base addresses */
6500 /** Peripheral RFSYS base address */
6501 #define RFSYS_BASE (0x40041000u)
6502 /** Peripheral RFSYS base pointer */
6503 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
6504 
6505 /**
6506  * @}
6507  */ /* end of group RFSYS_Peripheral_Access_Layer */
6508 
6509 
6510 /* ----------------------------------------------------------------------------
6511  -- RFVBAT Peripheral Access Layer
6512  ---------------------------------------------------------------------------- */
6513 
6514 /**
6515  * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
6516  * @{
6517  */
6518 
6519 /** RFVBAT - Register Layout Typedef */
6520 typedef struct {
6521  __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
6522 } RFVBAT_Type;
6523 
6524 /* ----------------------------------------------------------------------------
6525  -- RFVBAT Register Masks
6526  ---------------------------------------------------------------------------- */
6527 
6528 /**
6529  * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
6530  * @{
6531  */
6532 
6533 /* REG Bit Fields */
6534 #define RFVBAT_REG_LL_MASK 0xFFu
6535 #define RFVBAT_REG_LL_SHIFT 0
6536 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
6537 #define RFVBAT_REG_LH_MASK 0xFF00u
6538 #define RFVBAT_REG_LH_SHIFT 8
6539 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
6540 #define RFVBAT_REG_HL_MASK 0xFF0000u
6541 #define RFVBAT_REG_HL_SHIFT 16
6542 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
6543 #define RFVBAT_REG_HH_MASK 0xFF000000u
6544 #define RFVBAT_REG_HH_SHIFT 24
6545 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
6546 
6547 /**
6548  * @}
6549  */ /* end of group RFVBAT_Register_Masks */
6550 
6551 
6552 /* RFVBAT - Peripheral instance base addresses */
6553 /** Peripheral RFVBAT base address */
6554 #define RFVBAT_BASE (0x4003E000u)
6555 /** Peripheral RFVBAT base pointer */
6556 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
6557 
6558 /**
6559  * @}
6560  */ /* end of group RFVBAT_Peripheral_Access_Layer */
6561 
6562 
6563 /* ----------------------------------------------------------------------------
6564  -- RNG Peripheral Access Layer
6565  ---------------------------------------------------------------------------- */
6566 
6567 /**
6568  * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
6569  * @{
6570  */
6571 
6572 /** RNG - Register Layout Typedef */
6573 typedef struct {
6574  __I uint32_t VER; /**< RNGB Version ID Register, offset: 0x0 */
6575  __IO uint32_t CMD; /**< RNGB Command Register, offset: 0x4 */
6576  __IO uint32_t CR; /**< RNGB Control Register, offset: 0x8 */
6577  __I uint32_t SR; /**< RNGB Status Register, offset: 0xC */
6578  __I uint32_t ESR; /**< RNGB Error Status Register, offset: 0x10 */
6579  __I uint32_t OUT; /**< RNGB Output FIFO, offset: 0x14 */
6580 } RNG_Type;
6581 
6582 /* ----------------------------------------------------------------------------
6583  -- RNG Register Masks
6584  ---------------------------------------------------------------------------- */
6585 
6586 /**
6587  * @addtogroup RNG_Register_Masks RNG Register Masks
6588  * @{
6589  */
6590 
6591 /* VER Bit Fields */
6592 #define RNG_VER_MINOR_MASK 0xFFu
6593 #define RNG_VER_MINOR_SHIFT 0
6594 #define RNG_VER_MINOR(x) (((uint32_t)(((uint32_t)(x))<<RNG_VER_MINOR_SHIFT))&RNG_VER_MINOR_MASK)
6595 #define RNG_VER_MAJOR_MASK 0xFF00u
6596 #define RNG_VER_MAJOR_SHIFT 8
6597 #define RNG_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<RNG_VER_MAJOR_SHIFT))&RNG_VER_MAJOR_MASK)
6598 #define RNG_VER_TYPE_MASK 0xF0000000u
6599 #define RNG_VER_TYPE_SHIFT 28
6600 #define RNG_VER_TYPE(x) (((uint32_t)(((uint32_t)(x))<<RNG_VER_TYPE_SHIFT))&RNG_VER_TYPE_MASK)
6601 /* CMD Bit Fields */
6602 #define RNG_CMD_ST_MASK 0x1u
6603 #define RNG_CMD_ST_SHIFT 0
6604 #define RNG_CMD_GS_MASK 0x2u
6605 #define RNG_CMD_GS_SHIFT 1
6606 #define RNG_CMD_CI_MASK 0x10u
6607 #define RNG_CMD_CI_SHIFT 4
6608 #define RNG_CMD_CE_MASK 0x20u
6609 #define RNG_CMD_CE_SHIFT 5
6610 #define RNG_CMD_SR_MASK 0x40u
6611 #define RNG_CMD_SR_SHIFT 6
6612 /* CR Bit Fields */
6613 #define RNG_CR_FUFMOD_MASK 0x3u
6614 #define RNG_CR_FUFMOD_SHIFT 0
6615 #define RNG_CR_FUFMOD(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_FUFMOD_SHIFT))&RNG_CR_FUFMOD_MASK)
6616 #define RNG_CR_AR_MASK 0x10u
6617 #define RNG_CR_AR_SHIFT 4
6618 #define RNG_CR_MASKDONE_MASK 0x20u
6619 #define RNG_CR_MASKDONE_SHIFT 5
6620 #define RNG_CR_MASKERR_MASK 0x40u
6621 #define RNG_CR_MASKERR_SHIFT 6
6622 /* SR Bit Fields */
6623 #define RNG_SR_BUSY_MASK 0x2u
6624 #define RNG_SR_BUSY_SHIFT 1
6625 #define RNG_SR_SLP_MASK 0x4u
6626 #define RNG_SR_SLP_SHIFT 2
6627 #define RNG_SR_RS_MASK 0x8u
6628 #define RNG_SR_RS_SHIFT 3
6629 #define RNG_SR_STDN_MASK 0x10u
6630 #define RNG_SR_STDN_SHIFT 4
6631 #define RNG_SR_SDN_MASK 0x20u
6632 #define RNG_SR_SDN_SHIFT 5
6633 #define RNG_SR_NSDN_MASK 0x40u
6634 #define RNG_SR_NSDN_SHIFT 6
6635 #define RNG_SR_FIFO_LVL_MASK 0xF00u
6636 #define RNG_SR_FIFO_LVL_SHIFT 8
6637 #define RNG_SR_FIFO_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_FIFO_LVL_SHIFT))&RNG_SR_FIFO_LVL_MASK)
6638 #define RNG_SR_FIFO_SIZE_MASK 0xF000u
6639 #define RNG_SR_FIFO_SIZE_SHIFT 12
6640 #define RNG_SR_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_FIFO_SIZE_SHIFT))&RNG_SR_FIFO_SIZE_MASK)
6641 #define RNG_SR_ERR_MASK 0x10000u
6642 #define RNG_SR_ERR_SHIFT 16
6643 #define RNG_SR_ST_PF_MASK 0xE00000u
6644 #define RNG_SR_ST_PF_SHIFT 21
6645 #define RNG_SR_ST_PF(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_ST_PF_SHIFT))&RNG_SR_ST_PF_MASK)
6646 #define RNG_SR_STATPF_MASK 0xFF000000u
6647 #define RNG_SR_STATPF_SHIFT 24
6648 #define RNG_SR_STATPF(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_STATPF_SHIFT))&RNG_SR_STATPF_MASK)
6649 /* ESR Bit Fields */
6650 #define RNG_ESR_LFE_MASK 0x1u
6651 #define RNG_ESR_LFE_SHIFT 0
6652 #define RNG_ESR_OSCE_MASK 0x2u
6653 #define RNG_ESR_OSCE_SHIFT 1
6654 #define RNG_ESR_STE_MASK 0x4u
6655 #define RNG_ESR_STE_SHIFT 2
6656 #define RNG_ESR_SATE_MASK 0x8u
6657 #define RNG_ESR_SATE_SHIFT 3
6658 #define RNG_ESR_FUFE_MASK 0x10u
6659 #define RNG_ESR_FUFE_SHIFT 4
6660 /* OUT Bit Fields */
6661 #define RNG_OUT_RANDOUT_MASK 0xFFFFFFFFu
6662 #define RNG_OUT_RANDOUT_SHIFT 0
6663 #define RNG_OUT_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OUT_RANDOUT_SHIFT))&RNG_OUT_RANDOUT_MASK)
6664 
6665 /**
6666  * @}
6667  */ /* end of group RNG_Register_Masks */
6668 
6669 
6670 /* RNG - Peripheral instance base addresses */
6671 /** Peripheral RNG base address */
6672 #define RNG_BASE (0x400A0000u)
6673 /** Peripheral RNG base pointer */
6674 #define RNG ((RNG_Type *)RNG_BASE)
6675 
6676 /**
6677  * @}
6678  */ /* end of group RNG_Peripheral_Access_Layer */
6679 
6680 
6681 /* ----------------------------------------------------------------------------
6682  -- RTC Peripheral Access Layer
6683  ---------------------------------------------------------------------------- */
6684 
6685 /**
6686  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
6687  * @{
6688  */
6689 
6690 /** RTC - Register Layout Typedef */
6691 typedef struct {
6692  __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
6693  __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
6694  __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
6695  __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
6696  __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
6697  __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
6698  __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
6699  __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
6700  uint8_t RESERVED_0[2016];
6701  __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
6702  __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
6703 } RTC_Type;
6704 
6705 /* ----------------------------------------------------------------------------
6706  -- RTC Register Masks
6707  ---------------------------------------------------------------------------- */
6708 
6709 /**
6710  * @addtogroup RTC_Register_Masks RTC Register Masks
6711  * @{
6712  */
6713 
6714 /* TSR Bit Fields */
6715 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
6716 #define RTC_TSR_TSR_SHIFT 0
6717 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
6718 /* TPR Bit Fields */
6719 #define RTC_TPR_TPR_MASK 0xFFFFu
6720 #define RTC_TPR_TPR_SHIFT 0
6721 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
6722 /* TAR Bit Fields */
6723 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
6724 #define RTC_TAR_TAR_SHIFT 0
6725 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
6726 /* TCR Bit Fields */
6727 #define RTC_TCR_TCR_MASK 0xFFu
6728 #define RTC_TCR_TCR_SHIFT 0
6729 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
6730 #define RTC_TCR_CIR_MASK 0xFF00u
6731 #define RTC_TCR_CIR_SHIFT 8
6732 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
6733 #define RTC_TCR_TCV_MASK 0xFF0000u
6734 #define RTC_TCR_TCV_SHIFT 16
6735 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
6736 #define RTC_TCR_CIC_MASK 0xFF000000u
6737 #define RTC_TCR_CIC_SHIFT 24
6738 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
6739 /* CR Bit Fields */
6740 #define RTC_CR_SWR_MASK 0x1u
6741 #define RTC_CR_SWR_SHIFT 0
6742 #define RTC_CR_WPE_MASK 0x2u
6743 #define RTC_CR_WPE_SHIFT 1
6744 #define RTC_CR_SUP_MASK 0x4u
6745 #define RTC_CR_SUP_SHIFT 2
6746 #define RTC_CR_UM_MASK 0x8u
6747 #define RTC_CR_UM_SHIFT 3
6748 #define RTC_CR_OSCE_MASK 0x100u
6749 #define RTC_CR_OSCE_SHIFT 8
6750 #define RTC_CR_CLKO_MASK 0x200u
6751 #define RTC_CR_CLKO_SHIFT 9
6752 #define RTC_CR_SC16P_MASK 0x400u
6753 #define RTC_CR_SC16P_SHIFT 10
6754 #define RTC_CR_SC8P_MASK 0x800u
6755 #define RTC_CR_SC8P_SHIFT 11
6756 #define RTC_CR_SC4P_MASK 0x1000u
6757 #define RTC_CR_SC4P_SHIFT 12
6758 #define RTC_CR_SC2P_MASK 0x2000u
6759 #define RTC_CR_SC2P_SHIFT 13
6760 /* SR Bit Fields */
6761 #define RTC_SR_TIF_MASK 0x1u
6762 #define RTC_SR_TIF_SHIFT 0
6763 #define RTC_SR_TOF_MASK 0x2u
6764 #define RTC_SR_TOF_SHIFT 1
6765 #define RTC_SR_TAF_MASK 0x4u
6766 #define RTC_SR_TAF_SHIFT 2
6767 #define RTC_SR_TCE_MASK 0x10u
6768 #define RTC_SR_TCE_SHIFT 4
6769 /* LR Bit Fields */
6770 #define RTC_LR_TCL_MASK 0x8u
6771 #define RTC_LR_TCL_SHIFT 3
6772 #define RTC_LR_CRL_MASK 0x10u
6773 #define RTC_LR_CRL_SHIFT 4
6774 #define RTC_LR_SRL_MASK 0x20u
6775 #define RTC_LR_SRL_SHIFT 5
6776 #define RTC_LR_LRL_MASK 0x40u
6777 #define RTC_LR_LRL_SHIFT 6
6778 /* IER Bit Fields */
6779 #define RTC_IER_TIIE_MASK 0x1u
6780 #define RTC_IER_TIIE_SHIFT 0
6781 #define RTC_IER_TOIE_MASK 0x2u
6782 #define RTC_IER_TOIE_SHIFT 1
6783 #define RTC_IER_TAIE_MASK 0x4u
6784 #define RTC_IER_TAIE_SHIFT 2
6785 /* WAR Bit Fields */
6786 #define RTC_WAR_TSRW_MASK 0x1u
6787 #define RTC_WAR_TSRW_SHIFT 0
6788 #define RTC_WAR_TPRW_MASK 0x2u
6789 #define RTC_WAR_TPRW_SHIFT 1
6790 #define RTC_WAR_TARW_MASK 0x4u
6791 #define RTC_WAR_TARW_SHIFT 2
6792 #define RTC_WAR_TCRW_MASK 0x8u
6793 #define RTC_WAR_TCRW_SHIFT 3
6794 #define RTC_WAR_CRW_MASK 0x10u
6795 #define RTC_WAR_CRW_SHIFT 4
6796 #define RTC_WAR_SRW_MASK 0x20u
6797 #define RTC_WAR_SRW_SHIFT 5
6798 #define RTC_WAR_LRW_MASK 0x40u
6799 #define RTC_WAR_LRW_SHIFT 6
6800 #define RTC_WAR_IERW_MASK 0x80u
6801 #define RTC_WAR_IERW_SHIFT 7
6802 /* RAR Bit Fields */
6803 #define RTC_RAR_TSRR_MASK 0x1u
6804 #define RTC_RAR_TSRR_SHIFT 0
6805 #define RTC_RAR_TPRR_MASK 0x2u
6806 #define RTC_RAR_TPRR_SHIFT 1
6807 #define RTC_RAR_TARR_MASK 0x4u
6808 #define RTC_RAR_TARR_SHIFT 2
6809 #define RTC_RAR_TCRR_MASK 0x8u
6810 #define RTC_RAR_TCRR_SHIFT 3
6811 #define RTC_RAR_CRR_MASK 0x10u
6812 #define RTC_RAR_CRR_SHIFT 4
6813 #define RTC_RAR_SRR_MASK 0x20u
6814 #define RTC_RAR_SRR_SHIFT 5
6815 #define RTC_RAR_LRR_MASK 0x40u
6816 #define RTC_RAR_LRR_SHIFT 6
6817 #define RTC_RAR_IERR_MASK 0x80u
6818 #define RTC_RAR_IERR_SHIFT 7
6819 
6820 /**
6821  * @}
6822  */ /* end of group RTC_Register_Masks */
6823 
6824 
6825 /* RTC - Peripheral instance base addresses */
6826 /** Peripheral RTC base address */
6827 #define RTC_BASE (0x4003D000u)
6828 /** Peripheral RTC base pointer */
6829 #define RTC ((RTC_Type *)RTC_BASE)
6830 
6831 /**
6832  * @}
6833  */ /* end of group RTC_Peripheral_Access_Layer */
6834 
6835 
6836 /* ----------------------------------------------------------------------------
6837  -- SDHC Peripheral Access Layer
6838  ---------------------------------------------------------------------------- */
6839 
6840 /**
6841  * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
6842  * @{
6843  */
6844 
6845 /** SDHC - Register Layout Typedef */
6846 typedef struct {
6847  __IO uint32_t DSADDR; /**< DMA System Address Register, offset: 0x0 */
6848  __IO uint32_t BLKATTR; /**< Block Attributes Register, offset: 0x4 */
6849  __IO uint32_t CMDARG; /**< Command Argument Register, offset: 0x8 */
6850  __IO uint32_t XFERTYP; /**< Transfer Type Register, offset: 0xC */
6851  __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
6852  __IO uint32_t DATPORT; /**< Buffer Data Port Register, offset: 0x20 */
6853  __I uint32_t PRSSTAT; /**< Present State Register, offset: 0x24 */
6854  __IO uint32_t PROCTL; /**< Protocol Control Register, offset: 0x28 */
6855  __IO uint32_t SYSCTL; /**< System Control Register, offset: 0x2C */
6856  __IO uint32_t IRQSTAT; /**< Interrupt Status Register, offset: 0x30 */
6857  __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable Register, offset: 0x34 */
6858  __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable Register, offset: 0x38 */
6859  __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
6860  __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
6861  __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
6862  uint8_t RESERVED_0[8];
6863  __O uint32_t FEVT; /**< Force Event Register, offset: 0x50 */
6864  __I uint32_t ADMAES; /**< ADMA Error Status Register, offset: 0x54 */
6865  __IO uint32_t ADSADDR; /**< ADMA System Address Register, offset: 0x58 */
6866  uint8_t RESERVED_1[100];
6867  __IO uint32_t VENDOR; /**< Vendor Specific Register, offset: 0xC0 */
6868  __IO uint32_t MMCBOOT; /**< MMC Boot Register, offset: 0xC4 */
6869  uint8_t RESERVED_2[52];
6870  __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
6871 } SDHC_Type;
6872 
6873 /* ----------------------------------------------------------------------------
6874  -- SDHC Register Masks
6875  ---------------------------------------------------------------------------- */
6876 
6877 /**
6878  * @addtogroup SDHC_Register_Masks SDHC Register Masks
6879  * @{
6880  */
6881 
6882 /* DSADDR Bit Fields */
6883 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
6884 #define SDHC_DSADDR_DSADDR_SHIFT 2
6885 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
6886 /* BLKATTR Bit Fields */
6887 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
6888 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
6889 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
6890 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
6891 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
6892 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
6893 /* CMDARG Bit Fields */
6894 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
6895 #define SDHC_CMDARG_CMDARG_SHIFT 0
6896 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
6897 /* XFERTYP Bit Fields */
6898 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
6899 #define SDHC_XFERTYP_DMAEN_SHIFT 0
6900 #define SDHC_XFERTYP_BCEN_MASK 0x2u
6901 #define SDHC_XFERTYP_BCEN_SHIFT 1
6902 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
6903 #define SDHC_XFERTYP_AC12EN_SHIFT 2
6904 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
6905 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
6906 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
6907 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
6908 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
6909 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
6910 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
6911 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
6912 #define SDHC_XFERTYP_CCCEN_SHIFT 19
6913 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
6914 #define SDHC_XFERTYP_CICEN_SHIFT 20
6915 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
6916 #define SDHC_XFERTYP_DPSEL_SHIFT 21
6917 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
6918 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
6919 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
6920 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
6921 #define SDHC_XFERTYP_CMDINX_SHIFT 24
6922 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
6923 /* CMDRSP Bit Fields */
6924 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
6925 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
6926 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
6927 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
6928 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
6929 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
6930 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
6931 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
6932 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
6933 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
6934 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
6935 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
6936 /* DATPORT Bit Fields */
6937 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
6938 #define SDHC_DATPORT_DATCONT_SHIFT 0
6939 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
6940 /* PRSSTAT Bit Fields */
6941 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
6942 #define SDHC_PRSSTAT_CIHB_SHIFT 0
6943 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
6944 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
6945 #define SDHC_PRSSTAT_DLA_MASK 0x4u
6946 #define SDHC_PRSSTAT_DLA_SHIFT 2
6947 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
6948 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
6949 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
6950 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
6951 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
6952 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
6953 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
6954 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
6955 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
6956 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
6957 #define SDHC_PRSSTAT_WTA_MASK 0x100u
6958 #define SDHC_PRSSTAT_WTA_SHIFT 8
6959 #define SDHC_PRSSTAT_RTA_MASK 0x200u
6960 #define SDHC_PRSSTAT_RTA_SHIFT 9
6961 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
6962 #define SDHC_PRSSTAT_BWEN_SHIFT 10
6963 #define SDHC_PRSSTAT_BREN_MASK 0x800u
6964 #define SDHC_PRSSTAT_BREN_SHIFT 11
6965 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
6966 #define SDHC_PRSSTAT_CINS_SHIFT 16
6967 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
6968 #define SDHC_PRSSTAT_CLSL_SHIFT 23
6969 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
6970 #define SDHC_PRSSTAT_DLSL_SHIFT 24
6971 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
6972 /* PROCTL Bit Fields */
6973 #define SDHC_PROCTL_LCTL_MASK 0x1u
6974 #define SDHC_PROCTL_LCTL_SHIFT 0
6975 #define SDHC_PROCTL_DTW_MASK 0x6u
6976 #define SDHC_PROCTL_DTW_SHIFT 1
6977 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
6978 #define SDHC_PROCTL_D3CD_MASK 0x8u
6979 #define SDHC_PROCTL_D3CD_SHIFT 3
6980 #define SDHC_PROCTL_EMODE_MASK 0x30u
6981 #define SDHC_PROCTL_EMODE_SHIFT 4
6982 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
6983 #define SDHC_PROCTL_CDTL_MASK 0x40u
6984 #define SDHC_PROCTL_CDTL_SHIFT 6
6985 #define SDHC_PROCTL_CDSS_MASK 0x80u
6986 #define SDHC_PROCTL_CDSS_SHIFT 7
6987 #define SDHC_PROCTL_DMAS_MASK 0x300u
6988 #define SDHC_PROCTL_DMAS_SHIFT 8
6989 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
6990 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
6991 #define SDHC_PROCTL_SABGREQ_SHIFT 16
6992 #define SDHC_PROCTL_CREQ_MASK 0x20000u
6993 #define SDHC_PROCTL_CREQ_SHIFT 17
6994 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
6995 #define SDHC_PROCTL_RWCTL_SHIFT 18
6996 #define SDHC_PROCTL_IABG_MASK 0x80000u
6997 #define SDHC_PROCTL_IABG_SHIFT 19
6998 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
6999 #define SDHC_PROCTL_WECINT_SHIFT 24
7000 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
7001 #define SDHC_PROCTL_WECINS_SHIFT 25
7002 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
7003 #define SDHC_PROCTL_WECRM_SHIFT 26
7004 /* SYSCTL Bit Fields */
7005 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
7006 #define SDHC_SYSCTL_IPGEN_SHIFT 0
7007 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
7008 #define SDHC_SYSCTL_HCKEN_SHIFT 1
7009 #define SDHC_SYSCTL_PEREN_MASK 0x4u
7010 #define SDHC_SYSCTL_PEREN_SHIFT 2
7011 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
7012 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
7013 #define SDHC_SYSCTL_DVS_MASK 0xF0u
7014 #define SDHC_SYSCTL_DVS_SHIFT 4
7015 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
7016 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
7017 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
7018 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
7019 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
7020 #define SDHC_SYSCTL_DTOCV_SHIFT 16
7021 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
7022 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
7023 #define SDHC_SYSCTL_RSTA_SHIFT 24
7024 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
7025 #define SDHC_SYSCTL_RSTC_SHIFT 25
7026 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
7027 #define SDHC_SYSCTL_RSTD_SHIFT 26
7028 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
7029 #define SDHC_SYSCTL_INITA_SHIFT 27
7030 /* IRQSTAT Bit Fields */
7031 #define SDHC_IRQSTAT_CC_MASK 0x1u
7032 #define SDHC_IRQSTAT_CC_SHIFT 0
7033 #define SDHC_IRQSTAT_TC_MASK 0x2u
7034 #define SDHC_IRQSTAT_TC_SHIFT 1
7035 #define SDHC_IRQSTAT_BGE_MASK 0x4u
7036 #define SDHC_IRQSTAT_BGE_SHIFT 2
7037 #define SDHC_IRQSTAT_DINT_MASK 0x8u
7038 #define SDHC_IRQSTAT_DINT_SHIFT 3
7039 #define SDHC_IRQSTAT_BWR_MASK 0x10u
7040 #define SDHC_IRQSTAT_BWR_SHIFT 4
7041 #define SDHC_IRQSTAT_BRR_MASK 0x20u
7042 #define SDHC_IRQSTAT_BRR_SHIFT 5
7043 #define SDHC_IRQSTAT_CINS_MASK 0x40u
7044 #define SDHC_IRQSTAT_CINS_SHIFT 6
7045 #define SDHC_IRQSTAT_CRM_MASK 0x80u
7046 #define SDHC_IRQSTAT_CRM_SHIFT 7
7047 #define SDHC_IRQSTAT_CINT_MASK 0x100u
7048 #define SDHC_IRQSTAT_CINT_SHIFT 8
7049 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
7050 #define SDHC_IRQSTAT_CTOE_SHIFT 16
7051 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
7052 #define SDHC_IRQSTAT_CCE_SHIFT 17
7053 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
7054 #define SDHC_IRQSTAT_CEBE_SHIFT 18
7055 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
7056 #define SDHC_IRQSTAT_CIE_SHIFT 19
7057 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
7058 #define SDHC_IRQSTAT_DTOE_SHIFT 20
7059 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
7060 #define SDHC_IRQSTAT_DCE_SHIFT 21
7061 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
7062 #define SDHC_IRQSTAT_DEBE_SHIFT 22
7063 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
7064 #define SDHC_IRQSTAT_AC12E_SHIFT 24
7065 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
7066 #define SDHC_IRQSTAT_DMAE_SHIFT 28
7067 /* IRQSTATEN Bit Fields */
7068 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
7069 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
7070 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
7071 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
7072 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
7073 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
7074 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
7075 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
7076 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
7077 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
7078 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
7079 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
7080 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
7081 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
7082 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
7083 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
7084 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
7085 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
7086 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
7087 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
7088 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
7089 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
7090 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
7091 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
7092 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
7093 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
7094 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
7095 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
7096 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
7097 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
7098 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
7099 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
7100 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
7101 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
7102 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
7103 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
7104 /* IRQSIGEN Bit Fields */
7105 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
7106 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
7107 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
7108 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
7109 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
7110 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
7111 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
7112 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
7113 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
7114 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
7115 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
7116 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
7117 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
7118 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
7119 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
7120 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
7121 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
7122 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
7123 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
7124 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
7125 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
7126 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
7127 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
7128 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
7129 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
7130 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
7131 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
7132 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
7133 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
7134 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
7135 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
7136 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
7137 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
7138 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
7139 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
7140 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
7141 /* AC12ERR Bit Fields */
7142 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
7143 #define SDHC_AC12ERR_AC12NE_SHIFT 0
7144 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
7145 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
7146 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
7147 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
7148 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
7149 #define SDHC_AC12ERR_AC12CE_SHIFT 3
7150 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
7151 #define SDHC_AC12ERR_AC12IE_SHIFT 4
7152 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
7153 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
7154 /* HTCAPBLT Bit Fields */
7155 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
7156 #define SDHC_HTCAPBLT_MBL_SHIFT 16
7157 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
7158 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
7159 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
7160 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
7161 #define SDHC_HTCAPBLT_HSS_SHIFT 21
7162 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
7163 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
7164 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
7165 #define SDHC_HTCAPBLT_SRS_SHIFT 23
7166 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
7167 #define SDHC_HTCAPBLT_VS33_SHIFT 24
7168 #define SDHC_HTCAPBLT_VS30_MASK 0x2000000u
7169 #define SDHC_HTCAPBLT_VS30_SHIFT 25
7170 #define SDHC_HTCAPBLT_VS18_MASK 0x4000000u
7171 #define SDHC_HTCAPBLT_VS18_SHIFT 26
7172 /* WML Bit Fields */
7173 #define SDHC_WML_RDWML_MASK 0xFFu
7174 #define SDHC_WML_RDWML_SHIFT 0
7175 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
7176 #define SDHC_WML_WRWML_MASK 0xFF0000u
7177 #define SDHC_WML_WRWML_SHIFT 16
7178 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
7179 #define SDHC_WML_WRBRSTLEN_MASK 0x1F000000u
7180 #define SDHC_WML_WRBRSTLEN_SHIFT 24
7181 #define SDHC_WML_WRBRSTLEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRBRSTLEN_SHIFT))&SDHC_WML_WRBRSTLEN_MASK)
7182 /* FEVT Bit Fields */
7183 #define SDHC_FEVT_AC12NE_MASK 0x1u
7184 #define SDHC_FEVT_AC12NE_SHIFT 0
7185 #define SDHC_FEVT_AC12TOE_MASK 0x2u
7186 #define SDHC_FEVT_AC12TOE_SHIFT 1
7187 #define SDHC_FEVT_AC12CE_MASK 0x4u
7188 #define SDHC_FEVT_AC12CE_SHIFT 2
7189 #define SDHC_FEVT_AC12EBE_MASK 0x8u
7190 #define SDHC_FEVT_AC12EBE_SHIFT 3
7191 #define SDHC_FEVT_AC12IE_MASK 0x10u
7192 #define SDHC_FEVT_AC12IE_SHIFT 4
7193 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
7194 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
7195 #define SDHC_FEVT_CTOE_MASK 0x10000u
7196 #define SDHC_FEVT_CTOE_SHIFT 16
7197 #define SDHC_FEVT_CCE_MASK 0x20000u
7198 #define SDHC_FEVT_CCE_SHIFT 17
7199 #define SDHC_FEVT_CEBE_MASK 0x40000u
7200 #define SDHC_FEVT_CEBE_SHIFT 18
7201 #define SDHC_FEVT_CIE_MASK 0x80000u
7202 #define SDHC_FEVT_CIE_SHIFT 19
7203 #define SDHC_FEVT_DTOE_MASK 0x100000u
7204 #define SDHC_FEVT_DTOE_SHIFT 20
7205 #define SDHC_FEVT_DCE_MASK 0x200000u
7206 #define SDHC_FEVT_DCE_SHIFT 21
7207 #define SDHC_FEVT_DEBE_MASK 0x400000u
7208 #define SDHC_FEVT_DEBE_SHIFT 22
7209 #define SDHC_FEVT_AC12E_MASK 0x1000000u
7210 #define SDHC_FEVT_AC12E_SHIFT 24
7211 #define SDHC_FEVT_DMAE_MASK 0x10000000u
7212 #define SDHC_FEVT_DMAE_SHIFT 28
7213 #define SDHC_FEVT_CINT_MASK 0x80000000u
7214 #define SDHC_FEVT_CINT_SHIFT 31
7215 /* ADMAES Bit Fields */
7216 #define SDHC_ADMAES_ADMAES_MASK 0x3u
7217 #define SDHC_ADMAES_ADMAES_SHIFT 0
7218 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
7219 #define SDHC_ADMAES_ADMALME_MASK 0x4u
7220 #define SDHC_ADMAES_ADMALME_SHIFT 2
7221 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
7222 #define SDHC_ADMAES_ADMADCE_SHIFT 3
7223 /* ADSADDR Bit Fields */
7224 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
7225 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
7226 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
7227 /* VENDOR Bit Fields */
7228 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
7229 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
7230 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
7231 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
7232 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
7233 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
7234 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
7235 /* MMCBOOT Bit Fields */
7236 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
7237 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
7238 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
7239 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
7240 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
7241 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
7242 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
7243 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
7244 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
7245 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
7246 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
7247 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
7248 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
7249 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
7250 /* HOSTVER Bit Fields */
7251 #define SDHC_HOSTVER_SVN_MASK 0xFFu
7252 #define SDHC_HOSTVER_SVN_SHIFT 0
7253 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
7254 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
7255 #define SDHC_HOSTVER_VVN_SHIFT 8
7256 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
7257 
7258 /**
7259  * @}
7260  */ /* end of group SDHC_Register_Masks */
7261 
7262 
7263 /* SDHC - Peripheral instance base addresses */
7264 /** Peripheral SDHC base address */
7265 #define SDHC_BASE (0x400B1000u)
7266 /** Peripheral SDHC base pointer */
7267 #define SDHC ((SDHC_Type *)SDHC_BASE)
7268 
7269 /**
7270  * @}
7271  */ /* end of group SDHC_Peripheral_Access_Layer */
7272 
7273 
7274 /* ----------------------------------------------------------------------------
7275  -- SIM Peripheral Access Layer
7276  ---------------------------------------------------------------------------- */
7277 
7278 /**
7279  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
7280  * @{
7281  */
7282 
7283 /** SIM - Register Layout Typedef */
7284 typedef struct {
7285  __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
7286  uint8_t RESERVED_0[4096];
7287  __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
7288  uint8_t RESERVED_1[4];
7289  __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
7290  __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
7291  __IO uint32_t SOPT6; /**< System Options Register 6, offset: 0x1014 */
7292  __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
7293  uint8_t RESERVED_2[8];
7294  __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
7295  __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
7296  __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
7297  __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
7298  __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
7299  __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
7300  __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
7301  __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
7302  __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
7303  __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
7304  __I uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
7305  __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
7306  __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
7307  __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
7308  __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
7309  __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
7310 } SIM_Type;
7311 
7312 /* ----------------------------------------------------------------------------
7313  -- SIM Register Masks
7314  ---------------------------------------------------------------------------- */
7315 
7316 /**
7317  * @addtogroup SIM_Register_Masks SIM Register Masks
7318  * @{
7319  */
7320 
7321 /* SOPT1 Bit Fields */
7322 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
7323 #define SIM_SOPT1_RAMSIZE_SHIFT 12
7324 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
7325 #define SIM_SOPT1_OSC32KSEL_MASK 0x80000u
7326 #define SIM_SOPT1_OSC32KSEL_SHIFT 19
7327 #define SIM_SOPT1_MS_MASK 0x800000u
7328 #define SIM_SOPT1_MS_SHIFT 23
7329 #define SIM_SOPT1_USBSTBY_MASK 0x40000000u
7330 #define SIM_SOPT1_USBSTBY_SHIFT 30
7331 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
7332 #define SIM_SOPT1_USBREGEN_SHIFT 31
7333 /* SOPT2 Bit Fields */
7334 #define SIM_SOPT2_MCGCLKSEL_MASK 0x1u
7335 #define SIM_SOPT2_MCGCLKSEL_SHIFT 0
7336 #define SIM_SOPT2_FBSL_MASK 0x300u
7337 #define SIM_SOPT2_FBSL_SHIFT 8
7338 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
7339 #define SIM_SOPT2_CMTUARTPAD_MASK 0x800u
7340 #define SIM_SOPT2_CMTUARTPAD_SHIFT 11
7341 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
7342 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
7343 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
7344 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
7345 #define SIM_SOPT2_USBSRC_MASK 0x40000u
7346 #define SIM_SOPT2_USBSRC_SHIFT 18
7347 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
7348 #define SIM_SOPT2_TIMESRC_SHIFT 20
7349 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
7350 #define SIM_SOPT2_I2SSRC_MASK 0x3000000u
7351 #define SIM_SOPT2_I2SSRC_SHIFT 24
7352 #define SIM_SOPT2_I2SSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_I2SSRC_SHIFT))&SIM_SOPT2_I2SSRC_MASK)
7353 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
7354 #define SIM_SOPT2_SDHCSRC_SHIFT 28
7355 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
7356 /* SOPT4 Bit Fields */
7357 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
7358 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
7359 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
7360 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
7361 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
7362 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
7363 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
7364 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
7365 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
7366 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
7367 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
7368 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
7369 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
7370 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
7371 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
7372 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
7373 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
7374 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
7375 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
7376 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
7377 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
7378 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
7379 /* SOPT5 Bit Fields */
7380 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
7381 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
7382 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
7383 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
7384 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
7385 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
7386 #define SIM_SOPT5_UARTTXSRC_MASK 0x30u
7387 #define SIM_SOPT5_UARTTXSRC_SHIFT 4
7388 #define SIM_SOPT5_UARTTXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UARTTXSRC_SHIFT))&SIM_SOPT5_UARTTXSRC_MASK)
7389 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
7390 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
7391 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
7392 /* SOPT6 Bit Fields */
7393 #define SIM_SOPT6_RSTFLTSEL_MASK 0x1F000000u
7394 #define SIM_SOPT6_RSTFLTSEL_SHIFT 24
7395 #define SIM_SOPT6_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTSEL_SHIFT))&SIM_SOPT6_RSTFLTSEL_MASK)
7396 #define SIM_SOPT6_RSTFLTEN_MASK 0xE0000000u
7397 #define SIM_SOPT6_RSTFLTEN_SHIFT 29
7398 #define SIM_SOPT6_RSTFLTEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTEN_SHIFT))&SIM_SOPT6_RSTFLTEN_MASK)
7399 /* SOPT7 Bit Fields */
7400 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
7401 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
7402 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
7403 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
7404 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
7405 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
7406 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
7407 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
7408 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
7409 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
7410 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
7411 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
7412 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
7413 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
7414 /* SDID Bit Fields */
7415 #define SIM_SDID_PINID_MASK 0xFu
7416 #define SIM_SDID_PINID_SHIFT 0
7417 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
7418 #define SIM_SDID_FAMID_MASK 0x70u
7419 #define SIM_SDID_FAMID_SHIFT 4
7420 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
7421 #define SIM_SDID_REVID_MASK 0xF000u
7422 #define SIM_SDID_REVID_SHIFT 12
7423 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
7424 /* SCGC1 Bit Fields */
7425 #define SIM_SCGC1_UART4_MASK 0x400u
7426 #define SIM_SCGC1_UART4_SHIFT 10
7427 #define SIM_SCGC1_UART5_MASK 0x800u
7428 #define SIM_SCGC1_UART5_SHIFT 11
7429 /* SCGC2 Bit Fields */
7430 #define SIM_SCGC2_ENET_MASK 0x1u
7431 #define SIM_SCGC2_ENET_SHIFT 0
7432 #define SIM_SCGC2_DAC0_MASK 0x1000u
7433 #define SIM_SCGC2_DAC0_SHIFT 12
7434 #define SIM_SCGC2_DAC1_MASK 0x2000u
7435 #define SIM_SCGC2_DAC1_SHIFT 13
7436 /* SCGC3 Bit Fields */
7437 #define SIM_SCGC3_RNGB_MASK 0x1u
7438 #define SIM_SCGC3_RNGB_SHIFT 0
7439 #define SIM_SCGC3_FLEXCAN1_MASK 0x10u
7440 #define SIM_SCGC3_FLEXCAN1_SHIFT 4
7441 #define SIM_SCGC3_SPI2_MASK 0x1000u
7442 #define SIM_SCGC3_SPI2_SHIFT 12
7443 #define SIM_SCGC3_SDHC_MASK 0x20000u
7444 #define SIM_SCGC3_SDHC_SHIFT 17
7445 #define SIM_SCGC3_FTM2_MASK 0x1000000u
7446 #define SIM_SCGC3_FTM2_SHIFT 24
7447 #define SIM_SCGC3_ADC1_MASK 0x8000000u
7448 #define SIM_SCGC3_ADC1_SHIFT 27
7449 /* SCGC4 Bit Fields */
7450 #define SIM_SCGC4_EWM_MASK 0x2u
7451 #define SIM_SCGC4_EWM_SHIFT 1
7452 #define SIM_SCGC4_CMT_MASK 0x4u
7453 #define SIM_SCGC4_CMT_SHIFT 2
7454 #define SIM_SCGC4_I2C0_MASK 0x40u
7455 #define SIM_SCGC4_I2C0_SHIFT 6
7456 #define SIM_SCGC4_I2C1_MASK 0x80u
7457 #define SIM_SCGC4_I2C1_SHIFT 7
7458 #define SIM_SCGC4_UART0_MASK 0x400u
7459 #define SIM_SCGC4_UART0_SHIFT 10
7460 #define SIM_SCGC4_UART1_MASK 0x800u
7461 #define SIM_SCGC4_UART1_SHIFT 11
7462 #define SIM_SCGC4_UART2_MASK 0x1000u
7463 #define SIM_SCGC4_UART2_SHIFT 12
7464 #define SIM_SCGC4_UART3_MASK 0x2000u
7465 #define SIM_SCGC4_UART3_SHIFT 13
7466 #define SIM_SCGC4_USBOTG_MASK 0x40000u
7467 #define SIM_SCGC4_USBOTG_SHIFT 18
7468 #define SIM_SCGC4_CMP_MASK 0x80000u
7469 #define SIM_SCGC4_CMP_SHIFT 19
7470 #define SIM_SCGC4_VREF_MASK 0x100000u
7471 #define SIM_SCGC4_VREF_SHIFT 20
7472 #define SIM_SCGC4_LLWU_MASK 0x10000000u
7473 #define SIM_SCGC4_LLWU_SHIFT 28
7474 /* SCGC5 Bit Fields */
7475 #define SIM_SCGC5_LPTIMER_MASK 0x1u
7476 #define SIM_SCGC5_LPTIMER_SHIFT 0
7477 #define SIM_SCGC5_REGFILE_MASK 0x2u
7478 #define SIM_SCGC5_REGFILE_SHIFT 1
7479 #define SIM_SCGC5_TSI_MASK 0x20u
7480 #define SIM_SCGC5_TSI_SHIFT 5
7481 #define SIM_SCGC5_PORTA_MASK 0x200u
7482 #define SIM_SCGC5_PORTA_SHIFT 9
7483 #define SIM_SCGC5_PORTB_MASK 0x400u
7484 #define SIM_SCGC5_PORTB_SHIFT 10
7485 #define SIM_SCGC5_PORTC_MASK 0x800u
7486 #define SIM_SCGC5_PORTC_SHIFT 11
7487 #define SIM_SCGC5_PORTD_MASK 0x1000u
7488 #define SIM_SCGC5_PORTD_SHIFT 12
7489 #define SIM_SCGC5_PORTE_MASK 0x2000u
7490 #define SIM_SCGC5_PORTE_SHIFT 13
7491 /* SCGC6 Bit Fields */
7492 #define SIM_SCGC6_FTFL_MASK 0x1u
7493 #define SIM_SCGC6_FTFL_SHIFT 0
7494 #define SIM_SCGC6_DMAMUX_MASK 0x2u
7495 #define SIM_SCGC6_DMAMUX_SHIFT 1
7496 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
7497 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
7498 #define SIM_SCGC6_DSPI0_MASK 0x1000u
7499 #define SIM_SCGC6_DSPI0_SHIFT 12
7500 #define SIM_SCGC6_SPI1_MASK 0x2000u
7501 #define SIM_SCGC6_SPI1_SHIFT 13
7502 #define SIM_SCGC6_I2S_MASK 0x8000u
7503 #define SIM_SCGC6_I2S_SHIFT 15
7504 #define SIM_SCGC6_CRC_MASK 0x40000u
7505 #define SIM_SCGC6_CRC_SHIFT 18
7506 #define SIM_SCGC6_USBDCD_MASK 0x200000u
7507 #define SIM_SCGC6_USBDCD_SHIFT 21
7508 #define SIM_SCGC6_PDB_MASK 0x400000u
7509 #define SIM_SCGC6_PDB_SHIFT 22
7510 #define SIM_SCGC6_PIT_MASK 0x800000u
7511 #define SIM_SCGC6_PIT_SHIFT 23
7512 #define SIM_SCGC6_FTM0_MASK 0x1000000u
7513 #define SIM_SCGC6_FTM0_SHIFT 24
7514 #define SIM_SCGC6_FTM1_MASK 0x2000000u
7515 #define SIM_SCGC6_FTM1_SHIFT 25
7516 #define SIM_SCGC6_ADC0_MASK 0x8000000u
7517 #define SIM_SCGC6_ADC0_SHIFT 27
7518 #define SIM_SCGC6_RTC_MASK 0x20000000u
7519 #define SIM_SCGC6_RTC_SHIFT 29
7520 /* SCGC7 Bit Fields */
7521 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
7522 #define SIM_SCGC7_FLEXBUS_SHIFT 0
7523 #define SIM_SCGC7_DMA_MASK 0x2u
7524 #define SIM_SCGC7_DMA_SHIFT 1
7525 #define SIM_SCGC7_MPU_MASK 0x4u
7526 #define SIM_SCGC7_MPU_SHIFT 2
7527 /* CLKDIV1 Bit Fields */
7528 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
7529 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
7530 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
7531 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
7532 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
7533 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
7534 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
7535 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
7536 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
7537 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
7538 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
7539 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
7540 /* CLKDIV2 Bit Fields */
7541 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
7542 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
7543 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
7544 #define SIM_CLKDIV2_USBDIV_SHIFT 1
7545 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
7546 #define SIM_CLKDIV2_I2SFRAC_MASK 0xFF00u
7547 #define SIM_CLKDIV2_I2SFRAC_SHIFT 8
7548 #define SIM_CLKDIV2_I2SFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SFRAC_SHIFT))&SIM_CLKDIV2_I2SFRAC_MASK)
7549 #define SIM_CLKDIV2_I2SDIV_MASK 0xFFF00000u
7550 #define SIM_CLKDIV2_I2SDIV_SHIFT 20
7551 #define SIM_CLKDIV2_I2SDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SDIV_SHIFT))&SIM_CLKDIV2_I2SDIV_MASK)
7552 /* FCFG1 Bit Fields */
7553 #define SIM_FCFG1_DEPART_MASK 0xF00u
7554 #define SIM_FCFG1_DEPART_SHIFT 8
7555 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
7556 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
7557 #define SIM_FCFG1_EESIZE_SHIFT 16
7558 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
7559 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
7560 #define SIM_FCFG1_PFSIZE_SHIFT 24
7561 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
7562 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
7563 #define SIM_FCFG1_NVMSIZE_SHIFT 28
7564 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
7565 /* FCFG2 Bit Fields */
7566 #define SIM_FCFG2_MAXADDR1_MASK 0x3F0000u
7567 #define SIM_FCFG2_MAXADDR1_SHIFT 16
7568 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
7569 #define SIM_FCFG2_PFLSH_MASK 0x800000u
7570 #define SIM_FCFG2_PFLSH_SHIFT 23
7571 #define SIM_FCFG2_MAXADDR0_MASK 0x3F000000u
7572 #define SIM_FCFG2_MAXADDR0_SHIFT 24
7573 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
7574 #define SIM_FCFG2_SWAPPFLSH_MASK 0x80000000u
7575 #define SIM_FCFG2_SWAPPFLSH_SHIFT 31
7576 /* UIDH Bit Fields */
7577 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
7578 #define SIM_UIDH_UID_SHIFT 0
7579 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
7580 /* UIDMH Bit Fields */
7581 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
7582 #define SIM_UIDMH_UID_SHIFT 0
7583 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
7584 /* UIDML Bit Fields */
7585 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
7586 #define SIM_UIDML_UID_SHIFT 0
7587 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
7588 /* UIDL Bit Fields */
7589 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
7590 #define SIM_UIDL_UID_SHIFT 0
7591 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
7592 
7593 /**
7594  * @}
7595  */ /* end of group SIM_Register_Masks */
7596 
7597 
7598 /* SIM - Peripheral instance base addresses */
7599 /** Peripheral SIM base address */
7600 #define SIM_BASE (0x40047000u)
7601 /** Peripheral SIM base pointer */
7602 #define SIM ((SIM_Type *)SIM_BASE)
7603 
7604 /**
7605  * @}
7606  */ /* end of group SIM_Peripheral_Access_Layer */
7607 
7608 
7609 /* ----------------------------------------------------------------------------
7610  -- SPI Peripheral Access Layer
7611  ---------------------------------------------------------------------------- */
7612 
7613 /**
7614  * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
7615  * @{
7616  */
7617 
7618 /** SPI - Register Layout Typedef */
7619 typedef struct {
7620  __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
7621  uint8_t RESERVED_0[4];
7622  __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
7623  union { /* offset: 0xC */
7624  __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
7625  __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
7626  };
7627  uint8_t RESERVED_1[24];
7628  __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
7629  __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
7630  union { /* offset: 0x34 */
7631  __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
7632  __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
7633  };
7634  __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
7635  __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
7636  __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
7637  __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
7638  __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
7639  uint8_t RESERVED_2[48];
7640  __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
7641  __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
7642  __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
7643  __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
7644 } SPI_Type;
7645 
7646 /* ----------------------------------------------------------------------------
7647  -- SPI Register Masks
7648  ---------------------------------------------------------------------------- */
7649 
7650 /**
7651  * @addtogroup SPI_Register_Masks SPI Register Masks
7652  * @{
7653  */
7654 
7655 /* MCR Bit Fields */
7656 #define SPI_MCR_HALT_MASK 0x1u
7657 #define SPI_MCR_HALT_SHIFT 0
7658 #define SPI_MCR_SMPL_PT_MASK 0x300u
7659 #define SPI_MCR_SMPL_PT_SHIFT 8
7660 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
7661 #define SPI_MCR_CLR_RXF_MASK 0x400u
7662 #define SPI_MCR_CLR_RXF_SHIFT 10
7663 #define SPI_MCR_CLR_TXF_MASK 0x800u
7664 #define SPI_MCR_CLR_TXF_SHIFT 11
7665 #define SPI_MCR_DIS_RXF_MASK 0x1000u
7666 #define SPI_MCR_DIS_RXF_SHIFT 12
7667 #define SPI_MCR_DIS_TXF_MASK 0x2000u
7668 #define SPI_MCR_DIS_TXF_SHIFT 13
7669 #define SPI_MCR_MDIS_MASK 0x4000u
7670 #define SPI_MCR_MDIS_SHIFT 14
7671 #define SPI_MCR_DOZE_MASK 0x8000u
7672 #define SPI_MCR_DOZE_SHIFT 15
7673 #define SPI_MCR_PCSIS_MASK 0x3F0000u
7674 #define SPI_MCR_PCSIS_SHIFT 16
7675 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
7676 #define SPI_MCR_ROOE_MASK 0x1000000u
7677 #define SPI_MCR_ROOE_SHIFT 24
7678 #define SPI_MCR_PCSSE_MASK 0x2000000u
7679 #define SPI_MCR_PCSSE_SHIFT 25
7680 #define SPI_MCR_MTFE_MASK 0x4000000u
7681 #define SPI_MCR_MTFE_SHIFT 26
7682 #define SPI_MCR_FRZ_MASK 0x8000000u
7683 #define SPI_MCR_FRZ_SHIFT 27
7684 #define SPI_MCR_DCONF_MASK 0x30000000u
7685 #define SPI_MCR_DCONF_SHIFT 28
7686 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
7687 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
7688 #define SPI_MCR_CONT_SCKE_SHIFT 30
7689 #define SPI_MCR_MSTR_MASK 0x80000000u
7690 #define SPI_MCR_MSTR_SHIFT 31
7691 /* TCR Bit Fields */
7692 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
7693 #define SPI_TCR_SPI_TCNT_SHIFT 16
7694 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
7695 /* CTAR Bit Fields */
7696 #define SPI_CTAR_BR_MASK 0xFu
7697 #define SPI_CTAR_BR_SHIFT 0
7698 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
7699 #define SPI_CTAR_DT_MASK 0xF0u
7700 #define SPI_CTAR_DT_SHIFT 4
7701 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
7702 #define SPI_CTAR_ASC_MASK 0xF00u
7703 #define SPI_CTAR_ASC_SHIFT 8
7704 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
7705 #define SPI_CTAR_CSSCK_MASK 0xF000u
7706 #define SPI_CTAR_CSSCK_SHIFT 12
7707 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
7708 #define SPI_CTAR_PBR_MASK 0x30000u
7709 #define SPI_CTAR_PBR_SHIFT 16
7710 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
7711 #define SPI_CTAR_PDT_MASK 0xC0000u
7712 #define SPI_CTAR_PDT_SHIFT 18
7713 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
7714 #define SPI_CTAR_PASC_MASK 0x300000u
7715 #define SPI_CTAR_PASC_SHIFT 20
7716 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
7717 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
7718 #define SPI_CTAR_PCSSCK_SHIFT 22
7719 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
7720 #define SPI_CTAR_LSBFE_MASK 0x1000000u
7721 #define SPI_CTAR_LSBFE_SHIFT 24
7722 #define SPI_CTAR_CPHA_MASK 0x2000000u
7723 #define SPI_CTAR_CPHA_SHIFT 25
7724 #define SPI_CTAR_CPOL_MASK 0x4000000u
7725 #define SPI_CTAR_CPOL_SHIFT 26
7726 #define SPI_CTAR_FMSZ_MASK 0x78000000u
7727 #define SPI_CTAR_FMSZ_SHIFT 27
7728 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
7729 #define SPI_CTAR_DBR_MASK 0x80000000u
7730 #define SPI_CTAR_DBR_SHIFT 31
7731 /* CTAR_SLAVE Bit Fields */
7732 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
7733 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
7734 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
7735 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
7736 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
7737 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
7738 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
7739 /* SR Bit Fields */
7740 #define SPI_SR_POPNXTPTR_MASK 0xFu
7741 #define SPI_SR_POPNXTPTR_SHIFT 0
7742 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
7743 #define SPI_SR_RXCTR_MASK 0xF0u
7744 #define SPI_SR_RXCTR_SHIFT 4
7745 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
7746 #define SPI_SR_TXNXTPTR_MASK 0xF00u
7747 #define SPI_SR_TXNXTPTR_SHIFT 8
7748 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
7749 #define SPI_SR_TXCTR_MASK 0xF000u
7750 #define SPI_SR_TXCTR_SHIFT 12
7751 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
7752 #define SPI_SR_RFDF_MASK 0x20000u
7753 #define SPI_SR_RFDF_SHIFT 17
7754 #define SPI_SR_RFOF_MASK 0x80000u
7755 #define SPI_SR_RFOF_SHIFT 19
7756 #define SPI_SR_TFFF_MASK 0x2000000u
7757 #define SPI_SR_TFFF_SHIFT 25
7758 #define SPI_SR_TFUF_MASK 0x8000000u
7759 #define SPI_SR_TFUF_SHIFT 27
7760 #define SPI_SR_EOQF_MASK 0x10000000u
7761 #define SPI_SR_EOQF_SHIFT 28
7762 #define SPI_SR_TXRXS_MASK 0x40000000u
7763 #define SPI_SR_TXRXS_SHIFT 30
7764 #define SPI_SR_TCF_MASK 0x80000000u
7765 #define SPI_SR_TCF_SHIFT 31
7766 /* RSER Bit Fields */
7767 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
7768 #define SPI_RSER_RFDF_DIRS_SHIFT 16
7769 #define SPI_RSER_RFDF_RE_MASK 0x20000u
7770 #define SPI_RSER_RFDF_RE_SHIFT 17
7771 #define SPI_RSER_RFOF_RE_MASK 0x80000u
7772 #define SPI_RSER_RFOF_RE_SHIFT 19
7773 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
7774 #define SPI_RSER_TFFF_DIRS_SHIFT 24
7775 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
7776 #define SPI_RSER_TFFF_RE_SHIFT 25
7777 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
7778 #define SPI_RSER_TFUF_RE_SHIFT 27
7779 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
7780 #define SPI_RSER_EOQF_RE_SHIFT 28
7781 #define SPI_RSER_TCF_RE_MASK 0x80000000u
7782 #define SPI_RSER_TCF_RE_SHIFT 31
7783 /* PUSHR Bit Fields */
7784 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
7785 #define SPI_PUSHR_TXDATA_SHIFT 0
7786 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
7787 #define SPI_PUSHR_PCS_MASK 0x3F0000u
7788 #define SPI_PUSHR_PCS_SHIFT 16
7789 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
7790 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
7791 #define SPI_PUSHR_CTCNT_SHIFT 26
7792 #define SPI_PUSHR_EOQ_MASK 0x8000000u
7793 #define SPI_PUSHR_EOQ_SHIFT 27
7794 #define SPI_PUSHR_CTAS_MASK 0x70000000u
7795 #define SPI_PUSHR_CTAS_SHIFT 28
7796 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
7797 #define SPI_PUSHR_CONT_MASK 0x80000000u
7798 #define SPI_PUSHR_CONT_SHIFT 31
7799 /* PUSHR_SLAVE Bit Fields */
7800 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
7801 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
7802 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
7803 /* POPR Bit Fields */
7804 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
7805 #define SPI_POPR_RXDATA_SHIFT 0
7806 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
7807 /* TXFR0 Bit Fields */
7808 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
7809 #define SPI_TXFR0_TXDATA_SHIFT 0
7810 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
7811 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
7812 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
7813 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
7814 /* TXFR1 Bit Fields */
7815 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
7816 #define SPI_TXFR1_TXDATA_SHIFT 0
7817 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
7818 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
7819 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
7820 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
7821 /* TXFR2 Bit Fields */
7822 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
7823 #define SPI_TXFR2_TXDATA_SHIFT 0
7824 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
7825 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
7826 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
7827 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
7828 /* TXFR3 Bit Fields */
7829 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
7830 #define SPI_TXFR3_TXDATA_SHIFT 0
7831 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
7832 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
7833 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
7834 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
7835 /* RXFR0 Bit Fields */
7836 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
7837 #define SPI_RXFR0_RXDATA_SHIFT 0
7838 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
7839 /* RXFR1 Bit Fields */
7840 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
7841 #define SPI_RXFR1_RXDATA_SHIFT 0
7842 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
7843 /* RXFR2 Bit Fields */
7844 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
7845 #define SPI_RXFR2_RXDATA_SHIFT 0
7846 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
7847 /* RXFR3 Bit Fields */
7848 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
7849 #define SPI_RXFR3_RXDATA_SHIFT 0
7850 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
7851 
7852 /**
7853  * @}
7854  */ /* end of group SPI_Register_Masks */
7855 
7856 
7857 /* SPI - Peripheral instance base addresses */
7858 /** Peripheral SPI0 base address */
7859 #define SPI0_BASE (0x4002C000u)
7860 /** Peripheral SPI0 base pointer */
7861 #define SPI0 ((SPI_Type *)SPI0_BASE)
7862 /** Peripheral SPI1 base address */
7863 #define SPI1_BASE (0x4002D000u)
7864 /** Peripheral SPI1 base pointer */
7865 #define SPI1 ((SPI_Type *)SPI1_BASE)
7866 /** Peripheral SPI2 base address */
7867 #define SPI2_BASE (0x400AC000u)
7868 /** Peripheral SPI2 base pointer */
7869 #define SPI2 ((SPI_Type *)SPI2_BASE)
7870 
7871 /**
7872  * @}
7873  */ /* end of group SPI_Peripheral_Access_Layer */
7874 
7875 
7876 /* ----------------------------------------------------------------------------
7877  -- TSI Peripheral Access Layer
7878  ---------------------------------------------------------------------------- */
7879 
7880 /**
7881  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
7882  * @{
7883  */
7884 
7885 /** TSI - Register Layout Typedef */
7886 typedef struct {
7887  __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
7888  __IO uint32_t SCANC; /**< SCAN control register, offset: 0x4 */
7889  __IO uint32_t PEN; /**< Pin enable register, offset: 0x8 */
7890  __IO uint32_t STATUS; /**< Status Register, offset: 0xC */
7891  uint8_t RESERVED_0[240];
7892  __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
7893  __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
7894  __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
7895  __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
7896  __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
7897  __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
7898  __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
7899  __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
7900  __IO uint32_t THRESHLD[16]; /**< Channel n threshold register, array offset: 0x120, array step: 0x4 */
7901 } TSI_Type;
7902 
7903 /* ----------------------------------------------------------------------------
7904  -- TSI Register Masks
7905  ---------------------------------------------------------------------------- */
7906 
7907 /**
7908  * @addtogroup TSI_Register_Masks TSI Register Masks
7909  * @{
7910  */
7911 
7912 /* GENCS Bit Fields */
7913 #define TSI_GENCS_STPE_MASK 0x1u
7914 #define TSI_GENCS_STPE_SHIFT 0
7915 #define TSI_GENCS_STM_MASK 0x2u
7916 #define TSI_GENCS_STM_SHIFT 1
7917 #define TSI_GENCS_ESOR_MASK 0x10u
7918 #define TSI_GENCS_ESOR_SHIFT 4
7919 #define TSI_GENCS_ERIE_MASK 0x20u
7920 #define TSI_GENCS_ERIE_SHIFT 5
7921 #define TSI_GENCS_TSIIE_MASK 0x40u
7922 #define TSI_GENCS_TSIIE_SHIFT 6
7923 #define TSI_GENCS_TSIEN_MASK 0x80u
7924 #define TSI_GENCS_TSIEN_SHIFT 7
7925 #define TSI_GENCS_SWTS_MASK 0x100u
7926 #define TSI_GENCS_SWTS_SHIFT 8
7927 #define TSI_GENCS_SCNIP_MASK 0x200u
7928 #define TSI_GENCS_SCNIP_SHIFT 9
7929 #define TSI_GENCS_OVRF_MASK 0x1000u
7930 #define TSI_GENCS_OVRF_SHIFT 12
7931 #define TSI_GENCS_EXTERF_MASK 0x2000u
7932 #define TSI_GENCS_EXTERF_SHIFT 13
7933 #define TSI_GENCS_OUTRGF_MASK 0x4000u
7934 #define TSI_GENCS_OUTRGF_SHIFT 14
7935 #define TSI_GENCS_EOSF_MASK 0x8000u
7936 #define TSI_GENCS_EOSF_SHIFT 15
7937 #define TSI_GENCS_PS_MASK 0x70000u
7938 #define TSI_GENCS_PS_SHIFT 16
7939 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
7940 #define TSI_GENCS_NSCN_MASK 0xF80000u
7941 #define TSI_GENCS_NSCN_SHIFT 19
7942 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
7943 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
7944 #define TSI_GENCS_LPSCNITV_SHIFT 24
7945 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
7946 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
7947 #define TSI_GENCS_LPCLKS_SHIFT 28
7948 /* SCANC Bit Fields */
7949 #define TSI_SCANC_AMPSC_MASK 0x7u
7950 #define TSI_SCANC_AMPSC_SHIFT 0
7951 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
7952 #define TSI_SCANC_AMCLKS_MASK 0x18u
7953 #define TSI_SCANC_AMCLKS_SHIFT 3
7954 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
7955 #define TSI_SCANC_AMCLKDIV_MASK 0x20u
7956 #define TSI_SCANC_AMCLKDIV_SHIFT 5
7957 #define TSI_SCANC_SMOD_MASK 0xFF00u
7958 #define TSI_SCANC_SMOD_SHIFT 8
7959 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
7960 #define TSI_SCANC_DELVOL_MASK 0x70000u
7961 #define TSI_SCANC_DELVOL_SHIFT 16
7962 #define TSI_SCANC_DELVOL(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_DELVOL_SHIFT))&TSI_SCANC_DELVOL_MASK)
7963 #define TSI_SCANC_EXTCHRG_MASK 0xF80000u
7964 #define TSI_SCANC_EXTCHRG_SHIFT 19
7965 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
7966 #define TSI_SCANC_CAPTRM_MASK 0x7000000u
7967 #define TSI_SCANC_CAPTRM_SHIFT 24
7968 #define TSI_SCANC_CAPTRM(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_CAPTRM_SHIFT))&TSI_SCANC_CAPTRM_MASK)
7969 #define TSI_SCANC_REFCHRG_MASK 0xF8000000u
7970 #define TSI_SCANC_REFCHRG_SHIFT 27
7971 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
7972 /* PEN Bit Fields */
7973 #define TSI_PEN_PEN0_MASK 0x1u
7974 #define TSI_PEN_PEN0_SHIFT 0
7975 #define TSI_PEN_PEN1_MASK 0x2u
7976 #define TSI_PEN_PEN1_SHIFT 1
7977 #define TSI_PEN_PEN2_MASK 0x4u
7978 #define TSI_PEN_PEN2_SHIFT 2
7979 #define TSI_PEN_PEN3_MASK 0x8u
7980 #define TSI_PEN_PEN3_SHIFT 3
7981 #define TSI_PEN_PEN4_MASK 0x10u
7982 #define TSI_PEN_PEN4_SHIFT 4
7983 #define TSI_PEN_PEN5_MASK 0x20u
7984 #define TSI_PEN_PEN5_SHIFT 5
7985 #define TSI_PEN_PEN6_MASK 0x40u
7986 #define TSI_PEN_PEN6_SHIFT 6
7987 #define TSI_PEN_PEN7_MASK 0x80u
7988 #define TSI_PEN_PEN7_SHIFT 7
7989 #define TSI_PEN_PEN8_MASK 0x100u
7990 #define TSI_PEN_PEN8_SHIFT 8
7991 #define TSI_PEN_PEN9_MASK 0x200u
7992 #define TSI_PEN_PEN9_SHIFT 9
7993 #define TSI_PEN_PEN10_MASK 0x400u
7994 #define TSI_PEN_PEN10_SHIFT 10
7995 #define TSI_PEN_PEN11_MASK 0x800u
7996 #define TSI_PEN_PEN11_SHIFT 11
7997 #define TSI_PEN_PEN12_MASK 0x1000u
7998 #define TSI_PEN_PEN12_SHIFT 12
7999 #define TSI_PEN_PEN13_MASK 0x2000u
8000 #define TSI_PEN_PEN13_SHIFT 13
8001 #define TSI_PEN_PEN14_MASK 0x4000u
8002 #define TSI_PEN_PEN14_SHIFT 14
8003 #define TSI_PEN_PEN15_MASK 0x8000u
8004 #define TSI_PEN_PEN15_SHIFT 15
8005 #define TSI_PEN_LPSP_MASK 0xF0000u
8006 #define TSI_PEN_LPSP_SHIFT 16
8007 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
8008 /* STATUS Bit Fields */
8009 #define TSI_STATUS_ORNGF0_MASK 0x1u
8010 #define TSI_STATUS_ORNGF0_SHIFT 0
8011 #define TSI_STATUS_ORNGF1_MASK 0x2u
8012 #define TSI_STATUS_ORNGF1_SHIFT 1
8013 #define TSI_STATUS_ORNGF2_MASK 0x4u
8014 #define TSI_STATUS_ORNGF2_SHIFT 2
8015 #define TSI_STATUS_ORNGF3_MASK 0x8u
8016 #define TSI_STATUS_ORNGF3_SHIFT 3
8017 #define TSI_STATUS_ORNGF4_MASK 0x10u
8018 #define TSI_STATUS_ORNGF4_SHIFT 4
8019 #define TSI_STATUS_ORNGF5_MASK 0x20u
8020 #define TSI_STATUS_ORNGF5_SHIFT 5
8021 #define TSI_STATUS_ORNGF6_MASK 0x40u
8022 #define TSI_STATUS_ORNGF6_SHIFT 6
8023 #define TSI_STATUS_ORNGF7_MASK 0x80u
8024 #define TSI_STATUS_ORNGF7_SHIFT 7
8025 #define TSI_STATUS_ORNGF8_MASK 0x100u
8026 #define TSI_STATUS_ORNGF8_SHIFT 8
8027 #define TSI_STATUS_ORNGF9_MASK 0x200u
8028 #define TSI_STATUS_ORNGF9_SHIFT 9
8029 #define TSI_STATUS_ORNGF10_MASK 0x400u
8030 #define TSI_STATUS_ORNGF10_SHIFT 10
8031 #define TSI_STATUS_ORNGF11_MASK 0x800u
8032 #define TSI_STATUS_ORNGF11_SHIFT 11
8033 #define TSI_STATUS_ORNGF12_MASK 0x1000u
8034 #define TSI_STATUS_ORNGF12_SHIFT 12
8035 #define TSI_STATUS_ORNGF13_MASK 0x2000u
8036 #define TSI_STATUS_ORNGF13_SHIFT 13
8037 #define TSI_STATUS_ORNGF14_MASK 0x4000u
8038 #define TSI_STATUS_ORNGF14_SHIFT 14
8039 #define TSI_STATUS_ORNGF15_MASK 0x8000u
8040 #define TSI_STATUS_ORNGF15_SHIFT 15
8041 #define TSI_STATUS_ERROF0_MASK 0x10000u
8042 #define TSI_STATUS_ERROF0_SHIFT 16
8043 #define TSI_STATUS_ERROF1_MASK 0x20000u
8044 #define TSI_STATUS_ERROF1_SHIFT 17
8045 #define TSI_STATUS_ERROF2_MASK 0x40000u
8046 #define TSI_STATUS_ERROF2_SHIFT 18
8047 #define TSI_STATUS_ERROF3_MASK 0x80000u
8048 #define TSI_STATUS_ERROF3_SHIFT 19
8049 #define TSI_STATUS_ERROF4_MASK 0x100000u
8050 #define TSI_STATUS_ERROF4_SHIFT 20
8051 #define TSI_STATUS_ERROF5_MASK 0x200000u
8052 #define TSI_STATUS_ERROF5_SHIFT 21
8053 #define TSI_STATUS_ERROF6_MASK 0x400000u
8054 #define TSI_STATUS_ERROF6_SHIFT 22
8055 #define TSI_STATUS_ERROF7_MASK 0x800000u
8056 #define TSI_STATUS_ERROF7_SHIFT 23
8057 #define TSI_STATUS_ERROF8_MASK 0x1000000u
8058 #define TSI_STATUS_ERROF8_SHIFT 24
8059 #define TSI_STATUS_ERROF9_MASK 0x2000000u
8060 #define TSI_STATUS_ERROF9_SHIFT 25
8061 #define TSI_STATUS_ERROF10_MASK 0x4000000u
8062 #define TSI_STATUS_ERROF10_SHIFT 26
8063 #define TSI_STATUS_ERROF11_MASK 0x8000000u
8064 #define TSI_STATUS_ERROF11_SHIFT 27
8065 #define TSI_STATUS_ERROF12_MASK 0x10000000u
8066 #define TSI_STATUS_ERROF12_SHIFT 28
8067 #define TSI_STATUS_ERROF13_MASK 0x20000000u
8068 #define TSI_STATUS_ERROF13_SHIFT 29
8069 #define TSI_STATUS_ERROF14_MASK 0x40000000u
8070 #define TSI_STATUS_ERROF14_SHIFT 30
8071 #define TSI_STATUS_ERROF15_MASK 0x80000000u
8072 #define TSI_STATUS_ERROF15_SHIFT 31
8073 /* CNTR1 Bit Fields */
8074 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
8075 #define TSI_CNTR1_CTN1_SHIFT 0
8076 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
8077 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
8078 #define TSI_CNTR1_CTN_SHIFT 16
8079 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
8080 /* CNTR3 Bit Fields */
8081 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
8082 #define TSI_CNTR3_CTN1_SHIFT 0
8083 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
8084 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
8085 #define TSI_CNTR3_CTN_SHIFT 16
8086 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
8087 /* CNTR5 Bit Fields */
8088 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
8089 #define TSI_CNTR5_CTN1_SHIFT 0
8090 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
8091 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
8092 #define TSI_CNTR5_CTN_SHIFT 16
8093 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
8094 /* CNTR7 Bit Fields */
8095 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
8096 #define TSI_CNTR7_CTN1_SHIFT 0
8097 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
8098 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
8099 #define TSI_CNTR7_CTN_SHIFT 16
8100 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
8101 /* CNTR9 Bit Fields */
8102 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
8103 #define TSI_CNTR9_CTN1_SHIFT 0
8104 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
8105 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
8106 #define TSI_CNTR9_CTN_SHIFT 16
8107 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
8108 /* CNTR11 Bit Fields */
8109 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
8110 #define TSI_CNTR11_CTN1_SHIFT 0
8111 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
8112 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
8113 #define TSI_CNTR11_CTN_SHIFT 16
8114 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
8115 /* CNTR13 Bit Fields */
8116 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
8117 #define TSI_CNTR13_CTN1_SHIFT 0
8118 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
8119 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
8120 #define TSI_CNTR13_CTN_SHIFT 16
8121 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
8122 /* CNTR15 Bit Fields */
8123 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
8124 #define TSI_CNTR15_CTN1_SHIFT 0
8125 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
8126 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
8127 #define TSI_CNTR15_CTN_SHIFT 16
8128 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
8129 /* THRESHLD Bit Fields */
8130 #define TSI_THRESHLD_HTHH_MASK 0xFFFFu
8131 #define TSI_THRESHLD_HTHH_SHIFT 0
8132 #define TSI_THRESHLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_HTHH_SHIFT))&TSI_THRESHLD_HTHH_MASK)
8133 #define TSI_THRESHLD_LTHH_MASK 0xFFFF0000u
8134 #define TSI_THRESHLD_LTHH_SHIFT 16
8135 #define TSI_THRESHLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_LTHH_SHIFT))&TSI_THRESHLD_LTHH_MASK)
8136 
8137 /**
8138  * @}
8139  */ /* end of group TSI_Register_Masks */
8140 
8141 
8142 /* TSI - Peripheral instance base addresses */
8143 /** Peripheral TSI0 base address */
8144 #define TSI0_BASE (0x40045000u)
8145 /** Peripheral TSI0 base pointer */
8146 #define TSI0 ((TSI_Type *)TSI0_BASE)
8147 
8148 /**
8149  * @}
8150  */ /* end of group TSI_Peripheral_Access_Layer */
8151 
8152 
8153 /* ----------------------------------------------------------------------------
8154  -- UART Peripheral Access Layer
8155  ---------------------------------------------------------------------------- */
8156 
8157 /**
8158  * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
8159  * @{
8160  */
8161 
8162 /** UART - Register Layout Typedef */
8163 typedef struct {
8164  __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
8165  __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
8166  __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
8167  __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
8168  __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
8169  __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
8170  __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
8171  __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
8172  __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
8173  __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
8174  __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
8175  __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
8176  __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
8177  __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
8178  __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
8179  uint8_t RESERVED_0[1];
8180  __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
8181  __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
8182  __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
8183  __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
8184  __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
8185  __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
8186  __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
8187  uint8_t RESERVED_1[1];
8188  __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
8189  __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
8190  __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
8191  union { /* offset: 0x1B */
8192  __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
8193  __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
8194  };
8195  __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
8196  __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
8197  __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
8198  __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
8199 } UART_Type;
8200 
8201 /* ----------------------------------------------------------------------------
8202  -- UART Register Masks
8203  ---------------------------------------------------------------------------- */
8204 
8205 /**
8206  * @addtogroup UART_Register_Masks UART Register Masks
8207  * @{
8208  */
8209 
8210 /* BDH Bit Fields */
8211 #define UART_BDH_SBR_MASK 0x1Fu
8212 #define UART_BDH_SBR_SHIFT 0
8213 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
8214 #define UART_BDH_RXEDGIE_MASK 0x40u
8215 #define UART_BDH_RXEDGIE_SHIFT 6
8216 #define UART_BDH_LBKDIE_MASK 0x80u
8217 #define UART_BDH_LBKDIE_SHIFT 7
8218 /* BDL Bit Fields */
8219 #define UART_BDL_SBR_MASK 0xFFu
8220 #define UART_BDL_SBR_SHIFT 0
8221 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
8222 /* C1 Bit Fields */
8223 #define UART_C1_PT_MASK 0x1u
8224 #define UART_C1_PT_SHIFT 0
8225 #define UART_C1_PE_MASK 0x2u
8226 #define UART_C1_PE_SHIFT 1
8227 #define UART_C1_ILT_MASK 0x4u
8228 #define UART_C1_ILT_SHIFT 2
8229 #define UART_C1_WAKE_MASK 0x8u
8230 #define UART_C1_WAKE_SHIFT 3
8231 #define UART_C1_M_MASK 0x10u
8232 #define UART_C1_M_SHIFT 4
8233 #define UART_C1_RSRC_MASK 0x20u
8234 #define UART_C1_RSRC_SHIFT 5
8235 #define UART_C1_UARTSWAI_MASK 0x40u
8236 #define UART_C1_UARTSWAI_SHIFT 6
8237 #define UART_C1_LOOPS_MASK 0x80u
8238 #define UART_C1_LOOPS_SHIFT 7
8239 /* C2 Bit Fields */
8240 #define UART_C2_SBK_MASK 0x1u
8241 #define UART_C2_SBK_SHIFT 0
8242 #define UART_C2_RWU_MASK 0x2u
8243 #define UART_C2_RWU_SHIFT 1
8244 #define UART_C2_RE_MASK 0x4u
8245 #define UART_C2_RE_SHIFT 2
8246 #define UART_C2_TE_MASK 0x8u
8247 #define UART_C2_TE_SHIFT 3
8248 #define UART_C2_ILIE_MASK 0x10u
8249 #define UART_C2_ILIE_SHIFT 4
8250 #define UART_C2_RIE_MASK 0x20u
8251 #define UART_C2_RIE_SHIFT 5
8252 #define UART_C2_TCIE_MASK 0x40u
8253 #define UART_C2_TCIE_SHIFT 6
8254 #define UART_C2_TIE_MASK 0x80u
8255 #define UART_C2_TIE_SHIFT 7
8256 /* S1 Bit Fields */
8257 #define UART_S1_PF_MASK 0x1u
8258 #define UART_S1_PF_SHIFT 0
8259 #define UART_S1_FE_MASK 0x2u
8260 #define UART_S1_FE_SHIFT 1
8261 #define UART_S1_NF_MASK 0x4u
8262 #define UART_S1_NF_SHIFT 2
8263 #define UART_S1_OR_MASK 0x8u
8264 #define UART_S1_OR_SHIFT 3
8265 #define UART_S1_IDLE_MASK 0x10u
8266 #define UART_S1_IDLE_SHIFT 4
8267 #define UART_S1_RDRF_MASK 0x20u
8268 #define UART_S1_RDRF_SHIFT 5
8269 #define UART_S1_TC_MASK 0x40u
8270 #define UART_S1_TC_SHIFT 6
8271 #define UART_S1_TDRE_MASK 0x80u
8272 #define UART_S1_TDRE_SHIFT 7
8273 /* S2 Bit Fields */
8274 #define UART_S2_RAF_MASK 0x1u
8275 #define UART_S2_RAF_SHIFT 0
8276 #define UART_S2_LBKDE_MASK 0x2u
8277 #define UART_S2_LBKDE_SHIFT 1
8278 #define UART_S2_BRK13_MASK 0x4u
8279 #define UART_S2_BRK13_SHIFT 2
8280 #define UART_S2_RWUID_MASK 0x8u
8281 #define UART_S2_RWUID_SHIFT 3
8282 #define UART_S2_RXINV_MASK 0x10u
8283 #define UART_S2_RXINV_SHIFT 4
8284 #define UART_S2_MSBF_MASK 0x20u
8285 #define UART_S2_MSBF_SHIFT 5
8286 #define UART_S2_RXEDGIF_MASK 0x40u
8287 #define UART_S2_RXEDGIF_SHIFT 6
8288 #define UART_S2_LBKDIF_MASK 0x80u
8289 #define UART_S2_LBKDIF_SHIFT 7
8290 /* C3 Bit Fields */
8291 #define UART_C3_PEIE_MASK 0x1u
8292 #define UART_C3_PEIE_SHIFT 0
8293 #define UART_C3_FEIE_MASK 0x2u
8294 #define UART_C3_FEIE_SHIFT 1
8295 #define UART_C3_NEIE_MASK 0x4u
8296 #define UART_C3_NEIE_SHIFT 2
8297 #define UART_C3_ORIE_MASK 0x8u
8298 #define UART_C3_ORIE_SHIFT 3
8299 #define UART_C3_TXINV_MASK 0x10u
8300 #define UART_C3_TXINV_SHIFT 4
8301 #define UART_C3_TXDIR_MASK 0x20u
8302 #define UART_C3_TXDIR_SHIFT 5
8303 #define UART_C3_T8_MASK 0x40u
8304 #define UART_C3_T8_SHIFT 6
8305 #define UART_C3_R8_MASK 0x80u
8306 #define UART_C3_R8_SHIFT 7
8307 /* D Bit Fields */
8308 #define UART_D_RT_MASK 0xFFu
8309 #define UART_D_RT_SHIFT 0
8310 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
8311 /* MA1 Bit Fields */
8312 #define UART_MA1_MA_MASK 0xFFu
8313 #define UART_MA1_MA_SHIFT 0
8314 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
8315 /* MA2 Bit Fields */
8316 #define UART_MA2_MA_MASK 0xFFu
8317 #define UART_MA2_MA_SHIFT 0
8318 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
8319 /* C4 Bit Fields */
8320 #define UART_C4_BRFA_MASK 0x1Fu
8321 #define UART_C4_BRFA_SHIFT 0
8322 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
8323 #define UART_C4_M10_MASK 0x20u
8324 #define UART_C4_M10_SHIFT 5
8325 #define UART_C4_MAEN2_MASK 0x40u
8326 #define UART_C4_MAEN2_SHIFT 6
8327 #define UART_C4_MAEN1_MASK 0x80u
8328 #define UART_C4_MAEN1_SHIFT 7
8329 /* C5 Bit Fields */
8330 #define UART_C5_RDMAS_MASK 0x20u
8331 #define UART_C5_RDMAS_SHIFT 5
8332 #define UART_C5_TDMAS_MASK 0x80u
8333 #define UART_C5_TDMAS_SHIFT 7
8334 /* ED Bit Fields */
8335 #define UART_ED_PARITYE_MASK 0x40u
8336 #define UART_ED_PARITYE_SHIFT 6
8337 #define UART_ED_NOISY_MASK 0x80u
8338 #define UART_ED_NOISY_SHIFT 7
8339 /* MODEM Bit Fields */
8340 #define UART_MODEM_TXCTSE_MASK 0x1u
8341 #define UART_MODEM_TXCTSE_SHIFT 0
8342 #define UART_MODEM_TXRTSE_MASK 0x2u
8343 #define UART_MODEM_TXRTSE_SHIFT 1
8344 #define UART_MODEM_TXRTSPOL_MASK 0x4u
8345 #define UART_MODEM_TXRTSPOL_SHIFT 2
8346 #define UART_MODEM_RXRTSE_MASK 0x8u
8347 #define UART_MODEM_RXRTSE_SHIFT 3
8348 /* IR Bit Fields */
8349 #define UART_IR_TNP_MASK 0x3u
8350 #define UART_IR_TNP_SHIFT 0
8351 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
8352 #define UART_IR_IREN_MASK 0x4u
8353 #define UART_IR_IREN_SHIFT 2
8354 /* PFIFO Bit Fields */
8355 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
8356 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
8357 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
8358 #define UART_PFIFO_RXFE_MASK 0x8u
8359 #define UART_PFIFO_RXFE_SHIFT 3
8360 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
8361 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
8362 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
8363 #define UART_PFIFO_TXFE_MASK 0x80u
8364 #define UART_PFIFO_TXFE_SHIFT 7
8365 /* CFIFO Bit Fields */
8366 #define UART_CFIFO_RXUFE_MASK 0x1u
8367 #define UART_CFIFO_RXUFE_SHIFT 0
8368 #define UART_CFIFO_TXOFE_MASK 0x2u
8369 #define UART_CFIFO_TXOFE_SHIFT 1
8370 #define UART_CFIFO_RXFLUSH_MASK 0x40u
8371 #define UART_CFIFO_RXFLUSH_SHIFT 6
8372 #define UART_CFIFO_TXFLUSH_MASK 0x80u
8373 #define UART_CFIFO_TXFLUSH_SHIFT 7
8374 /* SFIFO Bit Fields */
8375 #define UART_SFIFO_RXUF_MASK 0x1u
8376 #define UART_SFIFO_RXUF_SHIFT 0
8377 #define UART_SFIFO_TXOF_MASK 0x2u
8378 #define UART_SFIFO_TXOF_SHIFT 1
8379 #define UART_SFIFO_RXEMPT_MASK 0x40u
8380 #define UART_SFIFO_RXEMPT_SHIFT 6
8381 #define UART_SFIFO_TXEMPT_MASK 0x80u
8382 #define UART_SFIFO_TXEMPT_SHIFT 7
8383 /* TWFIFO Bit Fields */
8384 #define UART_TWFIFO_TXWATER_MASK 0xFFu
8385 #define UART_TWFIFO_TXWATER_SHIFT 0
8386 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
8387 /* TCFIFO Bit Fields */
8388 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
8389 #define UART_TCFIFO_TXCOUNT_SHIFT 0
8390 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
8391 /* RWFIFO Bit Fields */
8392 #define UART_RWFIFO_RXWATER_MASK 0xFFu
8393 #define UART_RWFIFO_RXWATER_SHIFT 0
8394 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
8395 /* RCFIFO Bit Fields */
8396 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
8397 #define UART_RCFIFO_RXCOUNT_SHIFT 0
8398 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
8399 /* C7816 Bit Fields */
8400 #define UART_C7816_ISO_7816E_MASK 0x1u
8401 #define UART_C7816_ISO_7816E_SHIFT 0
8402 #define UART_C7816_TTYPE_MASK 0x2u
8403 #define UART_C7816_TTYPE_SHIFT 1
8404 #define UART_C7816_INIT_MASK 0x4u
8405 #define UART_C7816_INIT_SHIFT 2
8406 #define UART_C7816_ANACK_MASK 0x8u
8407 #define UART_C7816_ANACK_SHIFT 3
8408 #define UART_C7816_ONACK_MASK 0x10u
8409 #define UART_C7816_ONACK_SHIFT 4
8410 /* IE7816 Bit Fields */
8411 #define UART_IE7816_RXTE_MASK 0x1u
8412 #define UART_IE7816_RXTE_SHIFT 0
8413 #define UART_IE7816_TXTE_MASK 0x2u
8414 #define UART_IE7816_TXTE_SHIFT 1
8415 #define UART_IE7816_GTVE_MASK 0x4u
8416 #define UART_IE7816_GTVE_SHIFT 2
8417 #define UART_IE7816_INITDE_MASK 0x10u
8418 #define UART_IE7816_INITDE_SHIFT 4
8419 #define UART_IE7816_BWTE_MASK 0x20u
8420 #define UART_IE7816_BWTE_SHIFT 5
8421 #define UART_IE7816_CWTE_MASK 0x40u
8422 #define UART_IE7816_CWTE_SHIFT 6
8423 #define UART_IE7816_WTE_MASK 0x80u
8424 #define UART_IE7816_WTE_SHIFT 7
8425 /* IS7816 Bit Fields */
8426 #define UART_IS7816_RXT_MASK 0x1u
8427 #define UART_IS7816_RXT_SHIFT 0
8428 #define UART_IS7816_TXT_MASK 0x2u
8429 #define UART_IS7816_TXT_SHIFT 1
8430 #define UART_IS7816_GTV_MASK 0x4u
8431 #define UART_IS7816_GTV_SHIFT 2
8432 #define UART_IS7816_INITD_MASK 0x10u
8433 #define UART_IS7816_INITD_SHIFT 4
8434 #define UART_IS7816_BWT_MASK 0x20u
8435 #define UART_IS7816_BWT_SHIFT 5
8436 #define UART_IS7816_CWT_MASK 0x40u
8437 #define UART_IS7816_CWT_SHIFT 6
8438 #define UART_IS7816_WT_MASK 0x80u
8439 #define UART_IS7816_WT_SHIFT 7
8440 /* WP7816_T_TYPE0 Bit Fields */
8441 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
8442 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
8443 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
8444 /* WP7816_T_TYPE1 Bit Fields */
8445 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
8446 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
8447 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
8448 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
8449 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
8450 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
8451 /* WN7816 Bit Fields */
8452 #define UART_WN7816_GTN_MASK 0xFFu
8453 #define UART_WN7816_GTN_SHIFT 0
8454 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
8455 /* WF7816 Bit Fields */
8456 #define UART_WF7816_GTFD_MASK 0xFFu
8457 #define UART_WF7816_GTFD_SHIFT 0
8458 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
8459 /* ET7816 Bit Fields */
8460 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
8461 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
8462 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
8463 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
8464 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
8465 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
8466 /* TL7816 Bit Fields */
8467 #define UART_TL7816_TLEN_MASK 0xFFu
8468 #define UART_TL7816_TLEN_SHIFT 0
8469 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
8470 
8471 /**
8472  * @}
8473  */ /* end of group UART_Register_Masks */
8474 
8475 
8476 /* UART - Peripheral instance base addresses */
8477 /** Peripheral UART0 base address */
8478 #define UART0_BASE (0x4006A000u)
8479 /** Peripheral UART0 base pointer */
8480 #define UART0 ((UART_Type *)UART0_BASE)
8481 /** Peripheral UART1 base address */
8482 #define UART1_BASE (0x4006B000u)
8483 /** Peripheral UART1 base pointer */
8484 #define UART1 ((UART_Type *)UART1_BASE)
8485 /** Peripheral UART2 base address */
8486 #define UART2_BASE (0x4006C000u)
8487 /** Peripheral UART2 base pointer */
8488 #define UART2 ((UART_Type *)UART2_BASE)
8489 /** Peripheral UART3 base address */
8490 #define UART3_BASE (0x4006D000u)
8491 /** Peripheral UART3 base pointer */
8492 #define UART3 ((UART_Type *)UART3_BASE)
8493 /** Peripheral UART4 base address */
8494 #define UART4_BASE (0x400EA000u)
8495 /** Peripheral UART4 base pointer */
8496 #define UART4 ((UART_Type *)UART4_BASE)
8497 /** Peripheral UART5 base address */
8498 #define UART5_BASE (0x400EB000u)
8499 /** Peripheral UART5 base pointer */
8500 #define UART5 ((UART_Type *)UART5_BASE)
8501 
8502 /**
8503  * @}
8504  */ /* end of group UART_Peripheral_Access_Layer */
8505 
8506 
8507 /* ----------------------------------------------------------------------------
8508  -- USB Peripheral Access Layer
8509  ---------------------------------------------------------------------------- */
8510 
8511 /**
8512  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
8513  * @{
8514  */
8515 
8516 /** USB - Register Layout Typedef */
8517 typedef struct {
8518  __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
8519  uint8_t RESERVED_0[3];
8520  __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
8521  uint8_t RESERVED_1[3];
8522  __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
8523  uint8_t RESERVED_2[3];
8524  __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
8525  uint8_t RESERVED_3[3];
8526  __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
8527  uint8_t RESERVED_4[3];
8528  __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
8529  uint8_t RESERVED_5[3];
8530  __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
8531  uint8_t RESERVED_6[3];
8532  __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
8533  uint8_t RESERVED_7[99];
8534  __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
8535  uint8_t RESERVED_8[3];
8536  __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
8537  uint8_t RESERVED_9[3];
8538  __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
8539  uint8_t RESERVED_10[3];
8540  __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
8541  uint8_t RESERVED_11[3];
8542  __I uint8_t STAT; /**< Status Register, offset: 0x90 */
8543  uint8_t RESERVED_12[3];
8544  __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
8545  uint8_t RESERVED_13[3];
8546  __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
8547  uint8_t RESERVED_14[3];
8548  __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
8549  uint8_t RESERVED_15[3];
8550  __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
8551  uint8_t RESERVED_16[3];
8552  __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
8553  uint8_t RESERVED_17[3];
8554  __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
8555  uint8_t RESERVED_18[3];
8556  __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
8557  uint8_t RESERVED_19[3];
8558  __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
8559  uint8_t RESERVED_20[3];
8560  __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
8561  uint8_t RESERVED_21[11];
8562  struct { /* offset: 0xC0, array step: 0x4 */
8563  __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
8564  uint8_t RESERVED_0[3];
8565  } ENDPOINT[16];
8566  __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
8567  uint8_t RESERVED_22[3];
8568  __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
8569  uint8_t RESERVED_23[3];
8570  __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
8571  uint8_t RESERVED_24[3];
8572  __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
8573 } USB_Type;
8574 
8575 /* ----------------------------------------------------------------------------
8576  -- USB Register Masks
8577  ---------------------------------------------------------------------------- */
8578 
8579 /**
8580  * @addtogroup USB_Register_Masks USB Register Masks
8581  * @{
8582  */
8583 
8584 /* PERID Bit Fields */
8585 #define USB_PERID_ID_MASK 0x3Fu
8586 #define USB_PERID_ID_SHIFT 0
8587 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
8588 /* IDCOMP Bit Fields */
8589 #define USB_IDCOMP_NID_MASK 0x3Fu
8590 #define USB_IDCOMP_NID_SHIFT 0
8591 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
8592 /* REV Bit Fields */
8593 #define USB_REV_REV_MASK 0xFFu
8594 #define USB_REV_REV_SHIFT 0
8595 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
8596 /* ADDINFO Bit Fields */
8597 #define USB_ADDINFO_IEHOST_MASK 0x1u
8598 #define USB_ADDINFO_IEHOST_SHIFT 0
8599 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
8600 #define USB_ADDINFO_IRQNUM_SHIFT 3
8601 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
8602 /* OTGISTAT Bit Fields */
8603 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
8604 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
8605 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
8606 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
8607 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
8608 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
8609 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
8610 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
8611 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
8612 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
8613 #define USB_OTGISTAT_IDCHG_MASK 0x80u
8614 #define USB_OTGISTAT_IDCHG_SHIFT 7
8615 /* OTGICR Bit Fields */
8616 #define USB_OTGICR_AVBUSEN_MASK 0x1u
8617 #define USB_OTGICR_AVBUSEN_SHIFT 0
8618 #define USB_OTGICR_BSESSEN_MASK 0x4u
8619 #define USB_OTGICR_BSESSEN_SHIFT 2
8620 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
8621 #define USB_OTGICR_SESSVLDEN_SHIFT 3
8622 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
8623 #define USB_OTGICR_LINESTATEEN_SHIFT 5
8624 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
8625 #define USB_OTGICR_ONEMSECEN_SHIFT 6
8626 #define USB_OTGICR_IDEN_MASK 0x80u
8627 #define USB_OTGICR_IDEN_SHIFT 7
8628 /* OTGSTAT Bit Fields */
8629 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
8630 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
8631 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
8632 #define USB_OTGSTAT_BSESSEND_SHIFT 2
8633 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
8634 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
8635 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
8636 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
8637 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
8638 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
8639 #define USB_OTGSTAT_ID_MASK 0x80u
8640 #define USB_OTGSTAT_ID_SHIFT 7
8641 /* OTGCTL Bit Fields */
8642 #define USB_OTGCTL_OTGEN_MASK 0x4u
8643 #define USB_OTGCTL_OTGEN_SHIFT 2
8644 #define USB_OTGCTL_DMLOW_MASK 0x10u
8645 #define USB_OTGCTL_DMLOW_SHIFT 4
8646 #define USB_OTGCTL_DPLOW_MASK 0x20u
8647 #define USB_OTGCTL_DPLOW_SHIFT 5
8648 #define USB_OTGCTL_DPHIGH_MASK 0x80u
8649 #define USB_OTGCTL_DPHIGH_SHIFT 7
8650 /* ISTAT Bit Fields */
8651 #define USB_ISTAT_USBRST_MASK 0x1u
8652 #define USB_ISTAT_USBRST_SHIFT 0
8653 #define USB_ISTAT_ERROR_MASK 0x2u
8654 #define USB_ISTAT_ERROR_SHIFT 1
8655 #define USB_ISTAT_SOFTOK_MASK 0x4u
8656 #define USB_ISTAT_SOFTOK_SHIFT 2
8657 #define USB_ISTAT_TOKDNE_MASK 0x8u
8658 #define USB_ISTAT_TOKDNE_SHIFT 3
8659 #define USB_ISTAT_SLEEP_MASK 0x10u
8660 #define USB_ISTAT_SLEEP_SHIFT 4
8661 #define USB_ISTAT_RESUME_MASK 0x20u
8662 #define USB_ISTAT_RESUME_SHIFT 5
8663 #define USB_ISTAT_ATTACH_MASK 0x40u
8664 #define USB_ISTAT_ATTACH_SHIFT 6
8665 #define USB_ISTAT_STALL_MASK 0x80u
8666 #define USB_ISTAT_STALL_SHIFT 7
8667 /* INTEN Bit Fields */
8668 #define USB_INTEN_USBRSTEN_MASK 0x1u
8669 #define USB_INTEN_USBRSTEN_SHIFT 0
8670 #define USB_INTEN_ERROREN_MASK 0x2u
8671 #define USB_INTEN_ERROREN_SHIFT 1
8672 #define USB_INTEN_SOFTOKEN_MASK 0x4u
8673 #define USB_INTEN_SOFTOKEN_SHIFT 2
8674 #define USB_INTEN_TOKDNEEN_MASK 0x8u
8675 #define USB_INTEN_TOKDNEEN_SHIFT 3
8676 #define USB_INTEN_SLEEPEN_MASK 0x10u
8677 #define USB_INTEN_SLEEPEN_SHIFT 4
8678 #define USB_INTEN_RESUMEEN_MASK 0x20u
8679 #define USB_INTEN_RESUMEEN_SHIFT 5
8680 #define USB_INTEN_ATTACHEN_MASK 0x40u
8681 #define USB_INTEN_ATTACHEN_SHIFT 6
8682 #define USB_INTEN_STALLEN_MASK 0x80u
8683 #define USB_INTEN_STALLEN_SHIFT 7
8684 /* ERRSTAT Bit Fields */
8685 #define USB_ERRSTAT_PIDERR_MASK 0x1u
8686 #define USB_ERRSTAT_PIDERR_SHIFT 0
8687 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
8688 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
8689 #define USB_ERRSTAT_CRC16_MASK 0x4u
8690 #define USB_ERRSTAT_CRC16_SHIFT 2
8691 #define USB_ERRSTAT_DFN8_MASK 0x8u
8692 #define USB_ERRSTAT_DFN8_SHIFT 3
8693 #define USB_ERRSTAT_BTOERR_MASK 0x10u
8694 #define USB_ERRSTAT_BTOERR_SHIFT 4
8695 #define USB_ERRSTAT_DMAERR_MASK 0x20u
8696 #define USB_ERRSTAT_DMAERR_SHIFT 5
8697 #define USB_ERRSTAT_BTSERR_MASK 0x80u
8698 #define USB_ERRSTAT_BTSERR_SHIFT 7
8699 /* ERREN Bit Fields */
8700 #define USB_ERREN_PIDERREN_MASK 0x1u
8701 #define USB_ERREN_PIDERREN_SHIFT 0
8702 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
8703 #define USB_ERREN_CRC5EOFEN_SHIFT 1
8704 #define USB_ERREN_CRC16EN_MASK 0x4u
8705 #define USB_ERREN_CRC16EN_SHIFT 2
8706 #define USB_ERREN_DFN8EN_MASK 0x8u
8707 #define USB_ERREN_DFN8EN_SHIFT 3
8708 #define USB_ERREN_BTOERREN_MASK 0x10u
8709 #define USB_ERREN_BTOERREN_SHIFT 4
8710 #define USB_ERREN_DMAERREN_MASK 0x20u
8711 #define USB_ERREN_DMAERREN_SHIFT 5
8712 #define USB_ERREN_BTSERREN_MASK 0x80u
8713 #define USB_ERREN_BTSERREN_SHIFT 7
8714 /* STAT Bit Fields */
8715 #define USB_STAT_ODD_MASK 0x4u
8716 #define USB_STAT_ODD_SHIFT 2
8717 #define USB_STAT_TX_MASK 0x8u
8718 #define USB_STAT_TX_SHIFT 3
8719 #define USB_STAT_ENDP_MASK 0xF0u
8720 #define USB_STAT_ENDP_SHIFT 4
8721 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
8722 /* CTL Bit Fields */
8723 #define USB_CTL_USBENSOFEN_MASK 0x1u
8724 #define USB_CTL_USBENSOFEN_SHIFT 0
8725 #define USB_CTL_ODDRST_MASK 0x2u
8726 #define USB_CTL_ODDRST_SHIFT 1
8727 #define USB_CTL_RESUME_MASK 0x4u
8728 #define USB_CTL_RESUME_SHIFT 2
8729 #define USB_CTL_HOSTMODEEN_MASK 0x8u
8730 #define USB_CTL_HOSTMODEEN_SHIFT 3
8731 #define USB_CTL_RESET_MASK 0x10u
8732 #define USB_CTL_RESET_SHIFT 4
8733 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
8734 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
8735 #define USB_CTL_SE0_MASK 0x40u
8736 #define USB_CTL_SE0_SHIFT 6
8737 #define USB_CTL_JSTATE_MASK 0x80u
8738 #define USB_CTL_JSTATE_SHIFT 7
8739 /* ADDR Bit Fields */
8740 #define USB_ADDR_ADDR_MASK 0x7Fu
8741 #define USB_ADDR_ADDR_SHIFT 0
8742 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
8743 #define USB_ADDR_LSEN_MASK 0x80u
8744 #define USB_ADDR_LSEN_SHIFT 7
8745 /* BDTPAGE1 Bit Fields */
8746 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
8747 #define USB_BDTPAGE1_BDTBA_SHIFT 1
8748 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
8749 /* FRMNUML Bit Fields */
8750 #define USB_FRMNUML_FRM_MASK 0xFFu
8751 #define USB_FRMNUML_FRM_SHIFT 0
8752 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
8753 /* FRMNUMH Bit Fields */
8754 #define USB_FRMNUMH_FRM_MASK 0x7u
8755 #define USB_FRMNUMH_FRM_SHIFT 0
8756 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
8757 /* TOKEN Bit Fields */
8758 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
8759 #define USB_TOKEN_TOKENENDPT_SHIFT 0
8760 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
8761 #define USB_TOKEN_TOKENPID_MASK 0xF0u
8762 #define USB_TOKEN_TOKENPID_SHIFT 4
8763 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
8764 /* SOFTHLD Bit Fields */
8765 #define USB_SOFTHLD_CNT_MASK 0xFFu
8766 #define USB_SOFTHLD_CNT_SHIFT 0
8767 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
8768 /* BDTPAGE2 Bit Fields */
8769 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
8770 #define USB_BDTPAGE2_BDTBA_SHIFT 0
8771 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
8772 /* BDTPAGE3 Bit Fields */
8773 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
8774 #define USB_BDTPAGE3_BDTBA_SHIFT 0
8775 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
8776 /* ENDPT Bit Fields */
8777 #define USB_ENDPT_EPHSHK_MASK 0x1u
8778 #define USB_ENDPT_EPHSHK_SHIFT 0
8779 #define USB_ENDPT_EPSTALL_MASK 0x2u
8780 #define USB_ENDPT_EPSTALL_SHIFT 1
8781 #define USB_ENDPT_EPTXEN_MASK 0x4u
8782 #define USB_ENDPT_EPTXEN_SHIFT 2
8783 #define USB_ENDPT_EPRXEN_MASK 0x8u
8784 #define USB_ENDPT_EPRXEN_SHIFT 3
8785 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
8786 #define USB_ENDPT_EPCTLDIS_SHIFT 4
8787 #define USB_ENDPT_RETRYDIS_MASK 0x40u
8788 #define USB_ENDPT_RETRYDIS_SHIFT 6
8789 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
8790 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
8791 /* USBCTRL Bit Fields */
8792 #define USB_USBCTRL_PDE_MASK 0x40u
8793 #define USB_USBCTRL_PDE_SHIFT 6
8794 #define USB_USBCTRL_SUSP_MASK 0x80u
8795 #define USB_USBCTRL_SUSP_SHIFT 7
8796 /* OBSERVE Bit Fields */
8797 #define USB_OBSERVE_DMPD_MASK 0x10u
8798 #define USB_OBSERVE_DMPD_SHIFT 4
8799 #define USB_OBSERVE_DPPD_MASK 0x40u
8800 #define USB_OBSERVE_DPPD_SHIFT 6
8801 #define USB_OBSERVE_DPPU_MASK 0x80u
8802 #define USB_OBSERVE_DPPU_SHIFT 7
8803 /* CONTROL Bit Fields */
8804 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
8805 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
8806 /* USBTRC0 Bit Fields */
8807 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
8808 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
8809 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
8810 #define USB_USBTRC0_SYNC_DET_SHIFT 1
8811 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
8812 #define USB_USBTRC0_USBRESMEN_SHIFT 5
8813 #define USB_USBTRC0_USBRESET_MASK 0x80u
8814 #define USB_USBTRC0_USBRESET_SHIFT 7
8815 
8816 /**
8817  * @}
8818  */ /* end of group USB_Register_Masks */
8819 
8820 
8821 /* USB - Peripheral instance base addresses */
8822 /** Peripheral USB0 base address */
8823 #define USB0_BASE (0x40072000u)
8824 /** Peripheral USB0 base pointer */
8825 #define USB0 ((USB_Type *)USB0_BASE)
8826 
8827 /**
8828  * @}
8829  */ /* end of group USB_Peripheral_Access_Layer */
8830 
8831 
8832 /* ----------------------------------------------------------------------------
8833  -- USBDCD Peripheral Access Layer
8834  ---------------------------------------------------------------------------- */
8835 
8836 /**
8837  * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
8838  * @{
8839  */
8840 
8841 /** USBDCD - Register Layout Typedef */
8842 typedef struct {
8843  __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
8844  __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
8845  __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
8846  uint8_t RESERVED_0[4];
8847  __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
8848  __IO uint32_t TIMER1; /**< , offset: 0x14 */
8849  __IO uint32_t TIMER2; /**< , offset: 0x18 */
8850 } USBDCD_Type;
8851 
8852 /* ----------------------------------------------------------------------------
8853  -- USBDCD Register Masks
8854  ---------------------------------------------------------------------------- */
8855 
8856 /**
8857  * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
8858  * @{
8859  */
8860 
8861 /* CONTROL Bit Fields */
8862 #define USBDCD_CONTROL_IACK_MASK 0x1u
8863 #define USBDCD_CONTROL_IACK_SHIFT 0
8864 #define USBDCD_CONTROL_IF_MASK 0x100u
8865 #define USBDCD_CONTROL_IF_SHIFT 8
8866 #define USBDCD_CONTROL_IE_MASK 0x10000u
8867 #define USBDCD_CONTROL_IE_SHIFT 16
8868 #define USBDCD_CONTROL_START_MASK 0x1000000u
8869 #define USBDCD_CONTROL_START_SHIFT 24
8870 #define USBDCD_CONTROL_SR_MASK 0x2000000u
8871 #define USBDCD_CONTROL_SR_SHIFT 25
8872 /* CLOCK Bit Fields */
8873 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
8874 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
8875 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
8876 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
8877 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
8878 /* STATUS Bit Fields */
8879 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
8880 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
8881 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
8882 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
8883 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
8884 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
8885 #define USBDCD_STATUS_ERR_MASK 0x100000u
8886 #define USBDCD_STATUS_ERR_SHIFT 20
8887 #define USBDCD_STATUS_TO_MASK 0x200000u
8888 #define USBDCD_STATUS_TO_SHIFT 21
8889 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
8890 #define USBDCD_STATUS_ACTIVE_SHIFT 22
8891 /* TIMER0 Bit Fields */
8892 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
8893 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
8894 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
8895 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
8896 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
8897 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
8898 /* TIMER1 Bit Fields */
8899 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
8900 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
8901 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
8902 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
8903 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
8904 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
8905 /* TIMER2 Bit Fields */
8906 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
8907 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
8908 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
8909 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
8910 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
8911 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
8912 
8913 /**
8914  * @}
8915  */ /* end of group USBDCD_Register_Masks */
8916 
8917 
8918 /* USBDCD - Peripheral instance base addresses */
8919 /** Peripheral USBDCD base address */
8920 #define USBDCD_BASE (0x40035000u)
8921 /** Peripheral USBDCD base pointer */
8922 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
8923 
8924 /**
8925  * @}
8926  */ /* end of group USBDCD_Peripheral_Access_Layer */
8927 
8928 
8929 /* ----------------------------------------------------------------------------
8930  -- VREF Peripheral Access Layer
8931  ---------------------------------------------------------------------------- */
8932 
8933 /**
8934  * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
8935  * @{
8936  */
8937 
8938 /** VREF - Register Layout Typedef */
8939 typedef struct {
8940  __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
8941  __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
8942 } VREF_Type;
8943 
8944 /* ----------------------------------------------------------------------------
8945  -- VREF Register Masks
8946  ---------------------------------------------------------------------------- */
8947 
8948 /**
8949  * @addtogroup VREF_Register_Masks VREF Register Masks
8950  * @{
8951  */
8952 
8953 /* TRM Bit Fields */
8954 #define VREF_TRM_TRIM_MASK 0x3Fu
8955 #define VREF_TRM_TRIM_SHIFT 0
8956 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
8957 /* SC Bit Fields */
8958 #define VREF_SC_MODE_LV_MASK 0x3u
8959 #define VREF_SC_MODE_LV_SHIFT 0
8960 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
8961 #define VREF_SC_VREFST_MASK 0x4u
8962 #define VREF_SC_VREFST_SHIFT 2
8963 #define VREF_SC_REGEN_MASK 0x40u
8964 #define VREF_SC_REGEN_SHIFT 6
8965 #define VREF_SC_VREFEN_MASK 0x80u
8966 #define VREF_SC_VREFEN_SHIFT 7
8967 
8968 /**
8969  * @}
8970  */ /* end of group VREF_Register_Masks */
8971 
8972 
8973 /* VREF - Peripheral instance base addresses */
8974 /** Peripheral VREF base address */
8975 #define VREF_BASE (0x40074000u)
8976 /** Peripheral VREF base pointer */
8977 #define VREF ((VREF_Type *)VREF_BASE)
8978 
8979 /**
8980  * @}
8981  */ /* end of group VREF_Peripheral_Access_Layer */
8982 
8983 
8984 /* ----------------------------------------------------------------------------
8985  -- WDOG Peripheral Access Layer
8986  ---------------------------------------------------------------------------- */
8987 
8988 /**
8989  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
8990  * @{
8991  */
8992 
8993 /** WDOG - Register Layout Typedef */
8994 typedef struct {
8995  __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
8996  __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
8997  __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
8998  __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
8999  __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
9000  __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
9001  __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
9002  __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
9003  __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
9004  __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
9005  __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
9006  __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
9007 } WDOG_Type;
9008 
9009 /* ----------------------------------------------------------------------------
9010  -- WDOG Register Masks
9011  ---------------------------------------------------------------------------- */
9012 
9013 /**
9014  * @addtogroup WDOG_Register_Masks WDOG Register Masks
9015  * @{
9016  */
9017 
9018 /* STCTRLH Bit Fields */
9019 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
9020 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
9021 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
9022 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
9023 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
9024 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
9025 #define WDOG_STCTRLH_WINEN_MASK 0x8u
9026 #define WDOG_STCTRLH_WINEN_SHIFT 3
9027 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
9028 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
9029 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
9030 #define WDOG_STCTRLH_DBGEN_SHIFT 5
9031 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
9032 #define WDOG_STCTRLH_STOPEN_SHIFT 6
9033 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
9034 #define WDOG_STCTRLH_WAITEN_SHIFT 7
9035 #define WDOG_STCTRLH_STNDBYEN_MASK 0x100u
9036 #define WDOG_STCTRLH_STNDBYEN_SHIFT 8
9037 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
9038 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
9039 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
9040 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
9041 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
9042 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
9043 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
9044 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
9045 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
9046 /* STCTRLL Bit Fields */
9047 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
9048 #define WDOG_STCTRLL_INTFLG_SHIFT 15
9049 /* TOVALH Bit Fields */
9050 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
9051 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
9052 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
9053 /* TOVALL Bit Fields */
9054 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
9055 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
9056 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
9057 /* WINH Bit Fields */
9058 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
9059 #define WDOG_WINH_WINHIGH_SHIFT 0
9060 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
9061 /* WINL Bit Fields */
9062 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
9063 #define WDOG_WINL_WINLOW_SHIFT 0
9064 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
9065 /* REFRESH Bit Fields */
9066 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
9067 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
9068 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
9069 /* UNLOCK Bit Fields */
9070 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
9071 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
9072 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
9073 /* TMROUTH Bit Fields */
9074 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
9075 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
9076 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
9077 /* TMROUTL Bit Fields */
9078 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
9079 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
9080 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
9081 /* RSTCNT Bit Fields */
9082 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
9083 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
9084 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
9085 /* PRESC Bit Fields */
9086 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
9087 #define WDOG_PRESC_PRESCVAL_SHIFT 8
9088 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
9089 
9090 /**
9091  * @}
9092  */ /* end of group WDOG_Register_Masks */
9093 
9094 
9095 /* WDOG - Peripheral instance base addresses */
9096 /** Peripheral WDOG base address */
9097 #define WDOG_BASE (0x40052000u)
9098 /** Peripheral WDOG base pointer */
9099 #define WDOG ((WDOG_Type *)WDOG_BASE)
9100 
9101 /**
9102  * @}
9103  */ /* end of group WDOG_Peripheral_Access_Layer */
9104 
9105 
9106 /*
9107 ** End of section using anonymous unions
9108 */
9109 
9110 #if defined(__ARMCC_VERSION)
9111  #pragma pop
9112 #elif defined(__CWCC__)
9113  #pragma pop
9114 #elif defined(__GNUC__)
9115  /* leave anonymous unions enabled */
9116 #elif defined(__IAR_SYSTEMS_ICC__)
9117  #pragma language=default
9118 #else
9119  #error Not supported compiler type
9120 #endif
9121 
9122 /**
9123  * @}
9124  */ /* end of group Peripheral_access_layer */
9125 
9126 
9127 /* ----------------------------------------------------------------------------
9128  -- Backward Compatibility
9129  ---------------------------------------------------------------------------- */
9130 
9131 /**
9132  * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
9133  * @{
9134  */
9135 
9136 #define FB_CSCR_EXALE_MASK FB_CSCR_EXTS_MASK
9137 #define FB_CSCR_EXALE_SHIFT FB_CSCR_EXTS_SHIFT
9138 #define RTC_CCR_CONFIG_MASK This_symb_has_been_deprecated
9139 #define RTC_CCR_CONFIG_SHIFT This_symb_has_been_deprecated
9140 #define RTC_CCR_CONFIG This_symb_has_been_deprecated
9141 #define RTC_WAR_CCRW_MASK This_symb_has_been_deprecated
9142 #define RTC_WAR_CCRW_SHIFT This_symb_has_been_deprecated
9143 #define RTC_RAR_CCRR_MASK This_symb_has_been_deprecated
9144 #define RTC_RAR_CCRR_SHIFT This_symb_has_been_deprecated
9145 #define SIM_FCFG1_FSIZE_MASK This_symb_has_been_deprecated
9146 #define SIM_FCFG1_FSIZE_SHIFT This_symb_has_been_deprecated
9147 #define I2S_CR_SSIEN_MASK I2S_CR_I2SEN_MASK
9148 #define I2S_CR_SSIEN_SHIFT I2S_CR_I2SEN_SHIFT
9149 #define SDHC_VENDOR_VOLTSEL_MASK This_symb_has_been_deprecated
9150 #define SDHC_VENDOR_VOLTSEL_SHIFT This_symb_has_been_deprecated
9151 #define INT_Reserved4 INT_Mem_Manage_Fault
9152 #define TSI_CNTR1_CNTN_MASK TSI_CNTR1_CTN1_MASK
9153 #define TSI_CNTR1_CNTN_SHIFT TSI_CNTR1_CTN1_SHIFT
9154 #define TSI_CNTR1_CNTN(x) TSI_CNTR1_CTN1(x)
9155 #define TSI_CNTR1_CNTN1_MASK TSI_CNTR1_CTN_MASK
9156 #define TSI_CNTR1_CNTN1_SHIFT TSI_CNTR1_CTN_SHIFT
9157 #define TSI_CNTR1_CNTN1(x) TSI_CNTR1_CTN(x)
9158 #define TSI_CNTR3_CNTN_MASK TSI_CNTR3_CTN1_MASK
9159 #define TSI_CNTR3_CNTN_SHIFT TSI_CNTR3_CTN1_SHIFT
9160 #define TSI_CNTR3_CNTN(x) TSI_CNTR3_CTN1(x)
9161 #define TSI_CNTR3_CNTN1_MASK TSI_CNTR3_CTN_MASK
9162 #define TSI_CNTR3_CNTN1_SHIFT TSI_CNTR3_CTN_SHIFT
9163 #define TSI_CNTR3_CNTN1(x) TSI_CNTR3_CTN(x)
9164 #define TSI_CNTR5_CNTN_MASK TSI_CNTR5_CTN1_MASK
9165 #define TSI_CNTR5_CNTN_SHIFT TSI_CNTR5_CTN1_SHIFT
9166 #define TSI_CNTR5_CNTN(x) TSI_CNTR5_CTN1(x)
9167 #define TSI_CNTR5_CNTN1_MASK TSI_CNTR5_CTN_MASK
9168 #define TSI_CNTR5_CNTN1_SHIFT TSI_CNTR5_CTN_SHIFT
9169 #define TSI_CNTR5_CNTN1(x) TSI_CNTR5_CTN(x)
9170 #define TSI_CNTR7_CNTN_MASK TSI_CNTR7_CTN1_MASK
9171 #define TSI_CNTR7_CNTN_SHIFT TSI_CNTR7_CTN1_SHIFT
9172 #define TSI_CNTR7_CNTN(x) TSI_CNTR7_CTN1(x)
9173 #define TSI_CNTR7_CNTN1_MASK TSI_CNTR7_CTN_MASK
9174 #define TSI_CNTR7_CNTN1_SHIFT TSI_CNTR7_CTN_SHIFT
9175 #define TSI_CNTR7_CNTN1(x) TSI_CNTR7_CTN(x)
9176 #define TSI_CNTR9_CNTN_MASK TSI_CNTR9_CTN1_MASK
9177 #define TSI_CNTR9_CNTN_SHIFT TSI_CNTR9_CTN1_SHIFT
9178 #define TSI_CNTR9_CNTN(x) TSI_CNTR9_CTN1(x)
9179 #define TSI_CNTR9_CNTN1_MASK TSI_CNTR9_CTN_MASK
9180 #define TSI_CNTR9_CNTN1_SHIFT TSI_CNTR9_CTN_SHIFT
9181 #define TSI_CNTR9_CNTN1(x) TSI_CNTR9_CTN(x)
9182 #define TSI_CNTR11_CNTN_MASK TSI_CNTR11_CTN1_MASK
9183 #define TSI_CNTR11_CNTN_SHIFT TSI_CNTR11_CTN1_SHIFT
9184 #define TSI_CNTR11_CNTN(x) TSI_CNTR11_CTN1(x)
9185 #define TSI_CNTR11_CNTN1_MASK TSI_CNTR11_CTN_MASK
9186 #define TSI_CNTR11_CNTN1_SHIFT TSI_CNTR11_CTN_SHIFT
9187 #define TSI_CNTR11_CNTN1(x) TSI_CNTR11_CTN(x)
9188 #define TSI_CNTR13_CNTN_MASK TSI_CNTR13_CTN1_MASK
9189 #define TSI_CNTR13_CNTN_SHIFT TSI_CNTR13_CTN1_SHIFT
9190 #define TSI_CNTR13_CNTN(x) TSI_CNTR13_CTN1(x)
9191 #define TSI_CNTR13_CNTN1_MASK TSI_CNTR13_CTN_MASK
9192 #define TSI_CNTR13_CNTN1_SHIFT TSI_CNTR13_CTN_SHIFT
9193 #define TSI_CNTR13_CNTN1(x) TSI_CNTR13_CTN(x)
9194 #define TSI_CNTR15_CNTN_MASK TSI_CNTR15_CTN1_MASK
9195 #define TSI_CNTR15_CNTN_SHIFT TSI_CNTR15_CTN1_SHIFT
9196 #define TSI_CNTR15_CNTN(x) TSI_CNTR15_CTN1(x)
9197 #define TSI_CNTR15_CNTN1_MASK TSI_CNTR15_CTN_MASK
9198 #define TSI_CNTR15_CNTN1_SHIFT TSI_CNTR15_CTN_SHIFT
9199 #define TSI_CNTR15_CNTN1(x) TSI_CNTR15_CTN(x)
9200 
9201 /**
9202  * @}
9203  */ /* end of group Backward_Compatibility_Symbols */
9204 
9205 
9206 #endif /* #if !defined(MK60DZ10_H_) */
9207 
9208 /* MK60DZ10.h, eof. */
CAN0_Wake_Up_IRQn
CAN0 wake up interrupt.
Definition: MK60D10.h:130
DMA10_IRQn
DMA Channel 10 Transfer Complete.
Definition: MK60D10.h:106
DMA8_IRQn
DMA Channel 8 Transfer Complete.
Definition: MK60D10.h:104
CMP0_IRQn
CMP0 interrupt.
Definition: MK60D10.h:155
Reserved108_IRQn
Reserved interrupt 108.
Definition: MK60D10.h:188
I2S_Type::FCSR
__IO uint32_t FCSR
I2S FIFO Control/Status Register, offset: 0x2C.
Definition: MK60DZ10.h:4826
UART0_RX_TX_IRQn
UART0 Receive/Transmit interrupt.
Definition: MK60D10.h:141
RNG_IRQn
RNGB Interrupt.
Definition: MK60D10.h:119
PIT1_IRQn
PIT timer channel 1 interrupt.
Definition: MK60D10.h:165
DAC0_IRQn
DAC0 interrupt.
Definition: MK60D10.h:177
I2S_Type::RCR
__IO uint32_t RCR
I2S Receive Configuration Register, offset: 0x20.
Definition: MK60DZ10.h:4823
LPTimer_IRQn
LPTimer interrupt.
Definition: MK60D10.h:181
I2S_Type::RMSK
__IO uint32_t RMSK
I2S Receive Time Slot Mask Register, offset: 0x4C.
Definition: MK60DZ10.h:4833
PDB0_IRQn
PDB0 Interrupt.
Definition: MK60D10.h:168
MPU_Type
MPU - Register Layout Typedef.
Definition: MK60D10.h:5686
OSC_Type
OSC - Register Layout Typedef.
Definition: MK60D10.h:5989
FTFL_Type
FTFL - Register Layout Typedef.
Definition: MK60D10.h:3945
CMT_IRQn
CMT interrupt.
Definition: MK60D10.h:161
NV_Type
NV - Register Layout Typedef.
Definition: MK60D10.h:5858
Reserved60_IRQn
Reserved interrupt 60.
Definition: MK60DZ10.h:141
CMP1_IRQn
CMP1 interrupt.
Definition: MK60D10.h:156
I2C0_IRQn
I2C0 interrupt.
Definition: MK60D10.h:120
ENET_Type
ENET - Register Layout Typedef.
Definition: MK60D10.h:3112
CAN_Type::IMASK2
__IO uint32_t IMASK2
Interrupt Masks 2 Register, offset: 0x24.
Definition: MK60DZ10.h:1493
UART3_RX_TX_IRQn
UART3 Receive/Transmit interrupt.
Definition: MK60D10.h:147
USB_Type
USB - Register Layout Typedef.
Definition: MK60D10.h:8702
DMA3_IRQn
DMA Channel 3 Transfer Complete.
Definition: MK60D10.h:99
LLWU_Type
LLWU - Register Layout Typedef.
Definition: MK60D10.h:5145
CRC_Type
CRC - Register Layout Typedef.
Definition: MK60D10.h:2176
Reserved118_IRQn
Reserved interrupt 118.
Definition: MK60D10.h:198
MCG_IRQn
MCG Interrupt.
Definition: MK60D10.h:180
I2S_Type::ACADD
__IO uint32_t ACADD
I2S AC97 Command Address Register, offset: 0x3C.
Definition: MK60DZ10.h:4829
I2S_Type::TCR
__IO uint32_t TCR
I2S Transmit Configuration Register, offset: 0x1C.
Definition: MK60DZ10.h:4822
SDHC_Type
SDHC - Register Layout Typedef.
Definition: MK60D10.h:6891
LVD_LVW_IRQn
Low Voltage Detect, Low Voltage Warning.
Definition: MK60D10.h:116
I2S_Type::RX1
__IO uint32_t RX1
I2S Receive Data Registers 1, offset: 0xC.
Definition: MK60DZ10.h:4818
RNG_Type::VER
__I uint32_t VER
RNGB Version ID Register, offset: 0x0.
Definition: MK60DZ10.h:6574
CAN0_Error_IRQn
CAN0 error interrupt.
Definition: MK60D10.h:127
SPI2_IRQn
SPI2 Interrupt.
Definition: MK60D10.h:124
RTC_Type
RTC - Register Layout Typedef.
Definition: MK60D10.h:6730
MCG_Type
MCG - Register Layout Typedef.
Definition: MK60D10.h:5418
CAN0_Rx_Warning_IRQn
CAN0 Rx warning interrupt.
Definition: MK60D10.h:129
CAN1_ORed_Message_buffer_IRQn
CAN1 OR&#39;d message buffers interrupt.
Definition: MK60D10.h:133
CAN1_Tx_Warning_IRQn
CAN1 Tx warning interrupt.
Definition: MK60D10.h:136
Reserved102_IRQn
Reserved interrupt 102.
Definition: MK60D10.h:182
CAN0_Tx_Warning_IRQn
CAN0 Tx warning interrupt.
Definition: MK60D10.h:128
I2S_Type::TMSK
__IO uint32_t TMSK
I2S Transmit Time Slot Mask Register, offset: 0x48.
Definition: MK60DZ10.h:4832
LLWU_Type::CS
__IO uint8_t CS
LLWU Control and Status Register, offset: 0x8.
Definition: MK60DZ10.h:5163
PORTC_IRQn
Port C interrupt.
Definition: MK60D10.h:185
Reserved117_IRQn
Reserved interrupt 117.
Definition: MK60D10.h:197
RNG_Type::CMD
__IO uint32_t CMD
RNGB Command Register, offset: 0x4.
Definition: MK60DZ10.h:6575
PMC_Type
PMC - Register Layout Typedef.
Definition: MK60D10.h:6257
MCG_Type::ATC
__IO uint8_t ATC
MCG Auto Trim Control Register, offset: 0x8.
Definition: MK60DZ10.h:5497
DMA12_IRQn
DMA Channel 12 Transfer Complete.
Definition: MK60D10.h:108
Reserved113_IRQn
Reserved interrupt 113.
Definition: MK60D10.h:193
ENET_Receive_IRQn
Ethernet MAC Receive Interrupt.
Definition: MK60D10.h:173
DAC1_IRQn
DAC1 interrupt.
Definition: MK60D10.h:178
UART_Type
UART - Register Layout Typedef.
Definition: MK60D10.h:8221
I2S_Type::ACDAT
__IO uint32_t ACDAT
I2S AC97 Command Data Register, offset: 0x40.
Definition: MK60DZ10.h:4830
PIT2_IRQn
PIT timer channel 2 interrupt.
Definition: MK60D10.h:166
CMT_Type
CMT - Register Layout Typedef.
Definition: MK60D10.h:2061
SIM_Type::FCFG1
__I uint32_t FCFG1
Flash Configuration Register 1, offset: 0x104C.
Definition: MK60DZ10.h:7304
SPI_Type
SPI - Register Layout Typedef.
Definition: MK60D10.h:7742
DMA13_IRQn
DMA Channel 13 Transfer Complete.
Definition: MK60D10.h:109
I2S_Type::ACNT
__IO uint32_t ACNT
I2S AC97 Control Register, offset: 0x38.
Definition: MK60DZ10.h:4828
MCM_IRQn
Normal Interrupt.
Definition: MK60D10.h:113
CAN1_Rx_Warning_IRQn
CAN1 Rx warning interrupt.
Definition: MK60D10.h:137
PIT3_IRQn
PIT timer channel 3 interrupt.
Definition: MK60D10.h:167
DMAMUX_Type
DMAMUX - Register Layout Typedef.
Definition: MK60D10.h:3062
FB_Type
FB - Register Layout Typedef.
Definition: MK60D10.h:3685
PORTA_IRQn
Port A interrupt.
Definition: MK60D10.h:183
DMA11_IRQn
DMA Channel 11 Transfer Complete.
Definition: MK60D10.h:107
Reserved111_IRQn
Reserved interrupt 111.
Definition: MK60D10.h:191
Reserved110_IRQn
Reserved interrupt 110.
Definition: MK60DZ10.h:191
DMA0_IRQn
DMA Channel 0 Transfer Complete.
Definition: MK60D10.h:96
ENET_1588_Timer_IRQn
Ethernet MAC IEEE 1588 Timer Interrupt.
Definition: MK60D10.h:171
MC_Type::SRSH
__I uint8_t SRSH
System Reset Status Register High, offset: 0x0.
Definition: MK60DZ10.h:5406
AXBS_Type
AXBS - Register Layout Typedef.
Definition: MK60D10.h:1372
SIM_Type::SOPT6
__IO uint32_t SOPT6
System Options Register 6, offset: 0x1014.
Definition: MK60DZ10.h:7291
FTFL_IRQn
FTFL Interrupt.
Definition: MK60D10.h:114
RTC_IRQn
RTC interrupt.
Definition: MK60D10.h:162
I2S_Type::ACCDIS
__IO uint32_t ACCDIS
I2S AC97 Channel Disable Register, offset: 0x58.
Definition: MK60DZ10.h:4836
RNG_Type::ESR
__I uint32_t ESR
RNGB Error Status Register, offset: 0x10.
Definition: MK60DZ10.h:6578
UART3_ERR_IRQn
UART3 Error interrupt.
Definition: MK60D10.h:148
I2C1_IRQn
I2C1 interrupt.
Definition: MK60D10.h:121
RNG_Type
RNG - Register Layout Typedef.
Definition: MK60D10.h:6649
DMA1_IRQn
DMA Channel 1 Transfer Complete.
Definition: MK60D10.h:97
CMP2_IRQn
CMP2 interrupt.
Definition: MK60D10.h:157
RFVBAT_Type
RFVBAT - Register Layout Typedef.
Definition: MK60D10.h:6594
I2S_Type::ATAG
__IO uint32_t ATAG
I2S AC97 Tag Register, offset: 0x44.
Definition: MK60DZ10.h:4831
Read_Collision_IRQn
Read Collision Interrupt.
Definition: MK60D10.h:115
Reserved114_IRQn
Reserved interrupt 114.
Definition: MK60D10.h:194
PIT0_IRQn
PIT timer channel 0 interrupt.
Definition: MK60D10.h:164
DAC_Type
DAC - Register Layout Typedef.
Definition: MK60D10.h:2344
TSI_Type
TSI - Register Layout Typedef.
Definition: MK60D10.h:8011
CMP_Type
CMP - Register Layout Typedef.
Definition: MK60D10.h:1950
FTM2_IRQn
FTM2 fault, overflow and channels interrupt.
Definition: MK60D10.h:160
DMA9_IRQn
DMA Channel 9 Transfer Complete.
Definition: MK60D10.h:105
I2S_Type::RX0
__IO uint32_t RX0
I2S Receive Data Registers 0, offset: 0x8.
Definition: MK60DZ10.h:4817
CAU_Type
CAU - Register Layout Typedef.
Definition: MK60D10.h:1812
I2S_Type::ACCST
__I uint32_t ACCST
I2S AC97 Channel Status Register, offset: 0x50.
Definition: MK60DZ10.h:4834
Reserved119_IRQn
Reserved interrupt 119.
Definition: MK60D10.h:199
SIM_Type
SIM - Register Layout Typedef.
Definition: MK60D10.h:7328
__IO
#define __IO
Definition: core_cm0.h:189
I2S_Type::TX0
__IO uint32_t TX0
I2S Transmit Data Registers 0, offset: 0x0.
Definition: MK60DZ10.h:4815
GPIO_Type
GPIO - Register Layout Typedef.
Definition: MK60D10.h:4605
MC_Type
MC - Register Layout Typedef.
Definition: MK60DZ10.h:5405
MCM_Type::SRAMAP
__IO uint32_t SRAMAP
SRAM arbitration and protection, offset: 0xC.
Definition: MK60DZ10.h:5632
EWM_Type
EWM - Register Layout Typedef.
Definition: MK60D10.h:3613
Watchdog_IRQn
WDOG Interrupt.
Definition: MK60D10.h:118
DMA15_IRQn
DMA Channel 15 Transfer Complete.
Definition: MK60D10.h:111
DMA5_IRQn
DMA Channel 5 Transfer Complete.
Definition: MK60D10.h:101
UART0_ERR_IRQn
UART0 Error interrupt.
Definition: MK60D10.h:142
VREF_Type
VREF - Register Layout Typedef.
Definition: MK60D10.h:9134
UART1_ERR_IRQn
UART1 Error interrupt.
Definition: MK60D10.h:144
I2S_Type::ISR
__IO uint32_t ISR
I2S Interrupt Status Register, offset: 0x14.
Definition: MK60DZ10.h:4820
UART5_RX_TX_IRQn
UART5 Receive/Transmit interrupt.
Definition: MK60D10.h:151
__O
#define __O
Definition: core_cm0.h:188
I2S_Type
I2S - Register Layout Typedef.
Definition: MK60D10.h:4849
CAN1_Wake_Up_IRQn
CAN1 wake up interrupt.
Definition: MK60D10.h:138
I2S_Type::RCCR
__IO uint32_t RCCR
I2S Receive Clock Control Registers, offset: 0x28.
Definition: MK60DZ10.h:4825
ADC_Type
ADC - Register Layout Typedef.
Definition: MK60D10.h:266
UART2_ERR_IRQn
UART2 Error interrupt.
Definition: MK60D10.h:146
MC_Type::PMCTRL
__IO uint8_t PMCTRL
Power Mode Control Register, offset: 0x3.
Definition: MK60DZ10.h:5409
I2S_Type::IER
__IO uint32_t IER
I2S Interrupt Enable Register, offset: 0x18.
Definition: MK60DZ10.h:4821
UART2_RX_TX_IRQn
UART2 Receive/Transmit interrupt.
Definition: MK60D10.h:145
PIT_Type
PIT - Register Layout Typedef.
Definition: MK60D10.h:6185
CAN0_Bus_Off_IRQn
CAN0 bus off interrupt.
Definition: MK60D10.h:126
USB0_IRQn
USB0 interrupt.
Definition: MK60D10.h:169
I2S_Type::TCCR
__IO uint32_t TCCR
I2S Transmit Clock Control Registers, offset: 0x24.
Definition: MK60DZ10.h:4824
IRQn_Type
IRQn_Type
Definition: ADuCRF101.h:69
RNG_Type::OUT
__I uint32_t OUT
RNGB Output FIFO, offset: 0x14.
Definition: MK60DZ10.h:6579
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
LLWU_Type::F3
__IO uint8_t F3
LLWU Flag 3 Register, offset: 0x7.
Definition: MK60DZ10.h:5162
Reserved51_IRQn
Reserved interrupt 51.
Definition: MK60DZ10.h:132
DMA2_IRQn
DMA Channel 2 Transfer Complete.
Definition: MK60D10.h:98
UART1_RX_TX_IRQn
UART1 Receive/Transmit interrupt.
Definition: MK60D10.h:143
Reserved116_IRQn
Reserved interrupt 116.
Definition: MK60D10.h:196
PORTB_IRQn
Port B interrupt.
Definition: MK60D10.h:184
MC_Type::SRSL
__I uint8_t SRSL
System Reset Status Register Low, offset: 0x1.
Definition: MK60DZ10.h:5407
CAN1_Bus_Off_IRQn
CAN1 bus off interrupt.
Definition: MK60D10.h:134
CAN0_ORed_Message_buffer_IRQn
CAN0 OR&#39;d message buffers interrupt.
Definition: MK60D10.h:125
I2S_Type::CR
__IO uint32_t CR
I2S Control Register, offset: 0x10.
Definition: MK60DZ10.h:4819
TSI_Type::STATUS
__IO uint32_t STATUS
Status Register, offset: 0xC.
Definition: MK60DZ10.h:7890
DMA_Type
DMA - Register Layout Typedef.
Definition: MK60D10.h:2447
Reserved112_IRQn
Reserved interrupt 112.
Definition: MK60D10.h:192
DMA14_IRQn
DMA Channel 14 Transfer Complete.
Definition: MK60D10.h:110
TSI0_IRQn
TSI0 Interrupt.
Definition: MK60D10.h:179
CAN_Type::IFLAG2
__IO uint32_t IFLAG2
Interrupt Flags 2 Register, offset: 0x2C.
Definition: MK60DZ10.h:1495
I2S0_IRQn
I2S0 Interrupt.
Definition: MK60DZ10.h:176
Reserved52_IRQn
Reserved interrupt 52.
Definition: MK60DZ10.h:133
ENET_Error_IRQn
Ethernet MAC Error and miscelaneous Interrupt.
Definition: MK60D10.h:174
FTM1_IRQn
FTM1 fault, overflow and channels interrupt.
Definition: MK60D10.h:159
DMA6_IRQn
DMA Channel 6 Transfer Complete.
Definition: MK60D10.h:102
__I
#define __I
Definition: core_cm0.h:186
DMA_Error_IRQn
DMA Error Interrupt.
Definition: MK60D10.h:112
WDOG_Type
WDOG - Register Layout Typedef.
Definition: MK60D10.h:9195
FMC_Type
FMC - Register Layout Typedef.
Definition: MK60D10.h:3794
FTM0_IRQn
FTM0 fault, overflow and channels interrupt.
Definition: MK60D10.h:158
IRQn
IRQn
Interrupt Number Definitions.
Definition: MK60D10.h:83
RFSYS_Type
RFSYS - Register Layout Typedef.
Definition: MK60D10.h:6539
USBDCD_Type
USBDCD - Register Layout Typedef.
Definition: MK60D10.h:9035
LPTMR_Type
LPTMR - Register Layout Typedef.
Definition: MK60D10.h:5340
PORTD_IRQn
Port D interrupt.
Definition: MK60D10.h:186
Reserved115_IRQn
Reserved interrupt 115.
Definition: MK60D10.h:195
Reserved109_IRQn
Reserved interrupt 109.
Definition: MK60D10.h:189
UART4_ERR_IRQn
UART4 Error interrupt.
Definition: MK60D10.h:150
UART4_RX_TX_IRQn
UART4 Receive/Transmit interrupt.
Definition: MK60D10.h:149
UART5_ERR_IRQn
UART5 Error interrupt.
Definition: MK60D10.h:152
PORT_Type
PORT - Register Layout Typedef.
Definition: MK60D10.h:6332
CAN1_Error_IRQn
CAN1 error interrupt.
Definition: MK60D10.h:135
CAN_Type
CAN - Register Layout Typedef.
Definition: MK60D10.h:1488
ADC1_IRQn
ADC1 interrupt.
Definition: MK60D10.h:154
Reserved83_IRQn
Reserved interrupt 83.
Definition: MK60DZ10.h:164
ENET_Transmit_IRQn
Ethernet MAC Transmit Interrupt.
Definition: MK60D10.h:172
FTM_Type
FTM - Register Layout Typedef.
Definition: MK60D10.h:4126
USBDCD_IRQn
USBDCD Interrupt.
Definition: MK60D10.h:170
SDHC_IRQn
SDHC Interrupt.
Definition: MK60D10.h:176
I2S_Type::TX1
__IO uint32_t TX1
I2S Transmit Data Registers 1, offset: 0x4.
Definition: MK60DZ10.h:4816
MC_Type::PMPROT
__IO uint8_t PMPROT
Power Mode Protection Register, offset: 0x2.
Definition: MK60DZ10.h:5408
system_MK60DZ10.h
Device specific configuration file for MK60DZ10 (header file)
PORTE_IRQn
Port E interrupt.
Definition: MK60D10.h:187
LLW_IRQn
Low Leakage Wakeup.
Definition: MK60D10.h:117
DMA7_IRQn
DMA Channel 7 Transfer Complete.
Definition: MK60D10.h:103
DMA4_IRQn
DMA Channel 4 Transfer Complete.
Definition: MK60D10.h:100
PDB_Type
PDB - Register Layout Typedef.
Definition: MK60D10.h:6044
I2C_Type
I2C - Register Layout Typedef.
Definition: MK60D10.h:4692
AIPS_Type
AIPS - Register Layout Typedef.
Definition: MK60D10.h:487
Reserved59_IRQn
Reserved interrupt 59.
Definition: MK60D10.h:139
MCM_Type
MCM - Register Layout Typedef.
Definition: MK60D10.h:5585
I2S_Type::ACCEN
__IO uint32_t ACCEN
I2S AC97 Channel Enable Register, offset: 0x54.
Definition: MK60DZ10.h:4835
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